| T790 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3371474353 |
|
|
Jul 02 08:04:14 AM PDT 24 |
Jul 02 08:09:17 AM PDT 24 |
2927081220 ps |
| T791 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.4292774632 |
|
|
Jul 02 08:03:37 AM PDT 24 |
Jul 02 08:03:49 AM PDT 24 |
1316668950 ps |
| T792 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3010588184 |
|
|
Jul 02 08:03:22 AM PDT 24 |
Jul 02 08:03:41 AM PDT 24 |
49176457 ps |
| T793 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1031249384 |
|
|
Jul 02 08:04:47 AM PDT 24 |
Jul 02 08:05:04 AM PDT 24 |
1758775727 ps |
| T794 |
/workspace/coverage/default/32.sram_ctrl_alert_test.4208094661 |
|
|
Jul 02 08:04:44 AM PDT 24 |
Jul 02 08:04:52 AM PDT 24 |
17042618 ps |
| T795 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3704811668 |
|
|
Jul 02 08:03:50 AM PDT 24 |
Jul 02 08:03:58 AM PDT 24 |
1157945118 ps |
| T796 |
/workspace/coverage/default/9.sram_ctrl_smoke.3065549874 |
|
|
Jul 02 08:03:57 AM PDT 24 |
Jul 02 08:04:09 AM PDT 24 |
230639059 ps |
| T797 |
/workspace/coverage/default/17.sram_ctrl_smoke.1105951052 |
|
|
Jul 02 08:04:00 AM PDT 24 |
Jul 02 08:05:41 AM PDT 24 |
3594763016 ps |
| T798 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3028903462 |
|
|
Jul 02 08:04:22 AM PDT 24 |
Jul 02 08:04:37 AM PDT 24 |
19822979 ps |
| T799 |
/workspace/coverage/default/2.sram_ctrl_regwen.96370437 |
|
|
Jul 02 08:03:18 AM PDT 24 |
Jul 02 08:28:07 AM PDT 24 |
70732395506 ps |
| T800 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3542227718 |
|
|
Jul 02 08:03:39 AM PDT 24 |
Jul 02 08:03:55 AM PDT 24 |
3622377504 ps |
| T801 |
/workspace/coverage/default/2.sram_ctrl_bijection.511810496 |
|
|
Jul 02 08:03:23 AM PDT 24 |
Jul 02 08:04:02 AM PDT 24 |
1859107444 ps |
| T802 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.726125771 |
|
|
Jul 02 08:05:33 AM PDT 24 |
Jul 02 08:05:38 AM PDT 24 |
77935188 ps |
| T803 |
/workspace/coverage/default/0.sram_ctrl_partial_access.336449510 |
|
|
Jul 02 08:03:18 AM PDT 24 |
Jul 02 08:05:29 AM PDT 24 |
2896095843 ps |
| T804 |
/workspace/coverage/default/21.sram_ctrl_regwen.1105528501 |
|
|
Jul 02 08:04:01 AM PDT 24 |
Jul 02 08:26:14 AM PDT 24 |
3663013439 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1547218998 |
|
|
Jul 02 08:03:58 AM PDT 24 |
Jul 02 08:07:14 AM PDT 24 |
2601384060 ps |
| T806 |
/workspace/coverage/default/3.sram_ctrl_executable.2891387121 |
|
|
Jul 02 08:03:31 AM PDT 24 |
Jul 02 08:23:36 AM PDT 24 |
42220060318 ps |
| T807 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2698175767 |
|
|
Jul 02 08:03:49 AM PDT 24 |
Jul 02 08:05:14 AM PDT 24 |
427293131 ps |
| T808 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2995117580 |
|
|
Jul 02 08:05:22 AM PDT 24 |
Jul 02 08:05:33 AM PDT 24 |
818867175 ps |
| T809 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.767540424 |
|
|
Jul 02 08:05:26 AM PDT 24 |
Jul 02 08:10:58 AM PDT 24 |
3478457312 ps |
| T810 |
/workspace/coverage/default/20.sram_ctrl_smoke.2954284118 |
|
|
Jul 02 08:04:03 AM PDT 24 |
Jul 02 08:04:31 AM PDT 24 |
711142985 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_executable.818633156 |
|
|
Jul 02 08:04:47 AM PDT 24 |
Jul 02 08:16:41 AM PDT 24 |
4359592330 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3260741216 |
|
|
Jul 02 08:03:40 AM PDT 24 |
Jul 02 08:09:07 AM PDT 24 |
8355114763 ps |
| T813 |
/workspace/coverage/default/34.sram_ctrl_executable.2344492900 |
|
|
Jul 02 08:04:45 AM PDT 24 |
Jul 02 08:05:56 AM PDT 24 |
1385508455 ps |
| T814 |
/workspace/coverage/default/45.sram_ctrl_partial_access.455703838 |
|
|
Jul 02 08:05:32 AM PDT 24 |
Jul 02 08:06:05 AM PDT 24 |
396820136 ps |
| T815 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.558156806 |
|
|
Jul 02 08:05:53 AM PDT 24 |
Jul 02 08:05:58 AM PDT 24 |
138067117 ps |
| T816 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2217909367 |
|
|
Jul 02 08:03:58 AM PDT 24 |
Jul 02 08:10:31 AM PDT 24 |
14681004009 ps |
| T817 |
/workspace/coverage/default/7.sram_ctrl_executable.3120750613 |
|
|
Jul 02 08:03:39 AM PDT 24 |
Jul 02 08:31:14 AM PDT 24 |
71528339200 ps |
| T818 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2077624072 |
|
|
Jul 02 08:05:45 AM PDT 24 |
Jul 02 08:10:02 AM PDT 24 |
2592634852 ps |
| T819 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.939319087 |
|
|
Jul 02 08:04:30 AM PDT 24 |
Jul 02 08:14:42 AM PDT 24 |
5161950182 ps |
| T820 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3470268561 |
|
|
Jul 02 08:05:04 AM PDT 24 |
Jul 02 08:05:16 AM PDT 24 |
2444839580 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.840179332 |
|
|
Jul 02 08:03:37 AM PDT 24 |
Jul 02 08:03:43 AM PDT 24 |
28092373 ps |
| T822 |
/workspace/coverage/default/34.sram_ctrl_stress_all.42126556 |
|
|
Jul 02 08:04:46 AM PDT 24 |
Jul 02 08:47:07 AM PDT 24 |
17174674839 ps |
| T823 |
/workspace/coverage/default/6.sram_ctrl_regwen.2272713741 |
|
|
Jul 02 08:03:53 AM PDT 24 |
Jul 02 08:15:14 AM PDT 24 |
41720076423 ps |
| T824 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3771474031 |
|
|
Jul 02 08:05:19 AM PDT 24 |
Jul 02 08:05:33 AM PDT 24 |
3500466455 ps |
| T825 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.843787777 |
|
|
Jul 02 08:04:09 AM PDT 24 |
Jul 02 08:08:17 AM PDT 24 |
19490157224 ps |
| T826 |
/workspace/coverage/default/8.sram_ctrl_bijection.43623097 |
|
|
Jul 02 08:03:30 AM PDT 24 |
Jul 02 08:04:49 AM PDT 24 |
4184927688 ps |
| T827 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2436068081 |
|
|
Jul 02 08:04:42 AM PDT 24 |
Jul 02 08:08:42 AM PDT 24 |
3240528573 ps |
| T828 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.807409888 |
|
|
Jul 02 08:03:24 AM PDT 24 |
Jul 02 08:18:08 AM PDT 24 |
6744502159 ps |
| T829 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.1574409217 |
|
|
Jul 02 08:04:41 AM PDT 24 |
Jul 02 08:04:56 AM PDT 24 |
2386075762 ps |
| T830 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1698632036 |
|
|
Jul 02 08:04:01 AM PDT 24 |
Jul 02 08:22:09 AM PDT 24 |
14190912234 ps |
| T831 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1845907782 |
|
|
Jul 02 08:03:57 AM PDT 24 |
Jul 02 08:04:08 AM PDT 24 |
94485447 ps |
| T832 |
/workspace/coverage/default/32.sram_ctrl_partial_access.654814650 |
|
|
Jul 02 08:04:38 AM PDT 24 |
Jul 02 08:04:50 AM PDT 24 |
232991840 ps |
| T833 |
/workspace/coverage/default/44.sram_ctrl_regwen.424293111 |
|
|
Jul 02 08:05:25 AM PDT 24 |
Jul 02 08:14:12 AM PDT 24 |
48324771785 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2586544259 |
|
|
Jul 02 08:04:00 AM PDT 24 |
Jul 02 08:04:10 AM PDT 24 |
43761169 ps |
| T835 |
/workspace/coverage/default/21.sram_ctrl_partial_access.4064503200 |
|
|
Jul 02 08:04:12 AM PDT 24 |
Jul 02 08:04:27 AM PDT 24 |
47139189 ps |
| T836 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3466699431 |
|
|
Jul 02 08:03:31 AM PDT 24 |
Jul 02 08:04:29 AM PDT 24 |
107660168 ps |
| T837 |
/workspace/coverage/default/19.sram_ctrl_smoke.2238199076 |
|
|
Jul 02 08:04:08 AM PDT 24 |
Jul 02 08:04:31 AM PDT 24 |
165317735 ps |
| T838 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3095395564 |
|
|
Jul 02 08:05:32 AM PDT 24 |
Jul 02 08:11:34 AM PDT 24 |
74269225096 ps |
| T839 |
/workspace/coverage/default/39.sram_ctrl_partial_access.1673084030 |
|
|
Jul 02 08:05:06 AM PDT 24 |
Jul 02 08:05:33 AM PDT 24 |
211712136 ps |
| T840 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2648077941 |
|
|
Jul 02 08:05:25 AM PDT 24 |
Jul 02 08:05:29 AM PDT 24 |
43703547 ps |
| T841 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3410542373 |
|
|
Jul 02 08:03:54 AM PDT 24 |
Jul 02 08:06:01 AM PDT 24 |
591837445 ps |
| T842 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.4134974230 |
|
|
Jul 02 08:03:57 AM PDT 24 |
Jul 02 08:04:30 AM PDT 24 |
176318325 ps |
| T843 |
/workspace/coverage/default/15.sram_ctrl_regwen.853380232 |
|
|
Jul 02 08:03:59 AM PDT 24 |
Jul 02 08:21:04 AM PDT 24 |
31307738164 ps |
| T844 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.205725412 |
|
|
Jul 02 08:05:26 AM PDT 24 |
Jul 02 08:05:46 AM PDT 24 |
84059291 ps |
| T845 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.419745831 |
|
|
Jul 02 08:05:50 AM PDT 24 |
Jul 02 08:06:07 AM PDT 24 |
857730825 ps |
| T846 |
/workspace/coverage/default/27.sram_ctrl_alert_test.2865634741 |
|
|
Jul 02 08:04:13 AM PDT 24 |
Jul 02 08:04:26 AM PDT 24 |
21082740 ps |
| T847 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.658629645 |
|
|
Jul 02 08:03:57 AM PDT 24 |
Jul 02 08:04:05 AM PDT 24 |
116028251 ps |
| T848 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3592512777 |
|
|
Jul 02 08:04:45 AM PDT 24 |
Jul 02 08:22:59 AM PDT 24 |
29452056638 ps |
| T849 |
/workspace/coverage/default/8.sram_ctrl_regwen.776510691 |
|
|
Jul 02 08:03:43 AM PDT 24 |
Jul 02 08:31:32 AM PDT 24 |
24195851004 ps |
| T850 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1165806836 |
|
|
Jul 02 08:04:41 AM PDT 24 |
Jul 02 08:12:56 AM PDT 24 |
5833152689 ps |
| T851 |
/workspace/coverage/default/30.sram_ctrl_regwen.819438531 |
|
|
Jul 02 08:04:28 AM PDT 24 |
Jul 02 08:25:42 AM PDT 24 |
28604593305 ps |
| T852 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3904581483 |
|
|
Jul 02 08:04:44 AM PDT 24 |
Jul 02 08:16:09 AM PDT 24 |
5859696569 ps |
| T853 |
/workspace/coverage/default/24.sram_ctrl_executable.974205832 |
|
|
Jul 02 08:04:06 AM PDT 24 |
Jul 02 08:16:57 AM PDT 24 |
13966744104 ps |
| T854 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3401986718 |
|
|
Jul 02 08:04:24 AM PDT 24 |
Jul 02 08:13:21 AM PDT 24 |
6482953866 ps |
| T855 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.8623170 |
|
|
Jul 02 08:04:07 AM PDT 24 |
Jul 02 08:06:30 AM PDT 24 |
1393341983 ps |
| T856 |
/workspace/coverage/default/28.sram_ctrl_stress_all.4239659311 |
|
|
Jul 02 08:04:34 AM PDT 24 |
Jul 02 09:14:18 AM PDT 24 |
39754279395 ps |
| T857 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1492901217 |
|
|
Jul 02 08:04:15 AM PDT 24 |
Jul 02 08:10:46 AM PDT 24 |
40900621328 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_alert_test.24487410 |
|
|
Jul 02 08:04:17 AM PDT 24 |
Jul 02 08:04:31 AM PDT 24 |
11753274 ps |
| T859 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1593284833 |
|
|
Jul 02 08:04:59 AM PDT 24 |
Jul 02 08:27:51 AM PDT 24 |
18054778027 ps |
| T860 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.457693089 |
|
|
Jul 02 08:05:09 AM PDT 24 |
Jul 02 08:15:10 AM PDT 24 |
6269229840 ps |
| T861 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2279765984 |
|
|
Jul 02 08:03:30 AM PDT 24 |
Jul 02 08:03:47 AM PDT 24 |
2289922956 ps |
| T862 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2808604630 |
|
|
Jul 02 08:03:43 AM PDT 24 |
Jul 02 08:03:54 AM PDT 24 |
812164997 ps |
| T863 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1201952 |
|
|
Jul 02 08:04:05 AM PDT 24 |
Jul 02 08:18:39 AM PDT 24 |
42684751472 ps |
| T864 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2823758963 |
|
|
Jul 02 08:04:13 AM PDT 24 |
Jul 02 08:15:29 AM PDT 24 |
2527399887 ps |
| T865 |
/workspace/coverage/default/21.sram_ctrl_bijection.2409887717 |
|
|
Jul 02 08:04:12 AM PDT 24 |
Jul 02 08:05:02 AM PDT 24 |
2306495486 ps |
| T866 |
/workspace/coverage/default/0.sram_ctrl_executable.3636682225 |
|
|
Jul 02 08:03:18 AM PDT 24 |
Jul 02 08:22:47 AM PDT 24 |
24149297600 ps |
| T867 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.214755944 |
|
|
Jul 02 08:03:47 AM PDT 24 |
Jul 02 08:05:41 AM PDT 24 |
523950951 ps |
| T868 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2536107786 |
|
|
Jul 02 08:04:00 AM PDT 24 |
Jul 02 08:04:10 AM PDT 24 |
148633807 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1187832608 |
|
|
Jul 02 08:03:22 AM PDT 24 |
Jul 02 08:03:37 AM PDT 24 |
326628813 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.501129243 |
|
|
Jul 02 08:05:46 AM PDT 24 |
Jul 02 08:18:46 AM PDT 24 |
7943347206 ps |
| T870 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1538282160 |
|
|
Jul 02 08:04:11 AM PDT 24 |
Jul 02 08:04:24 AM PDT 24 |
41885332 ps |
| T871 |
/workspace/coverage/default/26.sram_ctrl_stress_all.4065836349 |
|
|
Jul 02 08:04:18 AM PDT 24 |
Jul 02 08:11:36 AM PDT 24 |
141731212915 ps |
| T872 |
/workspace/coverage/default/38.sram_ctrl_partial_access.932173881 |
|
|
Jul 02 08:05:03 AM PDT 24 |
Jul 02 08:05:55 AM PDT 24 |
1668040010 ps |
| T873 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2038783791 |
|
|
Jul 02 08:03:57 AM PDT 24 |
Jul 02 08:04:05 AM PDT 24 |
372828639 ps |
| T874 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3034175263 |
|
|
Jul 02 08:03:51 AM PDT 24 |
Jul 02 08:22:29 AM PDT 24 |
18005668605 ps |
| T875 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3099378366 |
|
|
Jul 02 08:04:25 AM PDT 24 |
Jul 02 08:11:32 AM PDT 24 |
2313117575 ps |
| T876 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1235588198 |
|
|
Jul 02 08:03:27 AM PDT 24 |
Jul 02 08:03:53 AM PDT 24 |
325857384 ps |
| T877 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3516445325 |
|
|
Jul 02 08:05:15 AM PDT 24 |
Jul 02 08:05:19 AM PDT 24 |
125182502 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.891444313 |
|
|
Jul 02 08:05:33 AM PDT 24 |
Jul 02 08:05:43 AM PDT 24 |
605370300 ps |
| T879 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3890265262 |
|
|
Jul 02 08:04:24 AM PDT 24 |
Jul 02 08:05:51 AM PDT 24 |
121500091 ps |
| T880 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2988698856 |
|
|
Jul 02 08:04:15 AM PDT 24 |
Jul 02 08:04:36 AM PDT 24 |
135160659 ps |
| T881 |
/workspace/coverage/default/24.sram_ctrl_smoke.2561548471 |
|
|
Jul 02 08:04:10 AM PDT 24 |
Jul 02 08:04:34 AM PDT 24 |
3844329984 ps |
| T882 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.888629648 |
|
|
Jul 02 08:04:31 AM PDT 24 |
Jul 02 08:04:46 AM PDT 24 |
202154425 ps |
| T883 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2648421954 |
|
|
Jul 02 08:05:00 AM PDT 24 |
Jul 02 08:11:38 AM PDT 24 |
5404015347 ps |
| T884 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3495565673 |
|
|
Jul 02 08:05:09 AM PDT 24 |
Jul 02 08:05:15 AM PDT 24 |
116948649 ps |
| T885 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3721499703 |
|
|
Jul 02 08:03:19 AM PDT 24 |
Jul 02 08:03:56 AM PDT 24 |
108027569 ps |
| T886 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2714543248 |
|
|
Jul 02 08:04:00 AM PDT 24 |
Jul 02 08:04:22 AM PDT 24 |
1764390698 ps |
| T887 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1975669512 |
|
|
Jul 02 08:04:30 AM PDT 24 |
Jul 02 08:05:34 AM PDT 24 |
496289194 ps |
| T888 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2239275111 |
|
|
Jul 02 08:05:44 AM PDT 24 |
Jul 02 08:05:50 AM PDT 24 |
292558873 ps |
| T889 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2563646319 |
|
|
Jul 02 08:03:41 AM PDT 24 |
Jul 02 08:04:07 AM PDT 24 |
3645036040 ps |
| T890 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2034216366 |
|
|
Jul 02 08:04:23 AM PDT 24 |
Jul 02 08:04:42 AM PDT 24 |
144659740 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3711625744 |
|
|
Jul 02 08:05:15 AM PDT 24 |
Jul 02 08:22:40 AM PDT 24 |
15254310704 ps |
| T892 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3179816002 |
|
|
Jul 02 08:04:51 AM PDT 24 |
Jul 02 08:07:02 AM PDT 24 |
169573756 ps |
| T893 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3028039870 |
|
|
Jul 02 08:03:50 AM PDT 24 |
Jul 02 08:03:59 AM PDT 24 |
95544720 ps |
| T894 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2871923169 |
|
|
Jul 02 08:05:52 AM PDT 24 |
Jul 02 08:05:58 AM PDT 24 |
161618036 ps |
| T895 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1920941899 |
|
|
Jul 02 08:03:34 AM PDT 24 |
Jul 02 08:03:43 AM PDT 24 |
61772088 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_smoke.3944157579 |
|
|
Jul 02 08:05:33 AM PDT 24 |
Jul 02 08:05:50 AM PDT 24 |
670560649 ps |
| T897 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.4216199522 |
|
|
Jul 02 08:04:12 AM PDT 24 |
Jul 02 08:04:29 AM PDT 24 |
91250556 ps |
| T898 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3549480272 |
|
|
Jul 02 08:04:02 AM PDT 24 |
Jul 02 08:04:14 AM PDT 24 |
76562310 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2818802995 |
|
|
Jul 02 08:04:27 AM PDT 24 |
Jul 02 08:11:54 AM PDT 24 |
215066818033 ps |
| T900 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1972492203 |
|
|
Jul 02 08:03:58 AM PDT 24 |
Jul 02 08:04:12 AM PDT 24 |
621287946 ps |
| T901 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1591078325 |
|
|
Jul 02 08:03:19 AM PDT 24 |
Jul 02 08:10:10 AM PDT 24 |
1631994372 ps |
| T902 |
/workspace/coverage/default/40.sram_ctrl_executable.1465199727 |
|
|
Jul 02 08:05:08 AM PDT 24 |
Jul 02 08:12:46 AM PDT 24 |
10657209128 ps |
| T903 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2527288804 |
|
|
Jul 02 08:03:56 AM PDT 24 |
Jul 02 08:16:13 AM PDT 24 |
13347799271 ps |
| T904 |
/workspace/coverage/default/49.sram_ctrl_partial_access.61619037 |
|
|
Jul 02 08:05:50 AM PDT 24 |
Jul 02 08:06:08 AM PDT 24 |
304742800 ps |
| T905 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1787441551 |
|
|
Jul 02 08:05:09 AM PDT 24 |
Jul 02 09:05:38 AM PDT 24 |
71257119868 ps |
| T906 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3652209826 |
|
|
Jul 02 08:05:31 AM PDT 24 |
Jul 02 08:05:45 AM PDT 24 |
457122294 ps |
| T907 |
/workspace/coverage/default/30.sram_ctrl_executable.663014089 |
|
|
Jul 02 08:04:31 AM PDT 24 |
Jul 02 08:05:44 AM PDT 24 |
1264008040 ps |
| T908 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.2386829343 |
|
|
Jul 02 08:04:58 AM PDT 24 |
Jul 02 08:05:15 AM PDT 24 |
517741041 ps |
| T909 |
/workspace/coverage/default/5.sram_ctrl_executable.109268013 |
|
|
Jul 02 08:03:24 AM PDT 24 |
Jul 02 08:14:59 AM PDT 24 |
10038278607 ps |
| T910 |
/workspace/coverage/default/36.sram_ctrl_bijection.960061180 |
|
|
Jul 02 08:04:51 AM PDT 24 |
Jul 02 08:05:50 AM PDT 24 |
3331783751 ps |
| T911 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2141879976 |
|
|
Jul 02 08:05:37 AM PDT 24 |
Jul 02 08:06:13 AM PDT 24 |
110175169 ps |
| T912 |
/workspace/coverage/default/30.sram_ctrl_alert_test.4258752550 |
|
|
Jul 02 08:04:36 AM PDT 24 |
Jul 02 08:04:47 AM PDT 24 |
40610400 ps |
| T913 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.597388382 |
|
|
Jul 02 08:04:08 AM PDT 24 |
Jul 02 08:04:22 AM PDT 24 |
131274920 ps |
| T914 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2103231261 |
|
|
Jul 02 08:03:38 AM PDT 24 |
Jul 02 08:29:43 AM PDT 24 |
63530806772 ps |
| T915 |
/workspace/coverage/default/31.sram_ctrl_regwen.3029920961 |
|
|
Jul 02 08:04:39 AM PDT 24 |
Jul 02 08:07:28 AM PDT 24 |
9268136793 ps |
| T916 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2746391527 |
|
|
Jul 02 08:05:40 AM PDT 24 |
Jul 02 08:05:53 AM PDT 24 |
1847400443 ps |
| T917 |
/workspace/coverage/default/37.sram_ctrl_bijection.1039622047 |
|
|
Jul 02 08:05:00 AM PDT 24 |
Jul 02 08:06:03 AM PDT 24 |
855007066 ps |
| T918 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2787279333 |
|
|
Jul 02 08:04:58 AM PDT 24 |
Jul 02 08:10:25 AM PDT 24 |
9831391509 ps |
| T919 |
/workspace/coverage/default/13.sram_ctrl_stress_all.820852938 |
|
|
Jul 02 08:03:47 AM PDT 24 |
Jul 02 09:33:05 AM PDT 24 |
11518257595 ps |
| T920 |
/workspace/coverage/default/41.sram_ctrl_bijection.1311235042 |
|
|
Jul 02 08:05:15 AM PDT 24 |
Jul 02 08:05:57 AM PDT 24 |
611968695 ps |
| T921 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3247666770 |
|
|
Jul 02 08:04:21 AM PDT 24 |
Jul 02 08:05:05 AM PDT 24 |
91780855 ps |
| T922 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2049213469 |
|
|
Jul 02 08:04:13 AM PDT 24 |
Jul 02 08:04:36 AM PDT 24 |
1328429791 ps |
| T923 |
/workspace/coverage/default/5.sram_ctrl_regwen.615965821 |
|
|
Jul 02 08:03:35 AM PDT 24 |
Jul 02 08:10:23 AM PDT 24 |
25965114364 ps |
| T924 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4097589870 |
|
|
Jul 02 08:04:02 AM PDT 24 |
Jul 02 08:04:18 AM PDT 24 |
118917146 ps |
| T925 |
/workspace/coverage/default/7.sram_ctrl_partial_access.199610055 |
|
|
Jul 02 08:03:42 AM PDT 24 |
Jul 02 08:04:00 AM PDT 24 |
2666844618 ps |
| T926 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3905735360 |
|
|
Jul 02 08:05:49 AM PDT 24 |
Jul 02 08:10:30 AM PDT 24 |
10815966561 ps |
| T927 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3642673727 |
|
|
Jul 02 08:04:14 AM PDT 24 |
Jul 02 08:04:30 AM PDT 24 |
561384020 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3375612139 |
|
|
Jul 02 08:04:30 AM PDT 24 |
Jul 02 08:39:18 AM PDT 24 |
4820668747 ps |
| T929 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1216571946 |
|
|
Jul 02 08:04:25 AM PDT 24 |
Jul 02 08:04:47 AM PDT 24 |
2103616903 ps |
| T930 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1339663396 |
|
|
Jul 02 08:03:58 AM PDT 24 |
Jul 02 08:08:48 AM PDT 24 |
3019879403 ps |
| T931 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.3429371794 |
|
|
Jul 02 08:04:15 AM PDT 24 |
Jul 02 08:22:19 AM PDT 24 |
158354505764 ps |
| T932 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3143334366 |
|
|
Jul 02 08:04:13 AM PDT 24 |
Jul 02 08:04:26 AM PDT 24 |
43342483 ps |
| T933 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2324698775 |
|
|
Jul 02 08:05:44 AM PDT 24 |
Jul 02 08:09:08 AM PDT 24 |
32013441367 ps |
| T934 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2172814771 |
|
|
Jul 02 08:04:03 AM PDT 24 |
Jul 02 08:04:15 AM PDT 24 |
85245636 ps |
| T935 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3681034976 |
|
|
Jul 02 08:04:16 AM PDT 24 |
Jul 02 08:04:37 AM PDT 24 |
685844977 ps |
| T936 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.18953863 |
|
|
Jul 02 08:04:24 AM PDT 24 |
Jul 02 08:05:06 AM PDT 24 |
190566428 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2392335614 |
|
|
Jul 02 08:02:41 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
135462693 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2742894070 |
|
|
Jul 02 08:02:34 AM PDT 24 |
Jul 02 08:02:51 AM PDT 24 |
14685913 ps |
| T69 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4038463021 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:53 AM PDT 24 |
763820668 ps |
| T70 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2471456821 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:00 AM PDT 24 |
38444723 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2784393682 |
|
|
Jul 02 08:02:42 AM PDT 24 |
Jul 02 08:03:00 AM PDT 24 |
2511056458 ps |
| T97 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3498911289 |
|
|
Jul 02 08:02:48 AM PDT 24 |
Jul 02 08:03:06 AM PDT 24 |
27086415 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1597192174 |
|
|
Jul 02 08:02:30 AM PDT 24 |
Jul 02 08:02:49 AM PDT 24 |
2213933578 ps |
| T938 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1560000218 |
|
|
Jul 02 08:02:46 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
42215850 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4128834495 |
|
|
Jul 02 08:02:34 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
178721706 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.309988079 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
113528230 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1143245415 |
|
|
Jul 02 08:02:37 AM PDT 24 |
Jul 02 08:02:56 AM PDT 24 |
220832563 ps |
| T940 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.510223596 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
126287463 ps |
| T98 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1711367469 |
|
|
Jul 02 08:02:41 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
1463091924 ps |
| T66 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.363951642 |
|
|
Jul 02 08:02:50 AM PDT 24 |
Jul 02 08:03:10 AM PDT 24 |
935856538 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3802912917 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:52 AM PDT 24 |
33152805 ps |
| T106 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3864335529 |
|
|
Jul 02 08:02:28 AM PDT 24 |
Jul 02 08:02:46 AM PDT 24 |
30079178 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1339645491 |
|
|
Jul 02 08:02:44 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
88646209 ps |
| T81 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2272973883 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:02 AM PDT 24 |
37849698 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3632948501 |
|
|
Jul 02 08:02:31 AM PDT 24 |
Jul 02 08:02:49 AM PDT 24 |
15398831 ps |
| T83 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3474106261 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:00 AM PDT 24 |
55789247 ps |
| T941 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3355928063 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:55 AM PDT 24 |
456647761 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1307205913 |
|
|
Jul 02 08:02:42 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
2195403801 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1040041248 |
|
|
Jul 02 08:02:40 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
114090355 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3022979963 |
|
|
Jul 02 08:02:39 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
395609214 ps |
| T123 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.142962089 |
|
|
Jul 02 08:02:30 AM PDT 24 |
Jul 02 08:02:47 AM PDT 24 |
449076756 ps |
| T942 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1916384353 |
|
|
Jul 02 08:02:44 AM PDT 24 |
Jul 02 08:03:04 AM PDT 24 |
127601132 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3361183707 |
|
|
Jul 02 08:02:42 AM PDT 24 |
Jul 02 08:02:59 AM PDT 24 |
78131475 ps |
| T86 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2871043947 |
|
|
Jul 02 08:02:30 AM PDT 24 |
Jul 02 08:02:51 AM PDT 24 |
5540373274 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1927807007 |
|
|
Jul 02 08:02:41 AM PDT 24 |
Jul 02 08:02:59 AM PDT 24 |
121812721 ps |
| T120 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2144111558 |
|
|
Jul 02 08:02:36 AM PDT 24 |
Jul 02 08:02:54 AM PDT 24 |
375948127 ps |
| T121 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2612665527 |
|
|
Jul 02 08:02:51 AM PDT 24 |
Jul 02 08:03:10 AM PDT 24 |
234000206 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2481027048 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:53 AM PDT 24 |
245215327 ps |
| T946 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3645269050 |
|
|
Jul 02 08:02:38 AM PDT 24 |
Jul 02 08:02:56 AM PDT 24 |
12018927 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1496657369 |
|
|
Jul 02 08:02:44 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
56217228 ps |
| T948 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.418851400 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:53 AM PDT 24 |
33274875 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.80506993 |
|
|
Jul 02 08:02:30 AM PDT 24 |
Jul 02 08:02:47 AM PDT 24 |
44764173 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3620060959 |
|
|
Jul 02 08:02:47 AM PDT 24 |
Jul 02 08:03:07 AM PDT 24 |
46817619 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3119469305 |
|
|
Jul 02 08:02:46 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
22363757 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3424920843 |
|
|
Jul 02 08:02:46 AM PDT 24 |
Jul 02 08:03:05 AM PDT 24 |
530280343 ps |
| T122 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1868201495 |
|
|
Jul 02 08:02:44 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
625771725 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1841736704 |
|
|
Jul 02 08:02:48 AM PDT 24 |
Jul 02 08:03:09 AM PDT 24 |
91221763 ps |
| T88 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1565433734 |
|
|
Jul 02 08:02:42 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
799040647 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1343502679 |
|
|
Jul 02 08:02:42 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
692641071 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.125737121 |
|
|
Jul 02 08:02:56 AM PDT 24 |
Jul 02 08:03:15 AM PDT 24 |
45246556 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.271391788 |
|
|
Jul 02 08:02:39 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
99212533 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3618354022 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:00 AM PDT 24 |
14710805 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2436219697 |
|
|
Jul 02 08:02:44 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
117383504 ps |
| T958 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2247140388 |
|
|
Jul 02 08:02:50 AM PDT 24 |
Jul 02 08:03:09 AM PDT 24 |
20662585 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1281635912 |
|
|
Jul 02 08:02:49 AM PDT 24 |
Jul 02 08:03:07 AM PDT 24 |
23207266 ps |
| T94 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2191297342 |
|
|
Jul 02 08:02:28 AM PDT 24 |
Jul 02 08:02:45 AM PDT 24 |
14212239 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.785348296 |
|
|
Jul 02 08:02:31 AM PDT 24 |
Jul 02 08:02:50 AM PDT 24 |
72396058 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2643719927 |
|
|
Jul 02 08:02:33 AM PDT 24 |
Jul 02 08:02:50 AM PDT 24 |
19366250 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3255944450 |
|
|
Jul 02 08:02:37 AM PDT 24 |
Jul 02 08:02:56 AM PDT 24 |
29895967 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4247049571 |
|
|
Jul 02 08:02:31 AM PDT 24 |
Jul 02 08:02:47 AM PDT 24 |
17322405 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1254428361 |
|
|
Jul 02 08:02:34 AM PDT 24 |
Jul 02 08:02:50 AM PDT 24 |
43121819 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1723383674 |
|
|
Jul 02 08:02:31 AM PDT 24 |
Jul 02 08:02:48 AM PDT 24 |
300572784 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2452687146 |
|
|
Jul 02 08:02:28 AM PDT 24 |
Jul 02 08:02:45 AM PDT 24 |
47659279 ps |
| T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4168905450 |
|
|
Jul 02 08:02:46 AM PDT 24 |
Jul 02 08:03:07 AM PDT 24 |
128953678 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1458760590 |
|
|
Jul 02 08:03:02 AM PDT 24 |
Jul 02 08:03:21 AM PDT 24 |
90240154 ps |
| T124 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1048285532 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:52 AM PDT 24 |
170857314 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.28862283 |
|
|
Jul 02 08:02:34 AM PDT 24 |
Jul 02 08:02:50 AM PDT 24 |
14486638 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2592560115 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:04 AM PDT 24 |
293455920 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2734716620 |
|
|
Jul 02 08:02:49 AM PDT 24 |
Jul 02 08:03:10 AM PDT 24 |
249603948 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.241129053 |
|
|
Jul 02 08:02:58 AM PDT 24 |
Jul 02 08:03:18 AM PDT 24 |
32058608 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.447317776 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:01 AM PDT 24 |
29375112 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.969424621 |
|
|
Jul 02 08:02:29 AM PDT 24 |
Jul 02 08:02:46 AM PDT 24 |
49709737 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4227474194 |
|
|
Jul 02 08:02:46 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
29821267 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1610926547 |
|
|
Jul 02 08:02:33 AM PDT 24 |
Jul 02 08:02:50 AM PDT 24 |
35837065 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4175706802 |
|
|
Jul 02 08:02:39 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
723033983 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2905114784 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:02 AM PDT 24 |
290409991 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2280971704 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:00 AM PDT 24 |
14517222 ps |
| T119 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2108663091 |
|
|
Jul 02 08:02:49 AM PDT 24 |
Jul 02 08:03:09 AM PDT 24 |
253158773 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.29074670 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
24156343 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.314099138 |
|
|
Jul 02 08:02:38 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
801434277 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3677691290 |
|
|
Jul 02 08:02:25 AM PDT 24 |
Jul 02 08:02:44 AM PDT 24 |
1471553177 ps |
| T116 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2787094272 |
|
|
Jul 02 08:02:44 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
964382626 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3613098580 |
|
|
Jul 02 08:02:47 AM PDT 24 |
Jul 02 08:03:06 AM PDT 24 |
799936855 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1075631530 |
|
|
Jul 02 08:02:37 AM PDT 24 |
Jul 02 08:02:54 AM PDT 24 |
38765033 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3463172458 |
|
|
Jul 02 08:02:26 AM PDT 24 |
Jul 02 08:02:42 AM PDT 24 |
12819050 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3825219793 |
|
|
Jul 02 08:02:48 AM PDT 24 |
Jul 02 08:03:05 AM PDT 24 |
22977333 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.233849958 |
|
|
Jul 02 08:02:34 AM PDT 24 |
Jul 02 08:02:51 AM PDT 24 |
64136941 ps |
| T986 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3700052680 |
|
|
Jul 02 08:02:47 AM PDT 24 |
Jul 02 08:03:08 AM PDT 24 |
116038231 ps |
| T117 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3608583822 |
|
|
Jul 02 08:02:30 AM PDT 24 |
Jul 02 08:02:48 AM PDT 24 |
968209976 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.390102330 |
|
|
Jul 02 08:02:36 AM PDT 24 |
Jul 02 08:02:55 AM PDT 24 |
135299388 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3443011850 |
|
|
Jul 02 08:02:43 AM PDT 24 |
Jul 02 08:03:02 AM PDT 24 |
67833006 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2876048225 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
35832382 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3221189699 |
|
|
Jul 02 08:02:54 AM PDT 24 |
Jul 02 08:03:13 AM PDT 24 |
35358033 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3978046460 |
|
|
Jul 02 08:02:41 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
66430205 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4108598568 |
|
|
Jul 02 08:02:35 AM PDT 24 |
Jul 02 08:02:52 AM PDT 24 |
77368782 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3143929558 |
|
|
Jul 02 08:02:30 AM PDT 24 |
Jul 02 08:02:51 AM PDT 24 |
131101301 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3200713504 |
|
|
Jul 02 08:02:41 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
306797680 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2733972615 |
|
|
Jul 02 08:02:42 AM PDT 24 |
Jul 02 08:02:59 AM PDT 24 |
35755507 ps |
| T125 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3771517553 |
|
|
Jul 02 08:02:48 AM PDT 24 |
Jul 02 08:03:08 AM PDT 24 |
655963537 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1014240966 |
|
|
Jul 02 08:02:57 AM PDT 24 |
Jul 02 08:03:16 AM PDT 24 |
40335872 ps |
| T997 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.107750827 |
|
|
Jul 02 08:02:47 AM PDT 24 |
Jul 02 08:03:05 AM PDT 24 |
60885306 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.514541367 |
|
|
Jul 02 08:02:53 AM PDT 24 |
Jul 02 08:03:12 AM PDT 24 |
73924130 ps |
| T999 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2545457209 |
|
|
Jul 02 08:02:51 AM PDT 24 |
Jul 02 08:03:09 AM PDT 24 |
20692269 ps |
| T128 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3308473938 |
|
|
Jul 02 08:02:47 AM PDT 24 |
Jul 02 08:03:05 AM PDT 24 |
325988588 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2079368854 |
|
|
Jul 02 08:02:38 AM PDT 24 |
Jul 02 08:02:58 AM PDT 24 |
396712090 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.598446107 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:05 AM PDT 24 |
342986048 ps |
| T1002 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.165133705 |
|
|
Jul 02 08:02:45 AM PDT 24 |
Jul 02 08:03:03 AM PDT 24 |
232692728 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3453076155 |
|
|
Jul 02 08:02:28 AM PDT 24 |
Jul 02 08:02:45 AM PDT 24 |
13816739 ps |