Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14209689

1

T1

21525

T2

7215

T5

77726

full_word

55929604

1

T1

216792

T2

49719

T3

3071

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70139013	1			T1	238317		T2	56934		T3	3071
auto[TlIntgErrCmd]	92	1			T62	3		T63	3		T64	3
auto[TlIntgErrData]	93	1			T62	4		T63	3		T64	3
auto[TlIntgErrBoth]	95	1			T62	3		T63	4		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32075282

1

T1

118845

T2

22577

T3

1024

auto[1]

38064011

1

T1

119472

T2

34357

T3

2047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6787298	1			T1	10644		T2	1974		T5	38927
auto[TlIntgErrNone]	partial	auto[1]	7422128	1			T1	10881		T2	5241		T5	38799
auto[TlIntgErrNone]	full_word	auto[0]	25287852	1			T1	108201		T2	20603		T3	1024
auto[TlIntgErrNone]	full_word	auto[1]	30641735	1			T1	108591		T2	29116		T3	2047
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T62	1		T63	1		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T62	2		T63	2		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T136	1		T137	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T138	1		T135	1		T139	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T63	2		T134	4		T138	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T62	4		T64	2		T130	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T134	1		T139	1		T140	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T63	1		T64	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T62	3		T63	1		T64	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T63	3		T64	1		T130	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T140	1		T141	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T130	1		T135	1		T141	1