Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	746756	1			T1	7919		T5	12025		T10	27
auto[1]	10540136	1			T1	5636		T2	648		T5	10307
auto[2]	614361	1			T1	5144		T5	10380		T10	11
auto[3]	10412545	1			T1	2864		T2	656		T5	8752

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14380330	1			T1	16774		T2	1069		T5	869
auto[1]	2131013	1			T1	2048		T2	108		T5	5420
auto[2]	2146948	1			T1	2489		T2	111		T5	5151
auto[3]	3655507	1			T1	252		T2	16		T5	30024

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8770097

1

T1

21535

T2

1301

T5

15

auto[1]

13543701

1

T1

28

T2

3

T5

41449

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	294358	1			T1	6516		T10	20		T20	27
auto[0]	auto[0]	auto[1]	29868	1			T1	662		T10	2		T20	3
auto[0]	auto[0]	auto[2]	29879	1			T1	670		T10	5		T20	1
auto[0]	auto[0]	auto[3]	6367	1			T1	61		T5	2		T79	45
auto[0]	auto[1]	auto[0]	3327931	1			T1	4332		T2	520		T6	336
auto[0]	auto[1]	auto[1]	343265	1			T1	795		T2	67		T5	1
auto[0]	auto[1]	auto[2]	333836	1			T1	443		T2	56		T6	39
auto[0]	auto[1]	auto[3]	70976	1			T1	60		T2	5		T5	3
auto[0]	auto[2]	auto[0]	248884	1			T1	4075		T26	946		T68	18
auto[0]	auto[2]	auto[1]	25084	1			T1	407		T5	1		T8	1
auto[0]	auto[2]	auto[2]	27349	1			T1	591		T5	1		T10	10
auto[0]	auto[2]	auto[3]	5690	1			T1	63		T5	2		T10	1
auto[0]	auto[3]	auto[0]	3282811	1			T1	1827		T2	547		T6	374
auto[0]	auto[3]	auto[1]	328154	1			T1	184		T2	41		T6	40
auto[0]	auto[3]	auto[2]	341942	1			T1	781		T2	54		T5	1
auto[0]	auto[3]	auto[3]	73703	1			T1	68		T2	11		T5	4
auto[1]	auto[0]	auto[0]	13098	1			T1	10		T5	368		T44	1
auto[1]	auto[0]	auto[1]	57449	1			T5	1804		T110	4055		T149	2
auto[1]	auto[0]	auto[2]	57518	1			T5	1789		T110	4100		T150	1
auto[1]	auto[0]	auto[3]	258219	1			T5	8062		T110	18671		T112	7390
auto[1]	auto[1]	auto[0]	3603782	1			T1	5		T5	69		T6	1
auto[1]	auto[1]	auto[1]	669961	1			T5	1772		T40	3		T42	4
auto[1]	auto[1]	auto[2]	653051	1			T1	1		T5	277		T40	2
auto[1]	auto[1]	auto[3]	1537334	1			T5	8185		T80	44840		T151	2
auto[1]	auto[2]	auto[0]	9413	1			T1	6		T5	397		T152	1
auto[1]	auto[2]	auto[1]	41261	1			T5	1683		T110	3714		T112	1030
auto[1]	auto[2]	auto[2]	46823	1			T1	2		T5	1519		T26	1
auto[1]	auto[2]	auto[3]	209857	1			T5	6777		T110	12524		T112	7908
auto[1]	auto[3]	auto[0]	3600053	1			T1	3		T2	2		T5	35
auto[1]	auto[3]	auto[1]	635971	1			T5	159		T40	1		T42	6
auto[1]	auto[3]	auto[2]	656550	1			T1	1		T2	1		T5	1564
auto[1]	auto[3]	auto[3]	1493361	1			T5	6989		T80	45153		T43	1