Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	336607331	192594	0	0
ctrl_regwen_rd_A	336607331	3214	0	0
exec_rd_A	336607331	2867	0	0
exec_regwen_rd_A	336607331	2895	0	0
readback_rd_A	336607331	1877	0	0
readback_regwen_rd_A	336607331	1538	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336607331	192594	0	0
T2	119432	5527	0	0
T3	32792	0	0	0
T4	355527	0	0	0
T5	733476	0	0	0
T6	34105	0	0	0
T9	2401	0	0	0
T10	86968	2420	0	0
T11	65469	0	0	0
T12	744	0	0	0
T25	0	2544	0	0
T40	266666	0	0	0
T45	0	759	0	0
T48	0	5567	0	0
T51	0	3485	0	0
T52	0	3295	0	0
T59	0	5314	0	0
T60	0	1692	0	0
T69	0	2731	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336607331	3214	0	0
T49	0	115	0	0
T51	171780	343	0	0
T65	0	47	0	0
T67	0	11	0	0
T69	63871	0	0	0
T70	29667	0	0	0
T71	0	52	0	0
T107	290049	0	0	0
T108	297182	0	0	0
T109	290804	0	0	0
T115	0	189	0	0
T116	0	146	0	0
T117	0	134	0	0
T118	0	368	0	0
T119	0	476	0	0
T120	106742	0	0	0
T121	2832	0	0	0
T122	52762	0	0	0
T123	35796	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336607331	2867	0	0
T49	0	154	0	0
T51	171780	262	0	0
T65	0	34	0	0
T67	0	8	0	0
T69	63871	0	0	0
T70	29667	0	0	0
T71	0	32	0	0
T107	290049	0	0	0
T108	297182	0	0	0
T109	290804	0	0	0
T115	0	119	0	0
T116	0	145	0	0
T117	0	145	0	0
T118	0	327	0	0
T119	0	396	0	0
T120	106742	0	0	0
T121	2832	0	0	0
T122	52762	0	0	0
T123	35796	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336607331	2895	0	0
T49	0	139	0	0
T51	171780	274	0	0
T65	0	41	0	0
T67	0	6	0	0
T69	63871	0	0	0
T70	29667	0	0	0
T71	0	33	0	0
T107	290049	0	0	0
T108	297182	0	0	0
T109	290804	0	0	0
T115	0	145	0	0
T116	0	105	0	0
T117	0	91	0	0
T118	0	378	0	0
T119	0	453	0	0
T120	106742	0	0	0
T121	2832	0	0	0
T122	52762	0	0	0
T123	35796	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336607331	1877	0	0
T49	0	144	0	0
T51	171780	248	0	0
T69	63871	0	0	0
T70	29667	0	0	0
T107	290049	0	0	0
T108	297182	0	0	0
T109	290804	0	0	0
T115	0	130	0	0
T116	0	147	0	0
T117	0	71	0	0
T118	0	405	0	0
T119	0	506	0	0
T120	106742	0	0	0
T121	2832	0	0	0
T122	52762	0	0	0
T123	35796	0	0	0
T124	0	23	0	0
T125	0	8	0	0
T126	0	25	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336607331	1538	0	0
T49	0	76	0	0
T51	171780	160	0	0
T69	63871	0	0	0
T70	29667	0	0	0
T107	290049	0	0	0
T108	297182	0	0	0
T109	290804	0	0	0
T115	0	157	0	0
T116	0	105	0	0
T117	0	69	0	0
T118	0	412	0	0
T119	0	396	0	0
T120	106742	0	0	0
T121	2832	0	0	0
T122	52762	0	0	0
T123	35796	0	0	0
T124	0	13	0	0
T125	0	8	0	0
T127	0	30	0	0