| T803 |
/workspace/coverage/default/44.sram_ctrl_stress_all.1271147480 |
|
|
Jul 03 04:33:51 PM PDT 24 |
Jul 03 05:11:05 PM PDT 24 |
194988108598 ps |
| T804 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2382329577 |
|
|
Jul 03 04:33:09 PM PDT 24 |
Jul 03 05:14:53 PM PDT 24 |
145816756154 ps |
| T805 |
/workspace/coverage/default/6.sram_ctrl_stress_all.714891824 |
|
|
Jul 03 04:32:27 PM PDT 24 |
Jul 03 04:43:33 PM PDT 24 |
15523234375 ps |
| T806 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1313239782 |
|
|
Jul 03 04:32:54 PM PDT 24 |
Jul 03 04:49:45 PM PDT 24 |
9668877299 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_smoke.4137273026 |
|
|
Jul 03 04:33:24 PM PDT 24 |
Jul 03 04:33:32 PM PDT 24 |
611530399 ps |
| T808 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1914057547 |
|
|
Jul 03 04:33:13 PM PDT 24 |
Jul 03 04:34:57 PM PDT 24 |
292739797 ps |
| T809 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2682066182 |
|
|
Jul 03 04:32:54 PM PDT 24 |
Jul 03 04:35:02 PM PDT 24 |
637982250 ps |
| T810 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.410841604 |
|
|
Jul 03 04:33:44 PM PDT 24 |
Jul 03 04:48:09 PM PDT 24 |
10604587488 ps |
| T811 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1776460509 |
|
|
Jul 03 04:33:00 PM PDT 24 |
Jul 03 05:04:20 PM PDT 24 |
28523740055 ps |
| T812 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1125126625 |
|
|
Jul 03 04:32:27 PM PDT 24 |
Jul 03 04:32:28 PM PDT 24 |
13726886 ps |
| T813 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4214813510 |
|
|
Jul 03 04:33:06 PM PDT 24 |
Jul 03 04:34:43 PM PDT 24 |
1869559482 ps |
| T814 |
/workspace/coverage/default/25.sram_ctrl_executable.2555569849 |
|
|
Jul 03 04:32:58 PM PDT 24 |
Jul 03 04:35:27 PM PDT 24 |
1868228282 ps |
| T815 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.486266526 |
|
|
Jul 03 04:34:05 PM PDT 24 |
Jul 03 04:36:39 PM PDT 24 |
1667511947 ps |
| T816 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2844611333 |
|
|
Jul 03 04:33:28 PM PDT 24 |
Jul 03 04:33:29 PM PDT 24 |
40135834 ps |
| T817 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4246095129 |
|
|
Jul 03 04:32:46 PM PDT 24 |
Jul 03 04:34:21 PM PDT 24 |
801462209 ps |
| T818 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.520047435 |
|
|
Jul 03 04:34:09 PM PDT 24 |
Jul 03 04:36:30 PM PDT 24 |
517267674 ps |
| T819 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.601226691 |
|
|
Jul 03 04:32:22 PM PDT 24 |
Jul 03 04:40:56 PM PDT 24 |
3186132601 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_alert_test.1353861682 |
|
|
Jul 03 04:32:27 PM PDT 24 |
Jul 03 04:32:28 PM PDT 24 |
40550493 ps |
| T821 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.895111297 |
|
|
Jul 03 04:33:37 PM PDT 24 |
Jul 03 04:46:20 PM PDT 24 |
2952947732 ps |
| T822 |
/workspace/coverage/default/11.sram_ctrl_partial_access.843872750 |
|
|
Jul 03 04:32:59 PM PDT 24 |
Jul 03 04:33:10 PM PDT 24 |
462371133 ps |
| T823 |
/workspace/coverage/default/3.sram_ctrl_partial_access.853623185 |
|
|
Jul 03 04:32:36 PM PDT 24 |
Jul 03 04:32:58 PM PDT 24 |
5270487753 ps |
| T824 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2220960274 |
|
|
Jul 03 04:32:18 PM PDT 24 |
Jul 03 04:32:25 PM PDT 24 |
1198996650 ps |
| T825 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1598635914 |
|
|
Jul 03 04:33:25 PM PDT 24 |
Jul 03 04:38:29 PM PDT 24 |
5477977816 ps |
| T826 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2468805132 |
|
|
Jul 03 04:33:16 PM PDT 24 |
Jul 03 05:20:25 PM PDT 24 |
370778435369 ps |
| T827 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2825387040 |
|
|
Jul 03 04:33:01 PM PDT 24 |
Jul 03 04:33:03 PM PDT 24 |
16162590 ps |
| T828 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3481240984 |
|
|
Jul 03 04:33:57 PM PDT 24 |
Jul 03 04:33:59 PM PDT 24 |
55154865 ps |
| T829 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1496076700 |
|
|
Jul 03 04:32:45 PM PDT 24 |
Jul 03 04:32:52 PM PDT 24 |
177885885 ps |
| T830 |
/workspace/coverage/default/30.sram_ctrl_alert_test.178796871 |
|
|
Jul 03 04:33:16 PM PDT 24 |
Jul 03 04:33:18 PM PDT 24 |
44636064 ps |
| T831 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.837401807 |
|
|
Jul 03 04:32:41 PM PDT 24 |
Jul 03 04:36:23 PM PDT 24 |
2557301578 ps |
| T832 |
/workspace/coverage/default/34.sram_ctrl_smoke.1153597215 |
|
|
Jul 03 04:33:12 PM PDT 24 |
Jul 03 04:33:15 PM PDT 24 |
145976103 ps |
| T833 |
/workspace/coverage/default/20.sram_ctrl_bijection.80272018 |
|
|
Jul 03 04:32:48 PM PDT 24 |
Jul 03 04:33:30 PM PDT 24 |
2778068749 ps |
| T834 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.4037036751 |
|
|
Jul 03 04:32:31 PM PDT 24 |
Jul 03 04:32:44 PM PDT 24 |
2717055366 ps |
| T835 |
/workspace/coverage/default/47.sram_ctrl_smoke.325135620 |
|
|
Jul 03 04:33:57 PM PDT 24 |
Jul 03 04:34:09 PM PDT 24 |
708049377 ps |
| T836 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1837210987 |
|
|
Jul 03 04:33:59 PM PDT 24 |
Jul 03 04:34:05 PM PDT 24 |
265356051 ps |
| T837 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.626101640 |
|
|
Jul 03 04:32:13 PM PDT 24 |
Jul 03 04:32:20 PM PDT 24 |
2842326901 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2798215342 |
|
|
Jul 03 04:33:05 PM PDT 24 |
Jul 03 04:38:21 PM PDT 24 |
7463845669 ps |
| T839 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3805888820 |
|
|
Jul 03 04:32:51 PM PDT 24 |
Jul 03 04:33:01 PM PDT 24 |
366201708 ps |
| T840 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2954740390 |
|
|
Jul 03 04:33:09 PM PDT 24 |
Jul 03 04:40:26 PM PDT 24 |
29301715577 ps |
| T841 |
/workspace/coverage/default/18.sram_ctrl_regwen.3611722607 |
|
|
Jul 03 04:32:46 PM PDT 24 |
Jul 03 04:51:57 PM PDT 24 |
9492232356 ps |
| T842 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1085161056 |
|
|
Jul 03 04:32:43 PM PDT 24 |
Jul 03 04:32:52 PM PDT 24 |
139784290 ps |
| T843 |
/workspace/coverage/default/12.sram_ctrl_bijection.977826183 |
|
|
Jul 03 04:33:03 PM PDT 24 |
Jul 03 04:33:56 PM PDT 24 |
10328634053 ps |
| T844 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2911697957 |
|
|
Jul 03 04:32:56 PM PDT 24 |
Jul 03 05:11:33 PM PDT 24 |
30886837361 ps |
| T845 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2978109691 |
|
|
Jul 03 04:32:51 PM PDT 24 |
Jul 03 04:33:05 PM PDT 24 |
1313425860 ps |
| T846 |
/workspace/coverage/default/36.sram_ctrl_regwen.1291498026 |
|
|
Jul 03 04:33:21 PM PDT 24 |
Jul 03 04:47:05 PM PDT 24 |
3195721191 ps |
| T847 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3455726879 |
|
|
Jul 03 04:33:22 PM PDT 24 |
Jul 03 04:59:34 PM PDT 24 |
4458238407 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.929392990 |
|
|
Jul 03 04:33:32 PM PDT 24 |
Jul 03 04:33:33 PM PDT 24 |
30241556 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4223516014 |
|
|
Jul 03 04:33:52 PM PDT 24 |
Jul 03 04:33:57 PM PDT 24 |
67613419 ps |
| T850 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3801571482 |
|
|
Jul 03 04:33:22 PM PDT 24 |
Jul 03 04:33:26 PM PDT 24 |
109246589 ps |
| T851 |
/workspace/coverage/default/41.sram_ctrl_regwen.2728188913 |
|
|
Jul 03 04:33:42 PM PDT 24 |
Jul 03 04:35:31 PM PDT 24 |
400540346 ps |
| T852 |
/workspace/coverage/default/13.sram_ctrl_bijection.2478493168 |
|
|
Jul 03 04:32:33 PM PDT 24 |
Jul 03 04:33:33 PM PDT 24 |
13985055036 ps |
| T853 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1941062556 |
|
|
Jul 03 04:33:39 PM PDT 24 |
Jul 03 04:44:47 PM PDT 24 |
1503081332 ps |
| T854 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3249978837 |
|
|
Jul 03 04:32:51 PM PDT 24 |
Jul 03 06:28:46 PM PDT 24 |
17261423819 ps |
| T855 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3400523007 |
|
|
Jul 03 04:33:08 PM PDT 24 |
Jul 03 04:33:10 PM PDT 24 |
104632450 ps |
| T856 |
/workspace/coverage/default/45.sram_ctrl_executable.7769898 |
|
|
Jul 03 04:33:51 PM PDT 24 |
Jul 03 04:44:03 PM PDT 24 |
12036888474 ps |
| T857 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4140376122 |
|
|
Jul 03 04:33:52 PM PDT 24 |
Jul 03 04:34:29 PM PDT 24 |
394312277 ps |
| T858 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3605682259 |
|
|
Jul 03 04:32:58 PM PDT 24 |
Jul 03 04:33:05 PM PDT 24 |
2032366698 ps |
| T859 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.135858698 |
|
|
Jul 03 04:33:14 PM PDT 24 |
Jul 03 04:35:25 PM PDT 24 |
576282014 ps |
| T118 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3959503778 |
|
|
Jul 03 04:33:22 PM PDT 24 |
Jul 03 04:34:12 PM PDT 24 |
3153948460 ps |
| T90 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2107728102 |
|
|
Jul 03 04:33:07 PM PDT 24 |
Jul 03 04:33:13 PM PDT 24 |
294714969 ps |
| T860 |
/workspace/coverage/default/9.sram_ctrl_alert_test.2548872573 |
|
|
Jul 03 04:32:35 PM PDT 24 |
Jul 03 04:32:36 PM PDT 24 |
35219521 ps |
| T861 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1202843830 |
|
|
Jul 03 04:34:07 PM PDT 24 |
Jul 03 04:39:39 PM PDT 24 |
12466437722 ps |
| T862 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.944924190 |
|
|
Jul 03 04:32:06 PM PDT 24 |
Jul 03 04:32:11 PM PDT 24 |
1193334110 ps |
| T863 |
/workspace/coverage/default/1.sram_ctrl_executable.2922992619 |
|
|
Jul 03 04:32:02 PM PDT 24 |
Jul 03 04:40:07 PM PDT 24 |
974439829 ps |
| T864 |
/workspace/coverage/default/48.sram_ctrl_bijection.323634887 |
|
|
Jul 03 04:34:06 PM PDT 24 |
Jul 03 04:34:37 PM PDT 24 |
484515681 ps |
| T865 |
/workspace/coverage/default/40.sram_ctrl_regwen.3452907813 |
|
|
Jul 03 04:33:39 PM PDT 24 |
Jul 03 04:41:24 PM PDT 24 |
1863408217 ps |
| T866 |
/workspace/coverage/default/7.sram_ctrl_smoke.885814877 |
|
|
Jul 03 04:32:20 PM PDT 24 |
Jul 03 04:32:22 PM PDT 24 |
710292417 ps |
| T119 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1099696211 |
|
|
Jul 03 04:32:21 PM PDT 24 |
Jul 03 04:33:50 PM PDT 24 |
43796642137 ps |
| T867 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2080256852 |
|
|
Jul 03 04:32:28 PM PDT 24 |
Jul 03 04:32:30 PM PDT 24 |
25364437 ps |
| T868 |
/workspace/coverage/default/18.sram_ctrl_partial_access.4233341473 |
|
|
Jul 03 04:32:38 PM PDT 24 |
Jul 03 04:33:17 PM PDT 24 |
760560257 ps |
| T869 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3406200587 |
|
|
Jul 03 04:32:39 PM PDT 24 |
Jul 03 04:32:40 PM PDT 24 |
40758126 ps |
| T870 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1088517323 |
|
|
Jul 03 04:33:46 PM PDT 24 |
Jul 03 04:33:53 PM PDT 24 |
440513460 ps |
| T871 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2788382959 |
|
|
Jul 03 04:32:56 PM PDT 24 |
Jul 03 04:35:13 PM PDT 24 |
135709002 ps |
| T872 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2741350485 |
|
|
Jul 03 04:32:07 PM PDT 24 |
Jul 03 04:47:40 PM PDT 24 |
11615797015 ps |
| T873 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1747104248 |
|
|
Jul 03 04:33:38 PM PDT 24 |
Jul 03 04:42:05 PM PDT 24 |
5089097132 ps |
| T874 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1124992096 |
|
|
Jul 03 04:33:09 PM PDT 24 |
Jul 03 04:33:10 PM PDT 24 |
26663674 ps |
| T875 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1685328595 |
|
|
Jul 03 04:33:23 PM PDT 24 |
Jul 03 04:34:11 PM PDT 24 |
395192332 ps |
| T876 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.615517014 |
|
|
Jul 03 04:33:30 PM PDT 24 |
Jul 03 04:48:01 PM PDT 24 |
3346500525 ps |
| T877 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4186282860 |
|
|
Jul 03 04:33:47 PM PDT 24 |
Jul 03 04:40:00 PM PDT 24 |
92914491321 ps |
| T878 |
/workspace/coverage/default/45.sram_ctrl_smoke.3396837935 |
|
|
Jul 03 04:33:52 PM PDT 24 |
Jul 03 04:34:14 PM PDT 24 |
3829523328 ps |
| T879 |
/workspace/coverage/default/19.sram_ctrl_smoke.1221313344 |
|
|
Jul 03 04:32:34 PM PDT 24 |
Jul 03 04:33:07 PM PDT 24 |
863274786 ps |
| T880 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2039551678 |
|
|
Jul 03 04:33:50 PM PDT 24 |
Jul 03 04:38:04 PM PDT 24 |
10195040954 ps |
| T881 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.878158424 |
|
|
Jul 03 04:33:01 PM PDT 24 |
Jul 03 04:33:09 PM PDT 24 |
306210179 ps |
| T882 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1904252205 |
|
|
Jul 03 04:33:20 PM PDT 24 |
Jul 03 04:55:06 PM PDT 24 |
61301265787 ps |
| T883 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2572943319 |
|
|
Jul 03 04:33:04 PM PDT 24 |
Jul 03 04:35:23 PM PDT 24 |
1386401127 ps |
| T884 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.481883016 |
|
|
Jul 03 04:32:31 PM PDT 24 |
Jul 03 04:39:12 PM PDT 24 |
6169276283 ps |
| T885 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1214082059 |
|
|
Jul 03 04:33:24 PM PDT 24 |
Jul 03 04:33:45 PM PDT 24 |
83999737 ps |
| T886 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2106406895 |
|
|
Jul 03 04:32:23 PM PDT 24 |
Jul 03 04:34:50 PM PDT 24 |
191821727 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_regwen.278185063 |
|
|
Jul 03 04:32:13 PM PDT 24 |
Jul 03 04:46:29 PM PDT 24 |
3002573162 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.874645234 |
|
|
Jul 03 04:32:36 PM PDT 24 |
Jul 03 04:32:42 PM PDT 24 |
374931164 ps |
| T889 |
/workspace/coverage/default/1.sram_ctrl_bijection.1052456121 |
|
|
Jul 03 04:32:00 PM PDT 24 |
Jul 03 04:33:00 PM PDT 24 |
924880199 ps |
| T890 |
/workspace/coverage/default/2.sram_ctrl_executable.2932458493 |
|
|
Jul 03 04:32:18 PM PDT 24 |
Jul 03 04:48:38 PM PDT 24 |
7479937378 ps |
| T891 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3540613503 |
|
|
Jul 03 04:32:29 PM PDT 24 |
Jul 03 04:54:07 PM PDT 24 |
5988168440 ps |
| T892 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.960372710 |
|
|
Jul 03 04:33:25 PM PDT 24 |
Jul 03 04:33:30 PM PDT 24 |
894343637 ps |
| T893 |
/workspace/coverage/default/2.sram_ctrl_partial_access.2361153257 |
|
|
Jul 03 04:32:12 PM PDT 24 |
Jul 03 04:32:27 PM PDT 24 |
788799545 ps |
| T894 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.715952037 |
|
|
Jul 03 04:33:44 PM PDT 24 |
Jul 03 04:34:02 PM PDT 24 |
393015270 ps |
| T895 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1214153078 |
|
|
Jul 03 04:33:23 PM PDT 24 |
Jul 03 04:33:25 PM PDT 24 |
31185166 ps |
| T896 |
/workspace/coverage/default/42.sram_ctrl_bijection.3061186197 |
|
|
Jul 03 04:33:49 PM PDT 24 |
Jul 03 04:34:40 PM PDT 24 |
43867099463 ps |
| T897 |
/workspace/coverage/default/22.sram_ctrl_alert_test.1627075020 |
|
|
Jul 03 04:33:05 PM PDT 24 |
Jul 03 04:33:06 PM PDT 24 |
16741912 ps |
| T898 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3346914698 |
|
|
Jul 03 04:33:55 PM PDT 24 |
Jul 03 04:34:07 PM PDT 24 |
1820955104 ps |
| T899 |
/workspace/coverage/default/17.sram_ctrl_bijection.2361432352 |
|
|
Jul 03 04:33:17 PM PDT 24 |
Jul 03 04:34:10 PM PDT 24 |
3165860584 ps |
| T900 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1571362010 |
|
|
Jul 03 04:32:38 PM PDT 24 |
Jul 03 05:24:51 PM PDT 24 |
39642777247 ps |
| T901 |
/workspace/coverage/default/24.sram_ctrl_regwen.3788121132 |
|
|
Jul 03 04:32:41 PM PDT 24 |
Jul 03 04:55:02 PM PDT 24 |
59588532234 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1847329107 |
|
|
Jul 03 04:33:09 PM PDT 24 |
Jul 03 04:34:44 PM PDT 24 |
1071635958 ps |
| T903 |
/workspace/coverage/default/27.sram_ctrl_smoke.1257601405 |
|
|
Jul 03 04:33:03 PM PDT 24 |
Jul 03 04:34:57 PM PDT 24 |
618669764 ps |
| T904 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1877190261 |
|
|
Jul 03 04:33:11 PM PDT 24 |
Jul 03 04:33:46 PM PDT 24 |
507655144 ps |
| T905 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1085886492 |
|
|
Jul 03 04:32:05 PM PDT 24 |
Jul 03 04:33:15 PM PDT 24 |
125443280 ps |
| T906 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2694259506 |
|
|
Jul 03 04:32:57 PM PDT 24 |
Jul 03 04:32:58 PM PDT 24 |
49160850 ps |
| T907 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3555771827 |
|
|
Jul 03 04:32:57 PM PDT 24 |
Jul 03 04:33:40 PM PDT 24 |
383338934 ps |
| T908 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.4151210426 |
|
|
Jul 03 04:32:36 PM PDT 24 |
Jul 03 04:32:47 PM PDT 24 |
2423116254 ps |
| T909 |
/workspace/coverage/default/15.sram_ctrl_bijection.74379639 |
|
|
Jul 03 04:33:00 PM PDT 24 |
Jul 03 04:34:11 PM PDT 24 |
1095557884 ps |
| T910 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.699333503 |
|
|
Jul 03 04:32:50 PM PDT 24 |
Jul 03 04:33:02 PM PDT 24 |
1399202429 ps |
| T911 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1671465395 |
|
|
Jul 03 04:32:45 PM PDT 24 |
Jul 03 04:39:01 PM PDT 24 |
1323303395 ps |
| T912 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3396288130 |
|
|
Jul 03 04:32:43 PM PDT 24 |
Jul 03 04:32:57 PM PDT 24 |
79327081 ps |
| T913 |
/workspace/coverage/default/17.sram_ctrl_executable.657093221 |
|
|
Jul 03 04:32:45 PM PDT 24 |
Jul 03 04:52:30 PM PDT 24 |
12619015360 ps |
| T914 |
/workspace/coverage/default/22.sram_ctrl_executable.504737097 |
|
|
Jul 03 04:33:01 PM PDT 24 |
Jul 03 04:40:31 PM PDT 24 |
1744470544 ps |
| T915 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1768938465 |
|
|
Jul 03 04:32:55 PM PDT 24 |
Jul 03 04:33:15 PM PDT 24 |
549010122 ps |
| T916 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2058907453 |
|
|
Jul 03 04:33:53 PM PDT 24 |
Jul 03 04:33:54 PM PDT 24 |
15862101 ps |
| T917 |
/workspace/coverage/default/0.sram_ctrl_bijection.194783903 |
|
|
Jul 03 04:32:04 PM PDT 24 |
Jul 03 04:33:08 PM PDT 24 |
2941558107 ps |
| T918 |
/workspace/coverage/default/28.sram_ctrl_smoke.2799907294 |
|
|
Jul 03 04:33:06 PM PDT 24 |
Jul 03 04:33:19 PM PDT 24 |
328913783 ps |
| T919 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.4271963357 |
|
|
Jul 03 04:32:58 PM PDT 24 |
Jul 03 04:33:04 PM PDT 24 |
259696611 ps |
| T920 |
/workspace/coverage/default/29.sram_ctrl_regwen.2487944970 |
|
|
Jul 03 04:33:15 PM PDT 24 |
Jul 03 04:37:34 PM PDT 24 |
21064384908 ps |
| T921 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3189421944 |
|
|
Jul 03 04:33:25 PM PDT 24 |
Jul 03 04:33:26 PM PDT 24 |
91441907 ps |
| T922 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.400681272 |
|
|
Jul 03 04:32:37 PM PDT 24 |
Jul 03 04:34:52 PM PDT 24 |
761836822 ps |
| T923 |
/workspace/coverage/default/47.sram_ctrl_regwen.1070564433 |
|
|
Jul 03 04:34:08 PM PDT 24 |
Jul 03 04:48:13 PM PDT 24 |
77068569784 ps |
| T924 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1292942991 |
|
|
Jul 03 04:32:16 PM PDT 24 |
Jul 03 04:32:23 PM PDT 24 |
1348040547 ps |
| T925 |
/workspace/coverage/default/16.sram_ctrl_partial_access.4104113029 |
|
|
Jul 03 04:33:15 PM PDT 24 |
Jul 03 04:35:16 PM PDT 24 |
206986365 ps |
| T926 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2924106705 |
|
|
Jul 03 04:33:55 PM PDT 24 |
Jul 03 04:37:53 PM PDT 24 |
2509032247 ps |
| T927 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1087287954 |
|
|
Jul 03 04:32:18 PM PDT 24 |
Jul 03 04:58:21 PM PDT 24 |
23799257799 ps |
| T928 |
/workspace/coverage/default/11.sram_ctrl_bijection.3898334607 |
|
|
Jul 03 04:32:31 PM PDT 24 |
Jul 03 04:33:43 PM PDT 24 |
23645146632 ps |
| T91 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1209447846 |
|
|
Jul 03 04:32:29 PM PDT 24 |
Jul 03 04:32:34 PM PDT 24 |
249496332 ps |
| T929 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.2703075888 |
|
|
Jul 03 04:32:41 PM PDT 24 |
Jul 03 04:32:48 PM PDT 24 |
673758465 ps |
| T930 |
/workspace/coverage/default/33.sram_ctrl_alert_test.975873584 |
|
|
Jul 03 04:33:14 PM PDT 24 |
Jul 03 04:33:16 PM PDT 24 |
24844233 ps |
| T931 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.578194109 |
|
|
Jul 03 04:32:46 PM PDT 24 |
Jul 03 04:33:40 PM PDT 24 |
239029798 ps |
| T932 |
/workspace/coverage/default/21.sram_ctrl_stress_all.467800914 |
|
|
Jul 03 04:32:57 PM PDT 24 |
Jul 03 05:02:14 PM PDT 24 |
50447101401 ps |
| T92 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2388853825 |
|
|
Jul 03 04:32:45 PM PDT 24 |
Jul 03 04:32:48 PM PDT 24 |
104915430 ps |
| T933 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1384118380 |
|
|
Jul 03 04:33:01 PM PDT 24 |
Jul 03 04:33:13 PM PDT 24 |
1669266451 ps |
| T934 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.4276643424 |
|
|
Jul 03 04:33:21 PM PDT 24 |
Jul 03 04:33:34 PM PDT 24 |
2705295272 ps |
| T935 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1791582796 |
|
|
Jul 03 04:33:17 PM PDT 24 |
Jul 03 04:52:35 PM PDT 24 |
14347159143 ps |
| T936 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2082734262 |
|
|
Jul 03 04:33:11 PM PDT 24 |
Jul 03 04:35:03 PM PDT 24 |
183541796 ps |
| T937 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2029869884 |
|
|
Jul 03 04:34:12 PM PDT 24 |
Jul 03 04:34:27 PM PDT 24 |
1514515324 ps |
| T938 |
/workspace/coverage/default/31.sram_ctrl_executable.3524575697 |
|
|
Jul 03 04:33:12 PM PDT 24 |
Jul 03 04:47:16 PM PDT 24 |
59662359572 ps |
| T939 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2728953091 |
|
|
Jul 03 04:32:30 PM PDT 24 |
Jul 03 04:49:43 PM PDT 24 |
60863656753 ps |
| T940 |
/workspace/coverage/default/2.sram_ctrl_smoke.3070156469 |
|
|
Jul 03 04:32:22 PM PDT 24 |
Jul 03 04:32:40 PM PDT 24 |
354042394 ps |
| T65 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1467076169 |
|
|
Jul 03 04:28:14 PM PDT 24 |
Jul 03 04:28:16 PM PDT 24 |
20275715 ps |
| T66 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3559556355 |
|
|
Jul 03 04:28:20 PM PDT 24 |
Jul 03 04:28:24 PM PDT 24 |
552691822 ps |
| T941 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3016419965 |
|
|
Jul 03 04:28:35 PM PDT 24 |
Jul 03 04:28:37 PM PDT 24 |
30777784 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4022969574 |
|
|
Jul 03 04:28:46 PM PDT 24 |
Jul 03 04:28:47 PM PDT 24 |
12827839 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2249823861 |
|
|
Jul 03 04:28:02 PM PDT 24 |
Jul 03 04:28:06 PM PDT 24 |
28974262 ps |
| T71 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1637026645 |
|
|
Jul 03 04:28:55 PM PDT 24 |
Jul 03 04:28:58 PM PDT 24 |
1550301358 ps |
| T113 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2786176116 |
|
|
Jul 03 04:28:32 PM PDT 24 |
Jul 03 04:28:33 PM PDT 24 |
22833329 ps |
| T72 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3678812872 |
|
|
Jul 03 04:28:27 PM PDT 24 |
Jul 03 04:28:28 PM PDT 24 |
78204304 ps |
| T73 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.613012032 |
|
|
Jul 03 04:28:30 PM PDT 24 |
Jul 03 04:28:31 PM PDT 24 |
23778097 ps |
| T124 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3959232627 |
|
|
Jul 03 04:29:21 PM PDT 24 |
Jul 03 04:29:24 PM PDT 24 |
172196635 ps |
| T943 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1204594956 |
|
|
Jul 03 04:28:30 PM PDT 24 |
Jul 03 04:28:31 PM PDT 24 |
45105577 ps |
| T944 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2863896043 |
|
|
Jul 03 04:28:36 PM PDT 24 |
Jul 03 04:28:38 PM PDT 24 |
37566897 ps |
| T103 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1675699372 |
|
|
Jul 03 04:28:05 PM PDT 24 |
Jul 03 04:28:14 PM PDT 24 |
84408991 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2562606416 |
|
|
Jul 03 04:28:23 PM PDT 24 |
Jul 03 04:28:24 PM PDT 24 |
12549755 ps |
| T62 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3215988106 |
|
|
Jul 03 04:28:41 PM PDT 24 |
Jul 03 04:28:44 PM PDT 24 |
205099492 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3140705984 |
|
|
Jul 03 04:28:17 PM PDT 24 |
Jul 03 04:28:19 PM PDT 24 |
175070505 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.34406561 |
|
|
Jul 03 04:28:03 PM PDT 24 |
Jul 03 04:28:08 PM PDT 24 |
30460517 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2041503899 |
|
|
Jul 03 04:28:04 PM PDT 24 |
Jul 03 04:28:14 PM PDT 24 |
169728429 ps |
| T77 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3048428860 |
|
|
Jul 03 04:28:34 PM PDT 24 |
Jul 03 04:28:37 PM PDT 24 |
810081605 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2637851313 |
|
|
Jul 03 04:28:14 PM PDT 24 |
Jul 03 04:28:16 PM PDT 24 |
19983927 ps |
| T82 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1647348894 |
|
|
Jul 03 04:28:25 PM PDT 24 |
Jul 03 04:28:30 PM PDT 24 |
1195300118 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3647481728 |
|
|
Jul 03 04:28:18 PM PDT 24 |
Jul 03 04:28:20 PM PDT 24 |
23356147 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2885737622 |
|
|
Jul 03 04:29:02 PM PDT 24 |
Jul 03 04:29:05 PM PDT 24 |
546026774 ps |
| T63 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.989034688 |
|
|
Jul 03 04:28:49 PM PDT 24 |
Jul 03 04:28:51 PM PDT 24 |
135149493 ps |
| T125 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.245372214 |
|
|
Jul 03 04:28:34 PM PDT 24 |
Jul 03 04:28:36 PM PDT 24 |
52545697 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1923766245 |
|
|
Jul 03 04:28:15 PM PDT 24 |
Jul 03 04:28:18 PM PDT 24 |
284877343 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.664521589 |
|
|
Jul 03 04:29:30 PM PDT 24 |
Jul 03 04:29:30 PM PDT 24 |
16178739 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1823519029 |
|
|
Jul 03 04:28:31 PM PDT 24 |
Jul 03 04:28:33 PM PDT 24 |
349392550 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2122292497 |
|
|
Jul 03 04:28:38 PM PDT 24 |
Jul 03 04:28:39 PM PDT 24 |
41559076 ps |
| T64 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4009370838 |
|
|
Jul 03 04:28:03 PM PDT 24 |
Jul 03 04:28:09 PM PDT 24 |
230042871 ps |
| T130 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.134694178 |
|
|
Jul 03 04:28:26 PM PDT 24 |
Jul 03 04:28:28 PM PDT 24 |
117354504 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3965740010 |
|
|
Jul 03 04:28:28 PM PDT 24 |
Jul 03 04:28:31 PM PDT 24 |
1664845568 ps |
| T105 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.579819230 |
|
|
Jul 03 04:28:34 PM PDT 24 |
Jul 03 04:28:36 PM PDT 24 |
20451234 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3961401055 |
|
|
Jul 03 04:28:38 PM PDT 24 |
Jul 03 04:28:41 PM PDT 24 |
416935164 ps |
| T134 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2139427350 |
|
|
Jul 03 04:28:03 PM PDT 24 |
Jul 03 04:28:09 PM PDT 24 |
167369961 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2842584087 |
|
|
Jul 03 04:28:05 PM PDT 24 |
Jul 03 04:28:11 PM PDT 24 |
15398514 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3421532087 |
|
|
Jul 03 04:28:23 PM PDT 24 |
Jul 03 04:28:24 PM PDT 24 |
128992247 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.197199063 |
|
|
Jul 03 04:28:07 PM PDT 24 |
Jul 03 04:28:13 PM PDT 24 |
41745852 ps |
| T951 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3018627062 |
|
|
Jul 03 04:28:38 PM PDT 24 |
Jul 03 04:28:39 PM PDT 24 |
15218299 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2887328326 |
|
|
Jul 03 04:28:35 PM PDT 24 |
Jul 03 04:28:36 PM PDT 24 |
74559552 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3915221628 |
|
|
Jul 03 04:28:04 PM PDT 24 |
Jul 03 04:28:09 PM PDT 24 |
28191328 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4011687890 |
|
|
Jul 03 04:28:07 PM PDT 24 |
Jul 03 04:28:16 PM PDT 24 |
117758066 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2408800849 |
|
|
Jul 03 04:28:29 PM PDT 24 |
Jul 03 04:28:31 PM PDT 24 |
332336849 ps |
| T94 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.314474206 |
|
|
Jul 03 04:28:24 PM PDT 24 |
Jul 03 04:28:30 PM PDT 24 |
20699413 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3552548745 |
|
|
Jul 03 04:28:02 PM PDT 24 |
Jul 03 04:28:10 PM PDT 24 |
54599238 ps |
| T127 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.411517966 |
|
|
Jul 03 04:28:17 PM PDT 24 |
Jul 03 04:28:21 PM PDT 24 |
77413428 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4288354382 |
|
|
Jul 03 04:28:04 PM PDT 24 |
Jul 03 04:28:10 PM PDT 24 |
43748051 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1070080494 |
|
|
Jul 03 04:28:31 PM PDT 24 |
Jul 03 04:28:34 PM PDT 24 |
1735675992 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1396931792 |
|
|
Jul 03 04:28:16 PM PDT 24 |
Jul 03 04:28:19 PM PDT 24 |
69150382 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3473805614 |
|
|
Jul 03 04:28:30 PM PDT 24 |
Jul 03 04:28:32 PM PDT 24 |
215332593 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3963682512 |
|
|
Jul 03 04:28:16 PM PDT 24 |
Jul 03 04:28:18 PM PDT 24 |
36668596 ps |
| T96 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1280663626 |
|
|
Jul 03 04:28:13 PM PDT 24 |
Jul 03 04:28:17 PM PDT 24 |
864659566 ps |
| T959 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4000773242 |
|
|
Jul 03 04:28:38 PM PDT 24 |
Jul 03 04:28:39 PM PDT 24 |
135178796 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1990518369 |
|
|
Jul 03 04:28:30 PM PDT 24 |
Jul 03 04:28:35 PM PDT 24 |
907624019 ps |
| T138 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.184497117 |
|
|
Jul 03 04:28:23 PM PDT 24 |
Jul 03 04:28:25 PM PDT 24 |
373825359 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4241446763 |
|
|
Jul 03 04:28:24 PM PDT 24 |
Jul 03 04:28:27 PM PDT 24 |
679950323 ps |
| T98 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.706240276 |
|
|
Jul 03 04:28:36 PM PDT 24 |
Jul 03 04:28:40 PM PDT 24 |
2014490346 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4082977141 |
|
|
Jul 03 04:28:34 PM PDT 24 |
Jul 03 04:28:36 PM PDT 24 |
68953669 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3682814070 |
|
|
Jul 03 04:28:36 PM PDT 24 |
Jul 03 04:28:40 PM PDT 24 |
428127136 ps |
| T964 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.372550891 |
|
|
Jul 03 04:28:46 PM PDT 24 |
Jul 03 04:28:48 PM PDT 24 |
47611767 ps |
| T965 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4009056353 |
|
|
Jul 03 04:28:37 PM PDT 24 |
Jul 03 04:28:38 PM PDT 24 |
19067953 ps |
| T966 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1705395443 |
|
|
Jul 03 04:28:33 PM PDT 24 |
Jul 03 04:28:37 PM PDT 24 |
79386266 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2029103266 |
|
|
Jul 03 04:28:17 PM PDT 24 |
Jul 03 04:28:20 PM PDT 24 |
414785477 ps |
| T136 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1938555732 |
|
|
Jul 03 04:28:43 PM PDT 24 |
Jul 03 04:28:46 PM PDT 24 |
1656473750 ps |
| T132 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1589739639 |
|
|
Jul 03 04:28:20 PM PDT 24 |
Jul 03 04:28:22 PM PDT 24 |
275179167 ps |
| T968 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2042967745 |
|
|
Jul 03 04:28:22 PM PDT 24 |
Jul 03 04:28:25 PM PDT 24 |
127093591 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4035798137 |
|
|
Jul 03 04:28:39 PM PDT 24 |
Jul 03 04:28:40 PM PDT 24 |
13210160 ps |
| T970 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.733009353 |
|
|
Jul 03 04:28:34 PM PDT 24 |
Jul 03 04:28:39 PM PDT 24 |
40860765 ps |
| T135 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1637713503 |
|
|
Jul 03 04:28:29 PM PDT 24 |
Jul 03 04:28:32 PM PDT 24 |
175554893 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2958869712 |
|
|
Jul 03 04:28:25 PM PDT 24 |
Jul 03 04:28:27 PM PDT 24 |
31885464 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2185765211 |
|
|
Jul 03 04:28:19 PM PDT 24 |
Jul 03 04:28:22 PM PDT 24 |
267113580 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.506809276 |
|
|
Jul 03 04:28:39 PM PDT 24 |
Jul 03 04:28:41 PM PDT 24 |
134257675 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.367748277 |
|
|
Jul 03 04:28:26 PM PDT 24 |
Jul 03 04:28:27 PM PDT 24 |
30855941 ps |
| T975 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.585061407 |
|
|
Jul 03 04:28:04 PM PDT 24 |
Jul 03 04:28:13 PM PDT 24 |
68986715 ps |
| T976 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.403281465 |
|
|
Jul 03 04:28:05 PM PDT 24 |
Jul 03 04:28:11 PM PDT 24 |
13829459 ps |
| T977 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2277916033 |
|
|
Jul 03 04:28:23 PM PDT 24 |
Jul 03 04:28:26 PM PDT 24 |
69196850 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.794445807 |
|
|
Jul 03 04:28:46 PM PDT 24 |
Jul 03 04:28:49 PM PDT 24 |
81388736 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1448528131 |
|
|
Jul 03 04:28:19 PM PDT 24 |
Jul 03 04:28:23 PM PDT 24 |
191252069 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2503201998 |
|
|
Jul 03 04:28:05 PM PDT 24 |
Jul 03 04:28:13 PM PDT 24 |
222119431 ps |
| T99 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.157627802 |
|
|
Jul 03 04:28:11 PM PDT 24 |
Jul 03 04:28:16 PM PDT 24 |
188004485 ps |
| T981 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2775618241 |
|
|
Jul 03 04:28:45 PM PDT 24 |
Jul 03 04:28:46 PM PDT 24 |
19014263 ps |
| T139 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2709221510 |
|
|
Jul 03 04:28:23 PM PDT 24 |
Jul 03 04:28:26 PM PDT 24 |
1184427455 ps |
| T982 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.155561269 |
|
|
Jul 03 04:28:11 PM PDT 24 |
Jul 03 04:28:15 PM PDT 24 |
88094574 ps |
| T140 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.323178439 |
|
|
Jul 03 04:28:04 PM PDT 24 |
Jul 03 04:28:10 PM PDT 24 |
312276904 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1764030821 |
|
|
Jul 03 04:28:14 PM PDT 24 |
Jul 03 04:28:18 PM PDT 24 |
92676460 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2767431304 |
|
|
Jul 03 04:28:15 PM PDT 24 |
Jul 03 04:28:18 PM PDT 24 |
36941064 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1067214107 |
|
|
Jul 03 04:28:11 PM PDT 24 |
Jul 03 04:28:15 PM PDT 24 |
21529287 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1401247914 |
|
|
Jul 03 04:28:02 PM PDT 24 |
Jul 03 04:28:07 PM PDT 24 |
835109722 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2310505350 |
|
|
Jul 03 04:28:17 PM PDT 24 |
Jul 03 04:28:20 PM PDT 24 |
262343264 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1120163701 |
|
|
Jul 03 04:28:03 PM PDT 24 |
Jul 03 04:28:07 PM PDT 24 |
36479499 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3658001920 |
|
|
Jul 03 04:29:32 PM PDT 24 |
Jul 03 04:29:33 PM PDT 24 |
22973174 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.774061905 |
|
|
Jul 03 04:28:33 PM PDT 24 |
Jul 03 04:28:38 PM PDT 24 |
445929872 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3607656490 |
|
|
Jul 03 04:28:20 PM PDT 24 |
Jul 03 04:28:21 PM PDT 24 |
16287594 ps |
| T991 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3987605127 |
|
|
Jul 03 04:28:31 PM PDT 24 |
Jul 03 04:28:33 PM PDT 24 |
71015645 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3836318725 |
|
|
Jul 03 04:28:15 PM PDT 24 |
Jul 03 04:28:17 PM PDT 24 |
59774077 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3622557223 |
|
|
Jul 03 04:28:34 PM PDT 24 |
Jul 03 04:28:35 PM PDT 24 |
44520491 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1218302709 |
|
|
Jul 03 04:28:05 PM PDT 24 |
Jul 03 04:28:15 PM PDT 24 |
264445705 ps |
| T101 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3977095171 |
|
|
Jul 03 04:28:50 PM PDT 24 |
Jul 03 04:28:57 PM PDT 24 |
811892746 ps |
| T995 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2219690546 |
|
|
Jul 03 04:28:13 PM PDT 24 |
Jul 03 04:28:18 PM PDT 24 |
61173765 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.516241988 |
|
|
Jul 03 04:28:17 PM PDT 24 |
Jul 03 04:28:20 PM PDT 24 |
487648870 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.428181754 |
|
|
Jul 03 04:28:08 PM PDT 24 |
Jul 03 04:28:13 PM PDT 24 |
16199679 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2318768326 |
|
|
Jul 03 04:28:40 PM PDT 24 |
Jul 03 04:28:41 PM PDT 24 |
31547341 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4075303249 |
|
|
Jul 03 04:28:23 PM PDT 24 |
Jul 03 04:28:25 PM PDT 24 |
13849968 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2307204449 |
|
|
Jul 03 04:28:33 PM PDT 24 |
Jul 03 04:28:35 PM PDT 24 |
99491513 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3351682020 |
|
|
Jul 03 04:28:05 PM PDT 24 |
Jul 03 04:28:11 PM PDT 24 |
26848103 ps |
| T1002 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1021983058 |
|
|
Jul 03 04:28:40 PM PDT 24 |
Jul 03 04:28:43 PM PDT 24 |
261705105 ps |
| T1003 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2591184853 |
|
|
Jul 03 04:28:26 PM PDT 24 |
Jul 03 04:28:29 PM PDT 24 |
279135155 ps |