SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
T1004 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1370222466 | Jul 03 04:28:43 PM PDT 24 | Jul 03 04:28:45 PM PDT 24 | 96754712 ps | ||
T1005 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3136397552 | Jul 03 04:28:18 PM PDT 24 | Jul 03 04:28:22 PM PDT 24 | 452068790 ps | ||
T1006 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3549185747 | Jul 03 04:28:28 PM PDT 24 | Jul 03 04:28:30 PM PDT 24 | 197579854 ps | ||
T141 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.689776876 | Jul 03 04:28:38 PM PDT 24 | Jul 03 04:28:42 PM PDT 24 | 645320138 ps | ||
T1007 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.912267232 | Jul 03 04:28:05 PM PDT 24 | Jul 03 04:28:12 PM PDT 24 | 42814007 ps | ||
T1008 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1469677389 | Jul 03 04:28:17 PM PDT 24 | Jul 03 04:28:19 PM PDT 24 | 21567877 ps | ||
T1009 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2881411441 | Jul 03 04:28:40 PM PDT 24 | Jul 03 04:28:41 PM PDT 24 | 14429984 ps | ||
T1010 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4228508059 | Jul 03 04:28:24 PM PDT 24 | Jul 03 04:28:25 PM PDT 24 | 17417656 ps | ||
T1011 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4293038021 | Jul 03 04:28:11 PM PDT 24 | Jul 03 04:28:18 PM PDT 24 | 6270180653 ps | ||
T1012 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3714585629 | Jul 03 04:28:34 PM PDT 24 | Jul 03 04:28:35 PM PDT 24 | 175141227 ps | ||
T1013 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1547869175 | Jul 03 04:28:19 PM PDT 24 | Jul 03 04:28:25 PM PDT 24 | 64110509 ps | ||
T1014 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3132268311 | Jul 03 04:28:01 PM PDT 24 | Jul 03 04:28:04 PM PDT 24 | 308338326 ps | ||
T1015 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4145005588 | Jul 03 04:28:01 PM PDT 24 | Jul 03 04:28:07 PM PDT 24 | 23359095 ps | ||
T1016 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1836157845 | Jul 03 04:28:17 PM PDT 24 | Jul 03 04:28:20 PM PDT 24 | 86238826 ps | ||
T1017 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2533625484 | Jul 03 04:28:31 PM PDT 24 | Jul 03 04:28:32 PM PDT 24 | 27906826 ps | ||
T1018 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.416259543 | Jul 03 04:28:25 PM PDT 24 | Jul 03 04:28:26 PM PDT 24 | 44880456 ps | ||
T1019 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1536536655 | Jul 03 04:28:15 PM PDT 24 | Jul 03 04:28:17 PM PDT 24 | 13863930 ps | ||
T133 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1796963001 | Jul 03 04:28:06 PM PDT 24 | Jul 03 04:28:14 PM PDT 24 | 224219626 ps | ||
T1020 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1930515693 | Jul 03 04:28:40 PM PDT 24 | Jul 03 04:28:41 PM PDT 24 | 105112400 ps | ||
T1021 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3300203909 | Jul 03 04:28:02 PM PDT 24 | Jul 03 04:28:08 PM PDT 24 | 370511177 ps | ||
T1022 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4017438210 | Jul 03 04:28:16 PM PDT 24 | Jul 03 04:28:18 PM PDT 24 | 24632370 ps | ||
T1023 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3425913697 | Jul 03 04:28:24 PM PDT 24 | Jul 03 04:28:25 PM PDT 24 | 18904700 ps | ||
T1024 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1809454265 | Jul 03 04:28:01 PM PDT 24 | Jul 03 04:28:07 PM PDT 24 | 346589738 ps | ||
T1025 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3847359025 | Jul 03 04:28:03 PM PDT 24 | Jul 03 04:28:10 PM PDT 24 | 1278040839 ps | ||
T137 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2148699284 | Jul 03 04:28:45 PM PDT 24 | Jul 03 04:28:47 PM PDT 24 | 337902594 ps | ||
T1026 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3628683810 | Jul 03 04:28:39 PM PDT 24 | Jul 03 04:28:42 PM PDT 24 | 828657945 ps | ||
T1027 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3153094020 | Jul 03 04:28:18 PM PDT 24 | Jul 03 04:28:22 PM PDT 24 | 439945073 ps |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1451424901 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 2437384195 ps |
CPU time | 359.47 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:40:00 PM PDT 24 |
Peak memory | 379932 kb |
Host | smart-930fb5e0-2b0f-4fb4-897e-463c40d62410 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1451424901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1451424901 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1465780828 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 380451698 ps |
CPU time | 5.59 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:32:37 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-9e227a25-e6b1-4903-bf30-e4d6ae4895bd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465780828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1465780828 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.2760150642 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2450689175 ps |
CPU time | 7.01 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:33:09 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-06dca413-bfb1-41a8-b7c3-6592afa9bb20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760150642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2760150642 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1244110357 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 7484412779 ps |
CPU time | 172.41 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:35:48 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-2d62be4f-3191-41f7-a6a0-2eb7a843d8c5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244110357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.1244110357 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3215988106 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 205099492 ps |
CPU time | 1.69 seconds |
Started | Jul 03 04:28:41 PM PDT 24 |
Finished | Jul 03 04:28:44 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-77b594b3-dde7-46e5-85d7-7add260997ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215988106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.3215988106 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.1137174088 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 19272567423 ps |
CPU time | 600.4 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:42:45 PM PDT 24 |
Peak memory | 366468 kb |
Host | smart-99feae94-8301-4050-ad4d-e6b78a4655c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137174088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1137174088 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3214383145 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 566334235 ps |
CPU time | 3.48 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:26 PM PDT 24 |
Peak memory | 221924 kb |
Host | smart-93e72eef-3978-4ac8-86cc-a857e6b2162a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214383145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3214383145 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2341914724 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 9543555083 ps |
CPU time | 129.29 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:35:08 PM PDT 24 |
Peak memory | 337948 kb |
Host | smart-49feae26-354d-44b7-a60a-665b6f58a0d1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2341914724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2341914724 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.613012032 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 23778097 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:28:30 PM PDT 24 |
Finished | Jul 03 04:28:31 PM PDT 24 |
Peak memory | 201880 kb |
Host | smart-40eda052-c8dd-49a4-b36f-ef922a3543ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613012032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.613012032 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.1260419745 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 30921326 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 04:32:10 PM PDT 24 |
Peak memory | 202312 kb |
Host | smart-da349fb2-c877-4ae1-b326-7db1523c7599 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260419745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1260419745 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1637713503 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 175554893 ps |
CPU time | 2.13 seconds |
Started | Jul 03 04:28:29 PM PDT 24 |
Finished | Jul 03 04:28:32 PM PDT 24 |
Peak memory | 210308 kb |
Host | smart-662c6a02-132d-4461-974d-bb494e77908d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637713503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1637713503 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.3495526733 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 5452329455 ps |
CPU time | 695.34 seconds |
Started | Jul 03 04:33:19 PM PDT 24 |
Finished | Jul 03 04:44:55 PM PDT 24 |
Peak memory | 350352 kb |
Host | smart-7a1ff6de-2ca0-4eec-b128-47c5416acdd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495526733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3495526733 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3293279312 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 29378943 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:29 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-372783d1-c5da-486c-9aa3-c788866fe100 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293279312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3293279312 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2830448633 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 683037060 ps |
CPU time | 5.2 seconds |
Started | Jul 03 04:32:59 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-536017ce-b102-497b-b7a5-1ac86a209538 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2830448633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2830448633 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.2881658260 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 29983747436 ps |
CPU time | 2776.35 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 05:19:31 PM PDT 24 |
Peak memory | 373784 kb |
Host | smart-f595c0d8-86b6-44f8-a514-fc1d7955aefe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881658260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.2881658260 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.323178439 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 312276904 ps |
CPU time | 1.44 seconds |
Started | Jul 03 04:28:04 PM PDT 24 |
Finished | Jul 03 04:28:10 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-b7ef8ce8-4328-4779-a15b-28c8d2454d97 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323178439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.323178439 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2735270710 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 36443118456 ps |
CPU time | 1804.41 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 05:02:27 PM PDT 24 |
Peak memory | 373632 kb |
Host | smart-b3d91162-df6f-485d-8775-5f5ccb05b5f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735270710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2735270710 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3961401055 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 416935164 ps |
CPU time | 2.91 seconds |
Started | Jul 03 04:28:38 PM PDT 24 |
Finished | Jul 03 04:28:41 PM PDT 24 |
Peak memory | 202184 kb |
Host | smart-547a6ce7-6e9b-4f6f-b913-cac10f9524c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961401055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3961401055 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2148699284 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 337902594 ps |
CPU time | 1.65 seconds |
Started | Jul 03 04:28:45 PM PDT 24 |
Finished | Jul 03 04:28:47 PM PDT 24 |
Peak memory | 210244 kb |
Host | smart-c7105c12-06db-4f4c-8109-2a484d07c968 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148699284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2148699284 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1467076169 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 20275715 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:28:14 PM PDT 24 |
Finished | Jul 03 04:28:16 PM PDT 24 |
Peak memory | 201676 kb |
Host | smart-043f8da0-fddd-42c2-b8e4-b7f276c701a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467076169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1467076169 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.157627802 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 188004485 ps |
CPU time | 1.44 seconds |
Started | Jul 03 04:28:11 PM PDT 24 |
Finished | Jul 03 04:28:16 PM PDT 24 |
Peak memory | 201912 kb |
Host | smart-86bfe089-f591-40b4-b959-f14746f7ffac |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157627802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.157627802 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3351682020 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 26848103 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:11 PM PDT 24 |
Peak memory | 201812 kb |
Host | smart-2e1c80c2-ae0c-4a7f-9038-9f6a0abe4959 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351682020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3351682020 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2029103266 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 414785477 ps |
CPU time | 1.1 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:20 PM PDT 24 |
Peak memory | 210160 kb |
Host | smart-7b4beb30-f4eb-405e-a2f7-5982f36b9ed0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029103266 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2029103266 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3915221628 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 28191328 ps |
CPU time | 0.61 seconds |
Started | Jul 03 04:28:04 PM PDT 24 |
Finished | Jul 03 04:28:09 PM PDT 24 |
Peak memory | 201852 kb |
Host | smart-9d636ef3-2d24-484e-8fd0-5607a62600ba |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915221628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3915221628 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3136397552 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 452068790 ps |
CPU time | 3.25 seconds |
Started | Jul 03 04:28:18 PM PDT 24 |
Finished | Jul 03 04:28:22 PM PDT 24 |
Peak memory | 202220 kb |
Host | smart-4ad2c9fb-1808-4f7f-b2a6-a953ef06d9b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136397552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3136397552 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.197199063 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 41745852 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:28:07 PM PDT 24 |
Finished | Jul 03 04:28:13 PM PDT 24 |
Peak memory | 201916 kb |
Host | smart-560a71a3-e5e1-4c7a-9159-e15b1b903422 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197199063 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.197199063 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3552548745 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 54599238 ps |
CPU time | 4.05 seconds |
Started | Jul 03 04:28:02 PM PDT 24 |
Finished | Jul 03 04:28:10 PM PDT 24 |
Peak memory | 202132 kb |
Host | smart-dccf654a-578f-43ca-8089-3268f7c7c81a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552548745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3552548745 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2139427350 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 167369961 ps |
CPU time | 2.06 seconds |
Started | Jul 03 04:28:03 PM PDT 24 |
Finished | Jul 03 04:28:09 PM PDT 24 |
Peak memory | 210304 kb |
Host | smart-ecc88d53-bb3e-4aa2-b788-823a24575c06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139427350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.2139427350 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.428181754 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 16199679 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:28:08 PM PDT 24 |
Finished | Jul 03 04:28:13 PM PDT 24 |
Peak memory | 201824 kb |
Host | smart-dfb73a83-7df8-4ab2-9fd5-782081a557a7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428181754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.428181754 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3559556355 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 552691822 ps |
CPU time | 1.9 seconds |
Started | Jul 03 04:28:20 PM PDT 24 |
Finished | Jul 03 04:28:24 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-c5f69d97-49a9-4317-8800-4cc0f36bcf65 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559556355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.3559556355 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2249823861 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 28974262 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:28:02 PM PDT 24 |
Finished | Jul 03 04:28:06 PM PDT 24 |
Peak memory | 201860 kb |
Host | smart-0fa8cac3-eae9-4d64-8cf7-44d028cbde29 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249823861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2249823861 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1764030821 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 92676460 ps |
CPU time | 2.08 seconds |
Started | Jul 03 04:28:14 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 210340 kb |
Host | smart-62d718a7-2c56-4e12-92c7-9d1c2c66d410 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764030821 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1764030821 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3658001920 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 22973174 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:29:32 PM PDT 24 |
Finished | Jul 03 04:29:33 PM PDT 24 |
Peak memory | 201740 kb |
Host | smart-7127c73c-4c5c-4209-8c89-934c43b8dfd8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658001920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3658001920 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4293038021 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 6270180653 ps |
CPU time | 3.7 seconds |
Started | Jul 03 04:28:11 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 202240 kb |
Host | smart-489551fa-97c5-4236-82f9-117a7804d763 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293038021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.4293038021 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.367748277 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 30855941 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:28:26 PM PDT 24 |
Finished | Jul 03 04:28:27 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-733e28af-03de-436e-8639-d9e1b44d2895 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367748277 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.367748277 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2185765211 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 267113580 ps |
CPU time | 2.53 seconds |
Started | Jul 03 04:28:19 PM PDT 24 |
Finished | Jul 03 04:28:22 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-1dc0f486-720e-4dd2-840e-1800d9d16cb3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185765211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2185765211 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1796963001 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 224219626 ps |
CPU time | 2.31 seconds |
Started | Jul 03 04:28:06 PM PDT 24 |
Finished | Jul 03 04:28:14 PM PDT 24 |
Peak memory | 210348 kb |
Host | smart-5e885c70-2d45-42d8-a8ef-afbaf836b496 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796963001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1796963001 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3421532087 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 128992247 ps |
CPU time | 1.2 seconds |
Started | Jul 03 04:28:23 PM PDT 24 |
Finished | Jul 03 04:28:24 PM PDT 24 |
Peak memory | 210360 kb |
Host | smart-ff6d5360-0fd5-4cce-9732-05ea183e6d82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421532087 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3421532087 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2887328326 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 74559552 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:28:35 PM PDT 24 |
Finished | Jul 03 04:28:36 PM PDT 24 |
Peak memory | 201856 kb |
Host | smart-f22281d8-5ddd-4fe6-8ca4-2fcd2494af39 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887328326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.2887328326 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3682814070 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 428127136 ps |
CPU time | 3.11 seconds |
Started | Jul 03 04:28:36 PM PDT 24 |
Finished | Jul 03 04:28:40 PM PDT 24 |
Peak memory | 202196 kb |
Host | smart-6cda519b-5da2-407b-b285-83f4954ed785 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682814070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3682814070 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3018627062 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 15218299 ps |
CPU time | 0.71 seconds |
Started | Jul 03 04:28:38 PM PDT 24 |
Finished | Jul 03 04:28:39 PM PDT 24 |
Peak memory | 201896 kb |
Host | smart-e48b3837-f104-4b8c-bfb3-ed0396674e86 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018627062 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3018627062 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2277916033 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 69196850 ps |
CPU time | 2.21 seconds |
Started | Jul 03 04:28:23 PM PDT 24 |
Finished | Jul 03 04:28:26 PM PDT 24 |
Peak memory | 210360 kb |
Host | smart-b77aa904-60a4-470c-ad27-6bf17c6f91ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277916033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.2277916033 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.506809276 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 134257675 ps |
CPU time | 1.91 seconds |
Started | Jul 03 04:28:39 PM PDT 24 |
Finished | Jul 03 04:28:41 PM PDT 24 |
Peak memory | 211868 kb |
Host | smart-169db699-73ad-4149-ac62-34cff1ae48c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506809276 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.506809276 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2562606416 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 12549755 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:28:23 PM PDT 24 |
Finished | Jul 03 04:28:24 PM PDT 24 |
Peak memory | 201828 kb |
Host | smart-8223b9c7-358f-4295-afd5-c390d2b718e5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562606416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.2562606416 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1647348894 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 1195300118 ps |
CPU time | 3.78 seconds |
Started | Jul 03 04:28:25 PM PDT 24 |
Finished | Jul 03 04:28:30 PM PDT 24 |
Peak memory | 202232 kb |
Host | smart-dcab2a50-bdbe-4bc7-a1d6-e45422459148 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647348894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1647348894 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2775618241 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 19014263 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:28:45 PM PDT 24 |
Finished | Jul 03 04:28:46 PM PDT 24 |
Peak memory | 201900 kb |
Host | smart-afc5f90b-f367-4557-8f01-46aeffa27d44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775618241 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2775618241 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1547869175 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 64110509 ps |
CPU time | 4.6 seconds |
Started | Jul 03 04:28:19 PM PDT 24 |
Finished | Jul 03 04:28:25 PM PDT 24 |
Peak memory | 210308 kb |
Host | smart-808c1dca-4b2c-4e67-9e5f-ca3d02ba3ca4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547869175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1547869175 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.516241988 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 487648870 ps |
CPU time | 1.5 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:20 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-6302f092-02a5-4404-86fb-cdb347c20777 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516241988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.sram_ctrl_tl_intg_err.516241988 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1396931792 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 69150382 ps |
CPU time | 2.4 seconds |
Started | Jul 03 04:28:16 PM PDT 24 |
Finished | Jul 03 04:28:19 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-9f9016e3-69d4-470a-9745-b27ca45a2bd9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396931792 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1396931792 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1070080494 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1735675992 ps |
CPU time | 3.1 seconds |
Started | Jul 03 04:28:31 PM PDT 24 |
Finished | Jul 03 04:28:34 PM PDT 24 |
Peak memory | 202284 kb |
Host | smart-b0b6f6f9-0bac-44b3-8e2c-da8788cb727e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070080494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1070080494 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4017438210 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 24632370 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:28:16 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-375ba9be-eae5-4ad5-a11b-d98a5f0e05f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017438210 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.4017438210 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.411517966 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 77413428 ps |
CPU time | 2.85 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:21 PM PDT 24 |
Peak memory | 210284 kb |
Host | smart-fd2df04b-5f70-4819-8b89-1cce701bc483 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411517966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.411517966 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2408800849 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 332336849 ps |
CPU time | 1.59 seconds |
Started | Jul 03 04:28:29 PM PDT 24 |
Finished | Jul 03 04:28:31 PM PDT 24 |
Peak memory | 210336 kb |
Host | smart-cc16f931-fca3-4122-ab38-45d0b21e425c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408800849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2408800849 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2958869712 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 31885464 ps |
CPU time | 1.46 seconds |
Started | Jul 03 04:28:25 PM PDT 24 |
Finished | Jul 03 04:28:27 PM PDT 24 |
Peak memory | 211612 kb |
Host | smart-52ec33f1-bce6-40e8-b17c-8c5ca3b8dea0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958869712 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2958869712 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.314474206 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 20699413 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:28:24 PM PDT 24 |
Finished | Jul 03 04:28:30 PM PDT 24 |
Peak memory | 201768 kb |
Host | smart-428feb00-1c8b-41a6-a043-41dfbc798b20 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314474206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_csr_rw.314474206 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3153094020 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 439945073 ps |
CPU time | 3.25 seconds |
Started | Jul 03 04:28:18 PM PDT 24 |
Finished | Jul 03 04:28:22 PM PDT 24 |
Peak memory | 202220 kb |
Host | smart-77490111-a309-466e-bb7c-538b5b322ef0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153094020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3153094020 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4009056353 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 19067953 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:28:37 PM PDT 24 |
Finished | Jul 03 04:28:38 PM PDT 24 |
Peak memory | 201876 kb |
Host | smart-0dff51a5-f43a-4b3a-adc6-9007835d0f08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009056353 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.4009056353 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.774061905 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 445929872 ps |
CPU time | 4.19 seconds |
Started | Jul 03 04:28:33 PM PDT 24 |
Finished | Jul 03 04:28:38 PM PDT 24 |
Peak memory | 210196 kb |
Host | smart-950774df-dc30-44e6-bd7f-d94b7faa0da6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774061905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.774061905 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4000773242 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 135178796 ps |
CPU time | 1.24 seconds |
Started | Jul 03 04:28:38 PM PDT 24 |
Finished | Jul 03 04:28:39 PM PDT 24 |
Peak memory | 210216 kb |
Host | smart-db1cb71d-8526-4c9e-886c-1bb47dd9d495 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000773242 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.4000773242 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3714585629 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 175141227 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:35 PM PDT 24 |
Peak memory | 201816 kb |
Host | smart-e8f7d33c-e70b-40ef-8494-9f8f431fd866 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714585629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.3714585629 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.372550891 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 47611767 ps |
CPU time | 0.71 seconds |
Started | Jul 03 04:28:46 PM PDT 24 |
Finished | Jul 03 04:28:48 PM PDT 24 |
Peak memory | 201912 kb |
Host | smart-536a6e3c-0c60-4047-bde8-32c2461610b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372550891 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.372550891 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3016419965 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 30777784 ps |
CPU time | 1.96 seconds |
Started | Jul 03 04:28:35 PM PDT 24 |
Finished | Jul 03 04:28:37 PM PDT 24 |
Peak memory | 210364 kb |
Host | smart-efa36406-e590-4bab-b430-bd378e535a0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016419965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3016419965 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1021983058 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 261705105 ps |
CPU time | 2.33 seconds |
Started | Jul 03 04:28:40 PM PDT 24 |
Finished | Jul 03 04:28:43 PM PDT 24 |
Peak memory | 210240 kb |
Host | smart-dfbd1c72-ccae-4878-b71c-4d56e4a54cb7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021983058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1021983058 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1370222466 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 96754712 ps |
CPU time | 1.05 seconds |
Started | Jul 03 04:28:43 PM PDT 24 |
Finished | Jul 03 04:28:45 PM PDT 24 |
Peak memory | 210176 kb |
Host | smart-aacf60da-9da9-4912-806d-4c1dd8072b39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370222466 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1370222466 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4035798137 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 13210160 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:28:39 PM PDT 24 |
Finished | Jul 03 04:28:40 PM PDT 24 |
Peak memory | 201820 kb |
Host | smart-2c4aac42-fb1b-404c-abb6-3f2587e1a819 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035798137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.4035798137 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3977095171 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 811892746 ps |
CPU time | 1.94 seconds |
Started | Jul 03 04:28:50 PM PDT 24 |
Finished | Jul 03 04:28:57 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-7b62caf5-02c5-4e76-803b-bdc573173819 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977095171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3977095171 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4228508059 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 17417656 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:28:24 PM PDT 24 |
Finished | Jul 03 04:28:25 PM PDT 24 |
Peak memory | 201860 kb |
Host | smart-163f4a46-d5bb-49c3-81bf-6afad44b0b0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228508059 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.4228508059 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2863896043 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 37566897 ps |
CPU time | 1.9 seconds |
Started | Jul 03 04:28:36 PM PDT 24 |
Finished | Jul 03 04:28:38 PM PDT 24 |
Peak memory | 210380 kb |
Host | smart-500b0fb3-45bf-4b41-9fbd-bff9abdac4de |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863896043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.2863896043 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.689776876 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 645320138 ps |
CPU time | 3.28 seconds |
Started | Jul 03 04:28:38 PM PDT 24 |
Finished | Jul 03 04:28:42 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-80409ae7-0bb0-481a-81a8-bb96bd109f1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689776876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.689776876 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3549185747 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 197579854 ps |
CPU time | 1.29 seconds |
Started | Jul 03 04:28:28 PM PDT 24 |
Finished | Jul 03 04:28:30 PM PDT 24 |
Peak memory | 210160 kb |
Host | smart-e17796b8-f186-40fb-8b42-9f5963cfa0b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549185747 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3549185747 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3425913697 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 18904700 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:28:24 PM PDT 24 |
Finished | Jul 03 04:28:25 PM PDT 24 |
Peak memory | 201876 kb |
Host | smart-466551af-7ef9-40d9-81f7-3c5ded1c0130 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425913697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.3425913697 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.706240276 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 2014490346 ps |
CPU time | 3.78 seconds |
Started | Jul 03 04:28:36 PM PDT 24 |
Finished | Jul 03 04:28:40 PM PDT 24 |
Peak memory | 202208 kb |
Host | smart-72e223d7-d9a1-4a71-8881-560cb5b087f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706240276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.706240276 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2318768326 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 31547341 ps |
CPU time | 0.74 seconds |
Started | Jul 03 04:28:40 PM PDT 24 |
Finished | Jul 03 04:28:41 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-2eb5e038-f8d8-48e7-a438-e1077504eb9e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318768326 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2318768326 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.733009353 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 40860765 ps |
CPU time | 3.86 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:39 PM PDT 24 |
Peak memory | 202184 kb |
Host | smart-61548ed9-83dc-459c-b260-c58565ef8653 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733009353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.733009353 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2042967745 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 127093591 ps |
CPU time | 1.86 seconds |
Started | Jul 03 04:28:22 PM PDT 24 |
Finished | Jul 03 04:28:25 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-4fce010b-9fd5-4b6b-9336-b9972e4371e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042967745 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2042967745 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2786176116 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 22833329 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:28:32 PM PDT 24 |
Finished | Jul 03 04:28:33 PM PDT 24 |
Peak memory | 201832 kb |
Host | smart-01cba30e-70f8-4ed0-a6e9-cd769a7660fe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786176116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.2786176116 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3048428860 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 810081605 ps |
CPU time | 2.05 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:37 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-ac3a9cea-3472-4681-8e19-a426fe798c58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048428860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3048428860 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1930515693 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 105112400 ps |
CPU time | 0.7 seconds |
Started | Jul 03 04:28:40 PM PDT 24 |
Finished | Jul 03 04:28:41 PM PDT 24 |
Peak memory | 201908 kb |
Host | smart-2d944783-2883-4671-8f31-d59154726d5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930515693 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1930515693 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3987605127 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 71015645 ps |
CPU time | 1.74 seconds |
Started | Jul 03 04:28:31 PM PDT 24 |
Finished | Jul 03 04:28:33 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-7f5b8d6d-3e6c-4bdf-894e-7b4fa5acff2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987605127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.3987605127 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.989034688 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 135149493 ps |
CPU time | 1.61 seconds |
Started | Jul 03 04:28:49 PM PDT 24 |
Finished | Jul 03 04:28:51 PM PDT 24 |
Peak memory | 210296 kb |
Host | smart-d9c99936-2ae9-4264-85bc-aa9660e1bc66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989034688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sram_ctrl_tl_intg_err.989034688 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1823519029 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 349392550 ps |
CPU time | 1.47 seconds |
Started | Jul 03 04:28:31 PM PDT 24 |
Finished | Jul 03 04:28:33 PM PDT 24 |
Peak memory | 210388 kb |
Host | smart-f6347ea7-7d9f-4bff-a730-79e747e2c998 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823519029 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1823519029 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2122292497 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 41559076 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:28:38 PM PDT 24 |
Finished | Jul 03 04:28:39 PM PDT 24 |
Peak memory | 201852 kb |
Host | smart-2be79aaa-af03-4bf3-a088-a011bf835006 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122292497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.2122292497 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3628683810 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 828657945 ps |
CPU time | 1.92 seconds |
Started | Jul 03 04:28:39 PM PDT 24 |
Finished | Jul 03 04:28:42 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-df96476a-98df-4215-896d-700fa76a1bd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628683810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3628683810 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.579819230 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 20451234 ps |
CPU time | 0.81 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:36 PM PDT 24 |
Peak memory | 201924 kb |
Host | smart-4f3dd9af-fcec-4eaf-86bd-d1e29c6d71f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579819230 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.579819230 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1705395443 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 79386266 ps |
CPU time | 2.8 seconds |
Started | Jul 03 04:28:33 PM PDT 24 |
Finished | Jul 03 04:28:37 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-c675d257-dedf-463a-9d7b-3eb10a1db3ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705395443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.1705395443 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1938555732 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1656473750 ps |
CPU time | 2.83 seconds |
Started | Jul 03 04:28:43 PM PDT 24 |
Finished | Jul 03 04:28:46 PM PDT 24 |
Peak memory | 210276 kb |
Host | smart-53e6f25f-d492-4c4f-9315-7698684ded43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938555732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.1938555732 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4082977141 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 68953669 ps |
CPU time | 1.75 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:36 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-33273b91-ab25-4f8f-aa57-f958423565ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082977141 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.4082977141 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4022969574 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 12827839 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:28:46 PM PDT 24 |
Finished | Jul 03 04:28:47 PM PDT 24 |
Peak memory | 201356 kb |
Host | smart-b44a2bb2-7380-4d97-a0a5-f852a1eef928 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022969574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.4022969574 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1637026645 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 1550301358 ps |
CPU time | 2.2 seconds |
Started | Jul 03 04:28:55 PM PDT 24 |
Finished | Jul 03 04:28:58 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-b8888a67-ee14-4932-88fb-dcedd2073579 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637026645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1637026645 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2881411441 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 14429984 ps |
CPU time | 0.7 seconds |
Started | Jul 03 04:28:40 PM PDT 24 |
Finished | Jul 03 04:28:41 PM PDT 24 |
Peak memory | 201808 kb |
Host | smart-6bee5040-60c9-462c-9c89-fe63d70ec8b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881411441 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2881411441 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.794445807 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 81388736 ps |
CPU time | 3.03 seconds |
Started | Jul 03 04:28:46 PM PDT 24 |
Finished | Jul 03 04:28:49 PM PDT 24 |
Peak memory | 210316 kb |
Host | smart-fe95dda9-5e02-4126-9f21-09b2f0b266bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794445807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.794445807 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.184497117 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 373825359 ps |
CPU time | 1.46 seconds |
Started | Jul 03 04:28:23 PM PDT 24 |
Finished | Jul 03 04:28:25 PM PDT 24 |
Peak memory | 210300 kb |
Host | smart-8c9b371e-d239-4601-a298-874c9e77ca4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184497117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.sram_ctrl_tl_intg_err.184497117 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1120163701 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 36479499 ps |
CPU time | 0.73 seconds |
Started | Jul 03 04:28:03 PM PDT 24 |
Finished | Jul 03 04:28:07 PM PDT 24 |
Peak memory | 201848 kb |
Host | smart-e5c4137f-8fd7-4524-b09c-5f54c9cbca93 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120163701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.1120163701 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.912267232 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 42814007 ps |
CPU time | 1.84 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:12 PM PDT 24 |
Peak memory | 201984 kb |
Host | smart-da3d94b1-4971-4423-adf6-4fc1b4f12b0c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912267232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.912267232 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.664521589 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 16178739 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:29:30 PM PDT 24 |
Finished | Jul 03 04:29:30 PM PDT 24 |
Peak memory | 201744 kb |
Host | smart-039060ad-b498-440c-b351-75b17e387f5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664521589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.664521589 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4075303249 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 13849968 ps |
CPU time | 0.68 seconds |
Started | Jul 03 04:28:23 PM PDT 24 |
Finished | Jul 03 04:28:25 PM PDT 24 |
Peak memory | 201832 kb |
Host | smart-6ec07e24-9686-41fd-b7bb-eac18fd4853b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075303249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.4075303249 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1923766245 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 284877343 ps |
CPU time | 1.96 seconds |
Started | Jul 03 04:28:15 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-7bbfaf08-3188-4d9d-ad41-b468e3f1aec6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923766245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1923766245 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3607656490 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 16287594 ps |
CPU time | 0.68 seconds |
Started | Jul 03 04:28:20 PM PDT 24 |
Finished | Jul 03 04:28:21 PM PDT 24 |
Peak memory | 201872 kb |
Host | smart-2dc16f86-f022-4036-8994-0b57c596f997 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607656490 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3607656490 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1448528131 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 191252069 ps |
CPU time | 3.32 seconds |
Started | Jul 03 04:28:19 PM PDT 24 |
Finished | Jul 03 04:28:23 PM PDT 24 |
Peak memory | 210320 kb |
Host | smart-4ab6c7e9-15fe-4d72-9b63-a9ead8a5ee64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448528131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.1448528131 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2709221510 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1184427455 ps |
CPU time | 2.3 seconds |
Started | Jul 03 04:28:23 PM PDT 24 |
Finished | Jul 03 04:28:26 PM PDT 24 |
Peak memory | 210296 kb |
Host | smart-5adc24b4-9e10-430f-88a0-0fdf2208500f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709221510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2709221510 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2637851313 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 19983927 ps |
CPU time | 0.69 seconds |
Started | Jul 03 04:28:14 PM PDT 24 |
Finished | Jul 03 04:28:16 PM PDT 24 |
Peak memory | 201848 kb |
Host | smart-48235b62-aed0-4b2e-a15f-d5cbc065896c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637851313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.2637851313 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2885737622 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 546026774 ps |
CPU time | 2.08 seconds |
Started | Jul 03 04:29:02 PM PDT 24 |
Finished | Jul 03 04:29:05 PM PDT 24 |
Peak memory | 201108 kb |
Host | smart-c50ffa39-dec6-4dfd-99a6-3136882bb55d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885737622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.2885737622 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3963682512 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 36668596 ps |
CPU time | 0.62 seconds |
Started | Jul 03 04:28:16 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 201848 kb |
Host | smart-7056ea09-d8cb-4eed-a27a-fa6b6ba3171f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963682512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.3963682512 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4288354382 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 43748051 ps |
CPU time | 1.02 seconds |
Started | Jul 03 04:28:04 PM PDT 24 |
Finished | Jul 03 04:28:10 PM PDT 24 |
Peak memory | 210108 kb |
Host | smart-f0967032-c2b9-4e7d-907d-59bcbf79cc08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288354382 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.4288354382 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1536536655 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 13863930 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:28:15 PM PDT 24 |
Finished | Jul 03 04:28:17 PM PDT 24 |
Peak memory | 201828 kb |
Host | smart-9df5ced2-fd54-4002-bbb0-b8917848a642 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536536655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1536536655 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3847359025 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 1278040839 ps |
CPU time | 2.31 seconds |
Started | Jul 03 04:28:03 PM PDT 24 |
Finished | Jul 03 04:28:10 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-a95b0ae8-906f-4a55-b51e-57e1c613cf53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847359025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3847359025 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1067214107 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 21529287 ps |
CPU time | 0.71 seconds |
Started | Jul 03 04:28:11 PM PDT 24 |
Finished | Jul 03 04:28:15 PM PDT 24 |
Peak memory | 201888 kb |
Host | smart-4d3e12fc-5855-4d8b-bde2-a4acb30db62c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067214107 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1067214107 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3959232627 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 172196635 ps |
CPU time | 2.88 seconds |
Started | Jul 03 04:29:21 PM PDT 24 |
Finished | Jul 03 04:29:24 PM PDT 24 |
Peak memory | 210300 kb |
Host | smart-3e6015b9-ebfa-418d-b4cb-deb89bd25267 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959232627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.3959232627 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3300203909 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 370511177 ps |
CPU time | 1.44 seconds |
Started | Jul 03 04:28:02 PM PDT 24 |
Finished | Jul 03 04:28:08 PM PDT 24 |
Peak memory | 210344 kb |
Host | smart-f17491b3-1009-42e9-8c7a-02d2ec5f9497 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300203909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.3300203909 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2041503899 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 169728429 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:28:04 PM PDT 24 |
Finished | Jul 03 04:28:14 PM PDT 24 |
Peak memory | 201804 kb |
Host | smart-5c5a6ed1-7918-43ef-b3e4-0ccd75f09c67 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041503899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2041503899 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1836157845 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 86238826 ps |
CPU time | 1.2 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:20 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-0f478de6-2750-49a0-a9bc-15367abad956 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836157845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.1836157845 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3140705984 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 175070505 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:19 PM PDT 24 |
Peak memory | 201736 kb |
Host | smart-bd75f754-dd9d-4c33-8c3b-8bf9d84c5ce3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140705984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.3140705984 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2310505350 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 262343264 ps |
CPU time | 1.14 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:20 PM PDT 24 |
Peak memory | 210180 kb |
Host | smart-b2843279-529d-4274-80fd-ed9dedfab40b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310505350 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2310505350 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2842584087 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 15398514 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:11 PM PDT 24 |
Peak memory | 201800 kb |
Host | smart-13fc56d9-148f-4305-b467-ebd28adc72a7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842584087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.2842584087 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2503201998 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 222119431 ps |
CPU time | 1.98 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:13 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-029289ae-06b0-4188-9a34-fcb380590886 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503201998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2503201998 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1675699372 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 84408991 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:14 PM PDT 24 |
Peak memory | 201896 kb |
Host | smart-81c25ab5-c7c7-44cc-accc-2c3c2340a732 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675699372 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1675699372 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4011687890 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 117758066 ps |
CPU time | 3.87 seconds |
Started | Jul 03 04:28:07 PM PDT 24 |
Finished | Jul 03 04:28:16 PM PDT 24 |
Peak memory | 210324 kb |
Host | smart-e83f39a5-3230-4a97-b6cd-200e8de39bb8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011687890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.4011687890 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4241446763 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 679950323 ps |
CPU time | 2.4 seconds |
Started | Jul 03 04:28:24 PM PDT 24 |
Finished | Jul 03 04:28:27 PM PDT 24 |
Peak memory | 210300 kb |
Host | smart-065448ea-1093-43a8-a6a9-4134a5c63476 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241446763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.4241446763 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1204594956 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 45105577 ps |
CPU time | 0.86 seconds |
Started | Jul 03 04:28:30 PM PDT 24 |
Finished | Jul 03 04:28:31 PM PDT 24 |
Peak memory | 201976 kb |
Host | smart-493163aa-5564-4a7e-8391-48a0b5782865 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204594956 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1204594956 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4145005588 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 23359095 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:28:01 PM PDT 24 |
Finished | Jul 03 04:28:07 PM PDT 24 |
Peak memory | 201276 kb |
Host | smart-515237a7-1359-4ab7-a087-dcdc6ea1ec68 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145005588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.4145005588 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1280663626 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 864659566 ps |
CPU time | 2 seconds |
Started | Jul 03 04:28:13 PM PDT 24 |
Finished | Jul 03 04:28:17 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-43c3c678-149e-4eca-8a22-02227e50cbe6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280663626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1280663626 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.155561269 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 88094574 ps |
CPU time | 0.79 seconds |
Started | Jul 03 04:28:11 PM PDT 24 |
Finished | Jul 03 04:28:15 PM PDT 24 |
Peak memory | 201880 kb |
Host | smart-0fe051fa-4ffe-45ba-b14b-cf30a3951ca6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155561269 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.155561269 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1809454265 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 346589738 ps |
CPU time | 3.63 seconds |
Started | Jul 03 04:28:01 PM PDT 24 |
Finished | Jul 03 04:28:07 PM PDT 24 |
Peak memory | 210296 kb |
Host | smart-6837226f-9277-4618-8dbb-9a30436c0746 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809454265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1809454265 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2307204449 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 99491513 ps |
CPU time | 0.92 seconds |
Started | Jul 03 04:28:33 PM PDT 24 |
Finished | Jul 03 04:28:35 PM PDT 24 |
Peak memory | 210176 kb |
Host | smart-ced07c8b-6871-4710-95b0-a396db6ac969 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307204449 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2307204449 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.34406561 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 30460517 ps |
CPU time | 0.6 seconds |
Started | Jul 03 04:28:03 PM PDT 24 |
Finished | Jul 03 04:28:08 PM PDT 24 |
Peak memory | 201272 kb |
Host | smart-5c4ef642-58f4-4270-80c1-ebad19fb96d2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34406561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 6.sram_ctrl_csr_rw.34406561 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3473805614 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 215332593 ps |
CPU time | 1.85 seconds |
Started | Jul 03 04:28:30 PM PDT 24 |
Finished | Jul 03 04:28:32 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-c086d350-0976-4ef9-b2cc-5ffa7b01ddda |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473805614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3473805614 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3647481728 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 23356147 ps |
CPU time | 0.7 seconds |
Started | Jul 03 04:28:18 PM PDT 24 |
Finished | Jul 03 04:28:20 PM PDT 24 |
Peak memory | 201816 kb |
Host | smart-de586b54-054a-4282-b2b4-f89937544d55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647481728 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3647481728 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1990518369 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 907624019 ps |
CPU time | 3.91 seconds |
Started | Jul 03 04:28:30 PM PDT 24 |
Finished | Jul 03 04:28:35 PM PDT 24 |
Peak memory | 210360 kb |
Host | smart-3d0d3c8d-956f-46cc-ba19-18ff42fc18c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990518369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.1990518369 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1589739639 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 275179167 ps |
CPU time | 1.38 seconds |
Started | Jul 03 04:28:20 PM PDT 24 |
Finished | Jul 03 04:28:22 PM PDT 24 |
Peak memory | 210304 kb |
Host | smart-4cb67a5b-9d0d-4e43-b4f7-89ecd95c3645 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589739639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1589739639 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.245372214 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 52545697 ps |
CPU time | 1.33 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:36 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-f1d47706-7657-4d00-b3bd-0a37236f09ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245372214 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.245372214 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3836318725 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 59774077 ps |
CPU time | 0.62 seconds |
Started | Jul 03 04:28:15 PM PDT 24 |
Finished | Jul 03 04:28:17 PM PDT 24 |
Peak memory | 201852 kb |
Host | smart-2f217ca8-2821-4902-a122-70259a882369 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836318725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3836318725 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3965740010 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 1664845568 ps |
CPU time | 2.96 seconds |
Started | Jul 03 04:28:28 PM PDT 24 |
Finished | Jul 03 04:28:31 PM PDT 24 |
Peak memory | 202212 kb |
Host | smart-554ec491-643f-4420-9ba2-5cdf958e6a1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965740010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3965740010 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.403281465 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 13829459 ps |
CPU time | 0.71 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:11 PM PDT 24 |
Peak memory | 201924 kb |
Host | smart-900259d1-c986-4be5-a429-df8cf35a45c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403281465 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.403281465 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1218302709 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 264445705 ps |
CPU time | 4.41 seconds |
Started | Jul 03 04:28:05 PM PDT 24 |
Finished | Jul 03 04:28:15 PM PDT 24 |
Peak memory | 202188 kb |
Host | smart-bc2777d5-70f3-4c22-938d-6993e28459c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218302709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1218302709 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3132268311 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 308338326 ps |
CPU time | 1.44 seconds |
Started | Jul 03 04:28:01 PM PDT 24 |
Finished | Jul 03 04:28:04 PM PDT 24 |
Peak memory | 210260 kb |
Host | smart-822fc2b5-fcf1-4e1b-a0b2-3a1159e005f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132268311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.3132268311 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2767431304 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 36941064 ps |
CPU time | 1.01 seconds |
Started | Jul 03 04:28:15 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 210168 kb |
Host | smart-b2dd977f-0dc0-4f34-839d-bafd48b6b1f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767431304 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2767431304 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1469677389 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 21567877 ps |
CPU time | 0.61 seconds |
Started | Jul 03 04:28:17 PM PDT 24 |
Finished | Jul 03 04:28:19 PM PDT 24 |
Peak memory | 201796 kb |
Host | smart-036142f3-dadd-497a-a686-0412bada2ed9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469677389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.1469677389 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1401247914 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 835109722 ps |
CPU time | 2.05 seconds |
Started | Jul 03 04:28:02 PM PDT 24 |
Finished | Jul 03 04:28:07 PM PDT 24 |
Peak memory | 201968 kb |
Host | smart-8e386260-942e-4d22-9532-facd7387853c |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401247914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1401247914 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3678812872 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 78204304 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:28:27 PM PDT 24 |
Finished | Jul 03 04:28:28 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-430a3ae1-49ea-4b42-9731-e5d50c517dfb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678812872 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3678812872 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.585061407 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 68986715 ps |
CPU time | 3.22 seconds |
Started | Jul 03 04:28:04 PM PDT 24 |
Finished | Jul 03 04:28:13 PM PDT 24 |
Peak memory | 210296 kb |
Host | smart-be00c308-87be-4065-a3fd-9204df239286 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585061407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.585061407 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4009370838 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 230042871 ps |
CPU time | 1.44 seconds |
Started | Jul 03 04:28:03 PM PDT 24 |
Finished | Jul 03 04:28:09 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-fdd8deb8-e777-4d95-bfb4-bc150eeba15c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009370838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.4009370838 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.416259543 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 44880456 ps |
CPU time | 1.12 seconds |
Started | Jul 03 04:28:25 PM PDT 24 |
Finished | Jul 03 04:28:26 PM PDT 24 |
Peak memory | 210164 kb |
Host | smart-c2310df3-c274-4ebc-ba19-9b04af02d62e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416259543 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.416259543 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2533625484 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 27906826 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:28:31 PM PDT 24 |
Finished | Jul 03 04:28:32 PM PDT 24 |
Peak memory | 201380 kb |
Host | smart-a2a31ce3-5eab-4d0f-b742-e3f654cebe55 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533625484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2533625484 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2591184853 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 279135155 ps |
CPU time | 1.9 seconds |
Started | Jul 03 04:28:26 PM PDT 24 |
Finished | Jul 03 04:28:29 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-d7705105-8316-4338-aef0-5c2da63f95f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591184853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2591184853 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3622557223 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 44520491 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:28:34 PM PDT 24 |
Finished | Jul 03 04:28:35 PM PDT 24 |
Peak memory | 201896 kb |
Host | smart-76d352a9-a7c7-40c4-a580-a4eb276dd8aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622557223 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3622557223 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2219690546 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 61173765 ps |
CPU time | 2.53 seconds |
Started | Jul 03 04:28:13 PM PDT 24 |
Finished | Jul 03 04:28:18 PM PDT 24 |
Peak memory | 202164 kb |
Host | smart-2f01e60f-a62f-4c43-9fa1-9e70a68c38ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219690546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2219690546 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.134694178 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 117354504 ps |
CPU time | 1.54 seconds |
Started | Jul 03 04:28:26 PM PDT 24 |
Finished | Jul 03 04:28:28 PM PDT 24 |
Peak memory | 210276 kb |
Host | smart-ba64bbcf-94d1-4017-89a6-c99dcf366dd0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134694178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sram_ctrl_tl_intg_err.134694178 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2512047452 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 2000740847 ps |
CPU time | 458.59 seconds |
Started | Jul 03 04:32:23 PM PDT 24 |
Finished | Jul 03 04:40:02 PM PDT 24 |
Peak memory | 361184 kb |
Host | smart-9f1ddff2-707c-42b1-aefd-95afd996ad50 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512047452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.2512047452 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.194783903 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 2941558107 ps |
CPU time | 63.51 seconds |
Started | Jul 03 04:32:04 PM PDT 24 |
Finished | Jul 03 04:33:08 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-e81460ef-41fe-40cb-b495-b4980ba62588 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194783903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.194783903 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.3012385383 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 18089312625 ps |
CPU time | 1422.3 seconds |
Started | Jul 03 04:31:52 PM PDT 24 |
Finished | Jul 03 04:55:35 PM PDT 24 |
Peak memory | 373544 kb |
Host | smart-96dde4b4-f443-46b7-8af9-45c0e43f61fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012385383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3012385383 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.2598680772 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 515119606 ps |
CPU time | 4.87 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:32:19 PM PDT 24 |
Peak memory | 210884 kb |
Host | smart-1e4be911-061b-4e9f-b2ca-b520185c569f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598680772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.2598680772 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.2520648822 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 211528172 ps |
CPU time | 3.99 seconds |
Started | Jul 03 04:32:05 PM PDT 24 |
Finished | Jul 03 04:32:10 PM PDT 24 |
Peak memory | 223264 kb |
Host | smart-10b7b1e5-364c-41b7-9b15-b22e8d8415a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520648822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2520648822 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.944924190 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 1193334110 ps |
CPU time | 4.61 seconds |
Started | Jul 03 04:32:06 PM PDT 24 |
Finished | Jul 03 04:32:11 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-2c64bddb-ce11-4711-ad66-4fba22ebe920 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944924190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.944924190 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.2897675813 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 91304450 ps |
CPU time | 4.56 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 04:32:14 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-ab6063d9-9c0a-41ec-bc80-4b033e00265a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897675813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.2897675813 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.1769754603 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 25176737657 ps |
CPU time | 735.8 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:44:36 PM PDT 24 |
Peak memory | 371564 kb |
Host | smart-0097ff5c-6af1-4e84-a991-7aa0ea5824f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769754603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.1769754603 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.2391357700 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 505345292 ps |
CPU time | 13.73 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:32:34 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-b190989b-3fc0-48bc-af33-b4ec51b5ef5d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391357700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.2391357700 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1267508225 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 8816217178 ps |
CPU time | 259.34 seconds |
Started | Jul 03 04:32:10 PM PDT 24 |
Finished | Jul 03 04:36:31 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-4656c53e-53ea-4164-a5b5-df37498f7977 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267508225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1267508225 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.2656928599 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 32234721 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:32:17 PM PDT 24 |
Finished | Jul 03 04:32:19 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-6ebf990f-d8ff-406b-8013-334fe22c769a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656928599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2656928599 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.278185063 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 3002573162 ps |
CPU time | 854.15 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:46:29 PM PDT 24 |
Peak memory | 369500 kb |
Host | smart-44ccffeb-f648-4ab8-b016-558dfa757144 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278185063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.278185063 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.1045307217 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 749017220 ps |
CPU time | 11.89 seconds |
Started | Jul 03 04:31:48 PM PDT 24 |
Finished | Jul 03 04:32:01 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-26cb1c85-40a6-43c7-9e7d-93df4a3ea299 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045307217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1045307217 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.2741350485 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 11615797015 ps |
CPU time | 932 seconds |
Started | Jul 03 04:32:07 PM PDT 24 |
Finished | Jul 03 04:47:40 PM PDT 24 |
Peak memory | 375752 kb |
Host | smart-da4819e0-f37c-4792-b281-de4566e2363f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741350485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.2741350485 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.335341740 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 771326669 ps |
CPU time | 180.83 seconds |
Started | Jul 03 04:32:14 PM PDT 24 |
Finished | Jul 03 04:35:16 PM PDT 24 |
Peak memory | 342620 kb |
Host | smart-7969c09d-653d-44df-8135-e8566fbe195d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=335341740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.335341740 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.400437654 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 6739714863 ps |
CPU time | 372.24 seconds |
Started | Jul 03 04:32:16 PM PDT 24 |
Finished | Jul 03 04:38:29 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-ac99aa8c-6108-428a-bed4-4953f84df520 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400437654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_stress_pipeline.400437654 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1976960642 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 67822360 ps |
CPU time | 2.54 seconds |
Started | Jul 03 04:31:59 PM PDT 24 |
Finished | Jul 03 04:32:02 PM PDT 24 |
Peak memory | 217928 kb |
Host | smart-b77ededc-332e-4846-be76-3d0628be1a13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976960642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1976960642 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2224512006 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 4463287422 ps |
CPU time | 937.1 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:48:04 PM PDT 24 |
Peak memory | 357212 kb |
Host | smart-5733ef3a-6a8c-448a-8e47-0847d4ee3051 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224512006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.2224512006 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.2843871980 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 34911749 ps |
CPU time | 0.62 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:32:25 PM PDT 24 |
Peak memory | 202272 kb |
Host | smart-3fdfd64f-a948-4ed1-8dc3-f792748e6517 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843871980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2843871980 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.1052456121 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 924880199 ps |
CPU time | 58.61 seconds |
Started | Jul 03 04:32:00 PM PDT 24 |
Finished | Jul 03 04:33:00 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-5ceaf379-c5e4-4ea0-b7e1-0cd05ad90fb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052456121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 1052456121 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.2922992619 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 974439829 ps |
CPU time | 484.47 seconds |
Started | Jul 03 04:32:02 PM PDT 24 |
Finished | Jul 03 04:40:07 PM PDT 24 |
Peak memory | 355080 kb |
Host | smart-9f4a352c-ec9b-461d-ab01-529d84e86f9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922992619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.2922992619 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.1052295130 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2650146104 ps |
CPU time | 8.4 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 04:32:18 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-68cdee77-3eb1-4d7c-b4da-970d2043eb8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052295130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1052295130 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1085886492 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 125443280 ps |
CPU time | 70 seconds |
Started | Jul 03 04:32:05 PM PDT 24 |
Finished | Jul 03 04:33:15 PM PDT 24 |
Peak memory | 348556 kb |
Host | smart-5687eabd-ee7f-4326-8372-f407c68ba015 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085886492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1085886492 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1822780889 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 157905676 ps |
CPU time | 2.6 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:32:22 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-2a2844ab-8d86-42b9-a742-babb0fb0cac0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822780889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.1822780889 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.1450811562 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 1295122914 ps |
CPU time | 10.31 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-429b4385-a415-46fd-874b-cb1cc94c420b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450811562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.1450811562 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.1982934687 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 1555869981 ps |
CPU time | 468.13 seconds |
Started | Jul 03 04:32:08 PM PDT 24 |
Finished | Jul 03 04:39:57 PM PDT 24 |
Peak memory | 374592 kb |
Host | smart-ce981ea8-9993-4e5e-bc9b-3ec08b8258dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982934687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.1982934687 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.2115734109 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 408829812 ps |
CPU time | 141.5 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:34:44 PM PDT 24 |
Peak memory | 359040 kb |
Host | smart-234f0705-fc89-4dea-92c5-13b9b897b19f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115734109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.2115734109 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1520021455 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 79623515816 ps |
CPU time | 288.2 seconds |
Started | Jul 03 04:31:59 PM PDT 24 |
Finished | Jul 03 04:36:47 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-281665f1-2f66-45d4-9abf-29c634e0350c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520021455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.1520021455 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.3521544101 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 78179677 ps |
CPU time | 0.74 seconds |
Started | Jul 03 04:31:57 PM PDT 24 |
Finished | Jul 03 04:31:58 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-d7817b01-55a2-4775-947c-6ac910c86fd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521544101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3521544101 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.3821446460 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 184323075 ps |
CPU time | 2.01 seconds |
Started | Jul 03 04:31:54 PM PDT 24 |
Finished | Jul 03 04:31:57 PM PDT 24 |
Peak memory | 221884 kb |
Host | smart-a09ea153-c6d7-450d-86dc-348e20d19bff |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821446460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3821446460 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.820319172 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 1436264857 ps |
CPU time | 8.43 seconds |
Started | Jul 03 04:32:02 PM PDT 24 |
Finished | Jul 03 04:32:11 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-136eefcd-5a08-4fb4-86a2-a4b3e157af5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820319172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.820319172 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.3013086311 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 12217817717 ps |
CPU time | 4130.92 seconds |
Started | Jul 03 04:31:57 PM PDT 24 |
Finished | Jul 03 05:40:49 PM PDT 24 |
Peak memory | 377104 kb |
Host | smart-4a0cb3b9-14ea-46ee-a467-7da5440731fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013086311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.3013086311 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3943262253 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 717098071 ps |
CPU time | 70.32 seconds |
Started | Jul 03 04:32:11 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 314460 kb |
Host | smart-bcf50fe7-690f-493a-b4b7-d25e67499165 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3943262253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3943262253 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1640416273 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 49328533684 ps |
CPU time | 242.4 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:36:29 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-33922c09-7b9f-4752-ab10-f03535e1c329 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640416273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1640416273 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.732447848 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 873397006 ps |
CPU time | 116.05 seconds |
Started | Jul 03 04:31:57 PM PDT 24 |
Finished | Jul 03 04:33:53 PM PDT 24 |
Peak memory | 363364 kb |
Host | smart-654ba1eb-d017-4de0-a08f-fea72ebabd72 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732447848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.732447848 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1279418901 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 1549358807 ps |
CPU time | 355.13 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:38:28 PM PDT 24 |
Peak memory | 358816 kb |
Host | smart-427463a7-fed6-410a-940c-3ac0baa42a4b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279418901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.1279418901 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.496726851 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 40489320 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:32:20 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-0ebe7c9a-90aa-472e-b048-d3d8e578e0b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496726851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.496726851 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.569301692 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 5681867841 ps |
CPU time | 25.86 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:32:50 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-a9f41a64-dc40-41ce-ba1c-bedf526e1dc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569301692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 569301692 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.3498154861 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 2194867422 ps |
CPU time | 226.34 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:36:29 PM PDT 24 |
Peak memory | 373600 kb |
Host | smart-3dd5d298-f9df-4abb-a739-322c61205cd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498154861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.3498154861 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.2212612351 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 1178225344 ps |
CPU time | 5.03 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:32:38 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-27f61dc5-c518-4bbe-a6a6-3fb7baaa1345 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212612351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.2212612351 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.2476349545 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 230339300 ps |
CPU time | 52.22 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:33:25 PM PDT 24 |
Peak memory | 340760 kb |
Host | smart-29ee8e1a-68e1-4540-8ea2-a2bedde7b912 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476349545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.2476349545 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.841613063 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 108891598 ps |
CPU time | 3.09 seconds |
Started | Jul 03 04:32:39 PM PDT 24 |
Finished | Jul 03 04:32:42 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-786a7736-125f-46d4-acdd-224e7cf0dbe8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841613063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_mem_partial_access.841613063 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.3460993332 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 927595728 ps |
CPU time | 6.14 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-72a18edc-d242-47d2-a1d0-820d169936fa |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460993332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3460993332 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.2728953091 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 60863656753 ps |
CPU time | 1031.63 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:49:43 PM PDT 24 |
Peak memory | 375604 kb |
Host | smart-10c4762d-1770-4e9c-9f2a-4c370f485505 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728953091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2728953091 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.2540470218 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 78367317 ps |
CPU time | 3.02 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:32:48 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-84b767c4-3e8a-43c6-ae9a-6d08f8173fb2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540470218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.2540470218 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1119810136 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 34687642434 ps |
CPU time | 436.08 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:39:51 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-d84eba49-9d04-4cde-bc8b-71fbd9a0a35b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119810136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.1119810136 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.927779844 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 40390407 ps |
CPU time | 0.83 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:31 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-aa60b5ac-70b2-4830-8a89-8c31acbb7c47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927779844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.927779844 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.2819841929 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 3569343915 ps |
CPU time | 1079.75 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:51:01 PM PDT 24 |
Peak memory | 374800 kb |
Host | smart-02fa87d1-fa03-4ec4-8be4-c800f144d8fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819841929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2819841929 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.3461262105 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1808919019 ps |
CPU time | 34.09 seconds |
Started | Jul 03 04:32:39 PM PDT 24 |
Finished | Jul 03 04:33:14 PM PDT 24 |
Peak memory | 299700 kb |
Host | smart-61f70ac9-bcd3-4aa1-8c51-d0bcf005f1f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461262105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3461262105 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.3639575251 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 391796221554 ps |
CPU time | 4824.49 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 05:52:55 PM PDT 24 |
Peak memory | 376804 kb |
Host | smart-e134edbf-35c1-41dd-ae67-ff6674c6b707 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639575251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.3639575251 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3525566162 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 11282202201 ps |
CPU time | 401.6 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:39:14 PM PDT 24 |
Peak memory | 343028 kb |
Host | smart-e5671a84-f92b-49e2-a1dc-8ee98982be65 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3525566162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3525566162 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.877565513 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 4950630535 ps |
CPU time | 241.87 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:36:23 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-32e2a232-0d65-4aea-9400-d9c2f440cae4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877565513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_stress_pipeline.877565513 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2106406895 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 191821727 ps |
CPU time | 146.55 seconds |
Started | Jul 03 04:32:23 PM PDT 24 |
Finished | Jul 03 04:34:50 PM PDT 24 |
Peak memory | 369384 kb |
Host | smart-f14f23ba-3b1c-46ec-b6c2-ec83dc2d23ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106406895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2106406895 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3352083521 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 17776596038 ps |
CPU time | 393.15 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:39:51 PM PDT 24 |
Peak memory | 373968 kb |
Host | smart-83d4f8d8-1d1f-43a7-8f5a-93f3899dcb06 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352083521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3352083521 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.570323342 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 17388085 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:32:51 PM PDT 24 |
Finished | Jul 03 04:32:52 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-17737a17-9f81-45b0-85c2-39894a2b29c5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570323342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.570323342 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.3898334607 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 23645146632 ps |
CPU time | 70.42 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-23febd4b-7cdb-4e36-80c8-fab4ab7bf432 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898334607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3898334607 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.3210947084 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 57939915027 ps |
CPU time | 956.16 seconds |
Started | Jul 03 04:32:18 PM PDT 24 |
Finished | Jul 03 04:48:15 PM PDT 24 |
Peak memory | 366968 kb |
Host | smart-9d023602-8e2b-499f-910b-ecb570938064 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210947084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.3210947084 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.3764553274 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2606938730 ps |
CPU time | 7.61 seconds |
Started | Jul 03 04:32:52 PM PDT 24 |
Finished | Jul 03 04:33:00 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-da3ffacc-c68a-4cd7-83da-2111efb1da33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764553274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.3764553274 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.400681272 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 761836822 ps |
CPU time | 135.04 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:34:52 PM PDT 24 |
Peak memory | 370416 kb |
Host | smart-e25d5fe5-e189-4d5d-b12e-bfc49a7a82f5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400681272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.400681272 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3510237152 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 89133023 ps |
CPU time | 2.92 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:32:41 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-7f26b7a4-8498-4f0b-b037-450df067b0ae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510237152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3510237152 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.106930890 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 134689422 ps |
CPU time | 8.59 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:32:42 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-3f4c13fb-a746-48d3-af9a-19a2b4e05e65 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106930890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _mem_walk.106930890 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.65947901 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 3684998734 ps |
CPU time | 1383.66 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:55:34 PM PDT 24 |
Peak memory | 373528 kb |
Host | smart-b6023ef7-4a8a-49e8-aac9-608cad4eeabd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65947901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multipl e_keys.65947901 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.843872750 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 462371133 ps |
CPU time | 11.34 seconds |
Started | Jul 03 04:32:59 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 241004 kb |
Host | smart-02f56d23-cd32-4c72-b5db-419d45b4cf04 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843872750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s ram_ctrl_partial_access.843872750 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2175957923 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 10276159881 ps |
CPU time | 377.63 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:38:38 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-379901b0-c907-4a6c-a7cb-90bc26cc0a0e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175957923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2175957923 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.3804046591 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 41864324 ps |
CPU time | 0.73 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:32:32 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-a5b46239-a33c-497a-9ceb-74cb38e9a325 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804046591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3804046591 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.4154623904 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 19369097083 ps |
CPU time | 607.85 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:42:38 PM PDT 24 |
Peak memory | 375480 kb |
Host | smart-56e05be4-a6da-4e20-98ab-3e0257dd1b76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154623904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4154623904 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.2367697757 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 576131681 ps |
CPU time | 8.04 seconds |
Started | Jul 03 04:32:34 PM PDT 24 |
Finished | Jul 03 04:32:42 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-eb669fad-8ebf-4967-b466-812b74665b87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367697757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2367697757 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.3171475164 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 90225947436 ps |
CPU time | 2403.62 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 05:12:34 PM PDT 24 |
Peak memory | 374668 kb |
Host | smart-edd4f86c-f47d-4812-9809-e4060c5dc7b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171475164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.3171475164 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.200568552 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 1341497688 ps |
CPU time | 37.03 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:33:34 PM PDT 24 |
Peak memory | 212432 kb |
Host | smart-0898bdff-bce2-42fa-aad8-292aa7d7e40c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=200568552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.200568552 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3653489857 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 3151097430 ps |
CPU time | 290.36 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:37:19 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-097fae98-ba9f-46f2-84c7-60ad4e3be136 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653489857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.3653489857 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3709287263 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 608324845 ps |
CPU time | 149.56 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:34:59 PM PDT 24 |
Peak memory | 370372 kb |
Host | smart-a4654c07-dc23-4e13-853b-034ee7d9411d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709287263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3709287263 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1243911475 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 8343673576 ps |
CPU time | 1786.24 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 05:02:20 PM PDT 24 |
Peak memory | 374704 kb |
Host | smart-31d1068d-cb4a-4c74-a768-4c3579f16996 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243911475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.1243911475 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.1211624131 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 35038195 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:32:31 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-88495ed6-6dd7-4b3f-9d8f-078fc26c0f8e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211624131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1211624131 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.977826183 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 10328634053 ps |
CPU time | 51.77 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:33:56 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-82b2ca69-57ea-47ca-9515-714ee34d7402 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977826183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection. 977826183 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.3498520233 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 10515474365 ps |
CPU time | 168.69 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:35:20 PM PDT 24 |
Peak memory | 253696 kb |
Host | smart-1dd1e435-0abf-4cf3-9a7b-84b3df861d3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498520233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.3498520233 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.1542927624 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 2180629726 ps |
CPU time | 3.87 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:31 PM PDT 24 |
Peak memory | 214312 kb |
Host | smart-9f1c09f7-3fb6-4b4f-81e2-44ffeb2f6f33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542927624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1542927624 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.3647155273 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 182113116 ps |
CPU time | 17.45 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:33:00 PM PDT 24 |
Peak memory | 267848 kb |
Host | smart-798d7686-6e83-4ba2-9655-a7019c1499c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647155273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3647155273 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.874645234 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 374931164 ps |
CPU time | 5.08 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:32:42 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-dc350cf8-c4db-431b-b3f3-7113eb04aa9a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874645234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_mem_partial_access.874645234 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.4271963357 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 259696611 ps |
CPU time | 5.7 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:33:04 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-104be8de-c8a1-4f40-a22a-4c7db39cdcf2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271963357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.4271963357 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.3605886364 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 263128452219 ps |
CPU time | 1768.18 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 05:01:59 PM PDT 24 |
Peak memory | 375692 kb |
Host | smart-1dd30519-a93d-42fd-bc9f-b7c9e8502d69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605886364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3605886364 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.2682066182 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 637982250 ps |
CPU time | 127.26 seconds |
Started | Jul 03 04:32:54 PM PDT 24 |
Finished | Jul 03 04:35:02 PM PDT 24 |
Peak memory | 357024 kb |
Host | smart-13f44edf-99f7-421d-bedf-bc77810947c7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682066182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2682066182 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3354431210 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 86254702927 ps |
CPU time | 582.97 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:42:15 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-460dd734-f931-490d-9e2d-bde72d5f2d9d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354431210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3354431210 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.816179405 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 30445967733 ps |
CPU time | 662.57 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:43:29 PM PDT 24 |
Peak memory | 374652 kb |
Host | smart-9ca90f21-2031-4304-95b3-4e7c1d91dd2c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816179405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.816179405 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.908132437 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 3086433781 ps |
CPU time | 150.39 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:35:03 PM PDT 24 |
Peak memory | 366888 kb |
Host | smart-e8d56a3f-f6f9-44df-be67-3e27a8e042be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908132437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.908132437 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.3249978837 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 17261423819 ps |
CPU time | 6953.54 seconds |
Started | Jul 03 04:32:51 PM PDT 24 |
Finished | Jul 03 06:28:46 PM PDT 24 |
Peak memory | 383448 kb |
Host | smart-3c1f3feb-d34c-4fb9-b24a-14ed04795e6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249978837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.3249978837 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4246095129 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 801462209 ps |
CPU time | 93.71 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:34:21 PM PDT 24 |
Peak memory | 331924 kb |
Host | smart-499d65b7-d559-469d-b689-200affc39ed9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4246095129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.4246095129 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.529498528 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 7852350742 ps |
CPU time | 164.53 seconds |
Started | Jul 03 04:32:34 PM PDT 24 |
Finished | Jul 03 04:35:19 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-d719cf43-7572-485b-858a-71c0368498a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529498528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_stress_pipeline.529498528 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2010655468 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 143068607 ps |
CPU time | 106.45 seconds |
Started | Jul 03 04:32:34 PM PDT 24 |
Finished | Jul 03 04:34:21 PM PDT 24 |
Peak memory | 353896 kb |
Host | smart-dcd9e87b-1843-41a5-a4d2-1cedf84c3b20 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010655468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2010655468 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3714852673 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 3454634457 ps |
CPU time | 863.34 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:46:55 PM PDT 24 |
Peak memory | 374708 kb |
Host | smart-2eaa225b-1dc3-4b9b-87d7-db33fcc1bcc9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714852673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.3714852673 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.4124391689 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 58353408 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:32:34 PM PDT 24 |
Finished | Jul 03 04:32:35 PM PDT 24 |
Peak memory | 202576 kb |
Host | smart-56859ba5-a661-45b8-8856-c69dd767198a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124391689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.4124391689 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.2478493168 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 13985055036 ps |
CPU time | 59.92 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:33:33 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-f57e1ed4-aeaa-4b14-bd74-8e082da76bea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478493168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .2478493168 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.1202190568 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 6715408822 ps |
CPU time | 188.07 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:36:10 PM PDT 24 |
Peak memory | 341000 kb |
Host | smart-538052c9-10b3-4e2b-93d2-2d366839c90a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202190568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1202190568 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.1780230276 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 1888162579 ps |
CPU time | 5.74 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:32:38 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-acd82b73-3df3-4207-9bb3-21cce9f3edfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780230276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.1780230276 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.753445420 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 1066082660 ps |
CPU time | 144.07 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:35:07 PM PDT 24 |
Peak memory | 368664 kb |
Host | smart-951f95d6-87e0-43d2-95f5-aac6c2dd24c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753445420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.sram_ctrl_max_throughput.753445420 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2388853825 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 104915430 ps |
CPU time | 2.49 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:32:48 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-d6f7aaa1-003a-4ba5-a69e-2614eb666039 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388853825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2388853825 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.1594493704 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 443737929 ps |
CPU time | 9.95 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:32:58 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-ee99322d-05ad-45cf-98df-26439d920e0a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594493704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.1594493704 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.3540613503 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 5988168440 ps |
CPU time | 1296.3 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:54:07 PM PDT 24 |
Peak memory | 375712 kb |
Host | smart-97539a12-232e-42f9-8031-c0e11280f275 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540613503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.3540613503 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.3547817756 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 628211635 ps |
CPU time | 17.04 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:32:49 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-3d2c7f1b-66c3-4ff1-8636-ba0b235c35f6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547817756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3547817756 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1692253171 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 49620855720 ps |
CPU time | 306.87 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:37:40 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-380eff98-c388-45d3-86ac-df30846e52a1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692253171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.1692253171 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.2552956186 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 57819613 ps |
CPU time | 0.73 seconds |
Started | Jul 03 04:32:53 PM PDT 24 |
Finished | Jul 03 04:32:54 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-bb119429-ec58-4c6d-a9ef-7b340176da22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552956186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2552956186 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3518980326 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 46080222593 ps |
CPU time | 1113.87 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:51:37 PM PDT 24 |
Peak memory | 368308 kb |
Host | smart-91bc211d-3705-4073-bf8e-8525d8449aac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518980326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3518980326 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.1783730667 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 233448666 ps |
CPU time | 15.12 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:32:50 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-bf2396ae-86e4-40fa-9691-b7b74071696e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783730667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1783730667 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1671465395 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 1323303395 ps |
CPU time | 375.9 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:39:01 PM PDT 24 |
Peak memory | 373600 kb |
Host | smart-44d4abfb-dc67-4751-b6fe-9c91b87cf9ba |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1671465395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1671465395 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2572943319 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 1386401127 ps |
CPU time | 138.46 seconds |
Started | Jul 03 04:33:04 PM PDT 24 |
Finished | Jul 03 04:35:23 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-223518db-a30d-4d89-994a-a8b3c97ad9ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572943319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2572943319 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2781573875 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 548630969 ps |
CPU time | 113.04 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:34:28 PM PDT 24 |
Peak memory | 369184 kb |
Host | smart-8adbf4b8-a873-4a00-b615-78bedced2542 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781573875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2781573875 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1732880191 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 7444562479 ps |
CPU time | 1598.86 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:59:43 PM PDT 24 |
Peak memory | 372644 kb |
Host | smart-c8e24ee9-a0e0-48c2-9bbc-9871ebba99e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732880191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.1732880191 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.1589477739 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 29987798 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:31 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-bcb2f6ca-3ca1-4f1f-aa73-fa215e4fa173 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589477739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1589477739 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.3154250486 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 61506829307 ps |
CPU time | 82.9 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:34:06 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-efabb998-cf8c-470d-ba25-00d5597a1f67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154250486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .3154250486 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.918889154 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 45565087667 ps |
CPU time | 879.44 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:47:09 PM PDT 24 |
Peak memory | 374612 kb |
Host | smart-798517ca-ce7e-4a1c-85d4-9daf707b34b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918889154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl e.918889154 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.740960869 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 511417634 ps |
CPU time | 4.06 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:32:48 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-b71e5726-daa3-4d0a-9ec9-f2554691b55a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740960869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc alation.740960869 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.3182753565 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 542847758 ps |
CPU time | 147.81 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:35:26 PM PDT 24 |
Peak memory | 370380 kb |
Host | smart-144ace81-46b7-4a2a-b914-1c294741fa5a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182753565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.3182753565 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4280027817 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 104033500 ps |
CPU time | 3.17 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:32:47 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-f3a441d3-d51d-42d3-b099-c36273367ad9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280027817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.4280027817 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.4037036751 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 2717055366 ps |
CPU time | 11.96 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:32:44 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-d14b1080-61f2-4e5d-884e-ccf588572771 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037036751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.4037036751 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3006106779 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 17801972266 ps |
CPU time | 1288.85 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:54:00 PM PDT 24 |
Peak memory | 375592 kb |
Host | smart-e2ad2393-0235-4735-bca9-61130a152e9b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006106779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3006106779 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.3590050614 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 4461257773 ps |
CPU time | 17.04 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:32:59 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-7c1a6ad2-ac27-462c-99a7-1c7efcc01d86 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590050614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.3590050614 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3062970526 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 150395777312 ps |
CPU time | 410.5 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:39:19 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-5b3a2fed-2018-44d8-a3bd-42ac75e1e0cd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062970526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.3062970526 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.3241024797 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 36652434 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-49fe1703-23b3-4071-8029-feae20a68439 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241024797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3241024797 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.1287773621 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 2571421424 ps |
CPU time | 856.17 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:46:43 PM PDT 24 |
Peak memory | 370632 kb |
Host | smart-80e420a6-bd5e-46c9-8ba2-69b0dbc3f14d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287773621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1287773621 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.186000712 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 1129014056 ps |
CPU time | 11.82 seconds |
Started | Jul 03 04:32:38 PM PDT 24 |
Finished | Jul 03 04:32:50 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-db232ae0-7b1b-41ec-bd71-0ea4cefc6197 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186000712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.186000712 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.1806507764 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 22594226734 ps |
CPU time | 1126.36 seconds |
Started | Jul 03 04:32:40 PM PDT 24 |
Finished | Jul 03 04:51:28 PM PDT 24 |
Peak memory | 374676 kb |
Host | smart-7edd64e6-7db0-4016-a02a-87f29cdbdb20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806507764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.1806507764 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2067688095 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 4053179664 ps |
CPU time | 209.72 seconds |
Started | Jul 03 04:32:40 PM PDT 24 |
Finished | Jul 03 04:36:10 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-64200e46-6ed9-4637-b647-f09d175f24d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067688095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2067688095 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3321685251 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 114453407 ps |
CPU time | 38.84 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:33:11 PM PDT 24 |
Peak memory | 303968 kb |
Host | smart-e8284493-b8cf-4fb8-bd67-b902b627995e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321685251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3321685251 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3953337114 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 5775576058 ps |
CPU time | 722.85 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:44:48 PM PDT 24 |
Peak memory | 374688 kb |
Host | smart-2fe37395-0b0c-4561-a9fc-d93bc95a4326 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953337114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.3953337114 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.2188285342 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 26857291 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:32:43 PM PDT 24 |
Peak memory | 202232 kb |
Host | smart-4fc00f64-c469-483e-88a5-28da808d1938 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188285342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2188285342 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.74379639 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 1095557884 ps |
CPU time | 70.58 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:34:11 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-eefd4ef0-e00c-476e-b165-c711df64430d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74379639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.74379639 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.3591793924 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 38607742563 ps |
CPU time | 1301.33 seconds |
Started | Jul 03 04:32:38 PM PDT 24 |
Finished | Jul 03 04:54:20 PM PDT 24 |
Peak memory | 363444 kb |
Host | smart-c9ce5e5f-094f-45b4-8d9b-00d443f823da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591793924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.3591793924 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.2703075888 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 673758465 ps |
CPU time | 6.48 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:32:48 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-bcf25a15-967d-43d6-b2e5-11c41cc18fb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703075888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2703075888 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1751694565 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 649816258 ps |
CPU time | 73.41 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:33:56 PM PDT 24 |
Peak memory | 344880 kb |
Host | smart-6356fdb7-1415-47a2-859d-3c82474f4501 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751694565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1751694565 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2625059523 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 344811301 ps |
CPU time | 5.54 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:32:50 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-7ed25057-1a5d-418c-a6a0-a4fcde6902a1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625059523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2625059523 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.3414449724 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1327957131 ps |
CPU time | 10.93 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:32:49 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-709c1846-582b-4b93-a2c2-4d596f4af2ac |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414449724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3414449724 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.2880333086 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 6553691984 ps |
CPU time | 690.04 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:44:05 PM PDT 24 |
Peak memory | 374332 kb |
Host | smart-6f4f7971-0b44-4e29-9e76-b15993a791d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880333086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2880333086 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.1528955015 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 8790966003 ps |
CPU time | 19.47 seconds |
Started | Jul 03 04:32:39 PM PDT 24 |
Finished | Jul 03 04:32:59 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-e35a33df-2bec-4d55-906e-0964fcf1204c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528955015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.1528955015 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2255488485 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 8752573949 ps |
CPU time | 233.27 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:36:23 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-a49f1fdd-2030-42a2-92c3-4c9806bcb77b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255488485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2255488485 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.2482136414 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 29561785 ps |
CPU time | 0.79 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:32:34 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-12f6c98c-2a42-4be0-ac92-23a57d318a2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482136414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2482136414 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.3897473464 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 13283690462 ps |
CPU time | 1450.89 seconds |
Started | Jul 03 04:32:49 PM PDT 24 |
Finished | Jul 03 04:57:00 PM PDT 24 |
Peak memory | 374700 kb |
Host | smart-7d12e353-2ed8-46ba-91b5-4be3b5543c95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897473464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3897473464 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.2745025608 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 4241755698 ps |
CPU time | 63.23 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:33:46 PM PDT 24 |
Peak memory | 309620 kb |
Host | smart-13697907-f6b7-457e-989b-b8244f899895 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745025608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2745025608 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.49929351 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 50231500729 ps |
CPU time | 2920.27 seconds |
Started | Jul 03 04:32:40 PM PDT 24 |
Finished | Jul 03 05:21:21 PM PDT 24 |
Peak memory | 375416 kb |
Host | smart-7fed1b2d-2a7e-4ae1-b749-2d5ce330633a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49929351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_stress_all.49929351 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2013890420 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 4391752790 ps |
CPU time | 253.02 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:36:45 PM PDT 24 |
Peak memory | 361564 kb |
Host | smart-e1617e27-4804-4150-bebc-e7d99afefdd4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2013890420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2013890420 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.4078409726 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 2812400757 ps |
CPU time | 280.08 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:37:17 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-a058b684-7fb8-4e7a-97bf-92904b2f3e43 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078409726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.4078409726 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2014382962 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 151375025 ps |
CPU time | 102.3 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:34:59 PM PDT 24 |
Peak memory | 369420 kb |
Host | smart-0f7e939b-3cc4-4ae2-bf91-015e1aab784e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014382962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2014382962 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.251628491 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 13121389151 ps |
CPU time | 748.23 seconds |
Started | Jul 03 04:32:52 PM PDT 24 |
Finished | Jul 03 04:45:21 PM PDT 24 |
Peak memory | 365464 kb |
Host | smart-6b56a893-ef53-46e1-86e2-eac42c78c663 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251628491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.251628491 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.3406200587 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 40758126 ps |
CPU time | 0.71 seconds |
Started | Jul 03 04:32:39 PM PDT 24 |
Finished | Jul 03 04:32:40 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-878a61e4-2093-473c-a6a4-0d0b09960cf2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406200587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3406200587 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.3238802470 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 660091862 ps |
CPU time | 23.63 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:33:11 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-4f96dc29-3d27-49c8-b274-860b502eb912 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238802470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3238802470 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.645531324 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 53001378113 ps |
CPU time | 979.38 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:49:11 PM PDT 24 |
Peak memory | 374360 kb |
Host | smart-dccca7ea-14eb-473b-8e5b-0b07cb88b1a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645531324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executabl e.645531324 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.2407162885 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 1451698020 ps |
CPU time | 4.91 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:35 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-b304cffc-99ec-4ff1-8aa2-76f162d34fef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407162885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2407162885 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.2874404202 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 347911317 ps |
CPU time | 21.3 seconds |
Started | Jul 03 04:33:14 PM PDT 24 |
Finished | Jul 03 04:33:37 PM PDT 24 |
Peak memory | 279780 kb |
Host | smart-613c2de2-f27e-480c-b6d9-7d1e47c37523 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874404202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.2874404202 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1664702155 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 202063740 ps |
CPU time | 3.36 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-834fa7d8-8898-47d9-815c-70f5e8f921c3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664702155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1664702155 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.2645062239 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 358019948 ps |
CPU time | 9.76 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:32:42 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-e518aeee-eca7-4e9a-88e8-c1a4c59d7b0a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645062239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.2645062239 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.103487384 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 2788552352 ps |
CPU time | 842.34 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:46:38 PM PDT 24 |
Peak memory | 374320 kb |
Host | smart-e9c3f794-5d80-4f35-b266-2bbd27ff6531 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103487384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip le_keys.103487384 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.4104113029 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 206986365 ps |
CPU time | 119.4 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:35:16 PM PDT 24 |
Peak memory | 355016 kb |
Host | smart-ffe10b94-15d3-45e8-bc4b-de10d393ef12 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104113029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.4104113029 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3316116497 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 98831536714 ps |
CPU time | 390.96 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:39:07 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-6563fff4-8a7e-47c7-ae4e-1575128bfa9a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316116497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.3316116497 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.3781384213 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 44356023 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:32:38 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-f58b5e47-6d44-4156-9954-e8ac18cf3899 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781384213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3781384213 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.536224142 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 4385822617 ps |
CPU time | 426.93 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:39:49 PM PDT 24 |
Peak memory | 342968 kb |
Host | smart-f1ca0da9-4fae-41cd-97bc-5c62acd38deb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536224142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.536224142 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.3616956478 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 64210809 ps |
CPU time | 1.05 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:32:47 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-d673dad6-e28b-4627-bfd3-1197c62485c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616956478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3616956478 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.2911697957 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 30886837361 ps |
CPU time | 2315.41 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 05:11:33 PM PDT 24 |
Peak memory | 375776 kb |
Host | smart-94e66a60-50d4-4f13-afa5-f188c0c884a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911697957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.2911697957 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1319048424 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 839175430 ps |
CPU time | 63.88 seconds |
Started | Jul 03 04:32:38 PM PDT 24 |
Finished | Jul 03 04:33:42 PM PDT 24 |
Peak memory | 305268 kb |
Host | smart-fbcd7f7c-beed-4cef-9a3f-0552d90c78d1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1319048424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1319048424 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1806481843 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 3393931226 ps |
CPU time | 333.43 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:38:21 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-63fe6553-9537-4c7a-9770-89ddbe05a181 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806481843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.1806481843 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1916833816 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 113507687 ps |
CPU time | 7.14 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:38 PM PDT 24 |
Peak memory | 235476 kb |
Host | smart-e6c64cac-da2a-4ef7-b1b9-1d51224ea868 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916833816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1916833816 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2692612937 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 4351123480 ps |
CPU time | 1224.72 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:53:01 PM PDT 24 |
Peak memory | 372388 kb |
Host | smart-a4b73218-c963-4c64-92ea-a1f3a67d75f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692612937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.2692612937 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.4258913799 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 33898980 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:32:49 PM PDT 24 |
Finished | Jul 03 04:32:50 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-64543d3d-dc37-4f35-a9ab-889beb417fd8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258913799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.4258913799 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.2361432352 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 3165860584 ps |
CPU time | 52.7 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:34:10 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-389300e5-23a8-44ee-9c25-140c4152e24b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361432352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2361432352 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.657093221 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 12619015360 ps |
CPU time | 1184.58 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:52:30 PM PDT 24 |
Peak memory | 371208 kb |
Host | smart-e075f9f7-9bec-4842-b29f-f88d7919be47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657093221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.657093221 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.1027245750 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1198236235 ps |
CPU time | 3.21 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-7e2d0c3a-edb0-4cce-98e6-9a14a2252d5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027245750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.1027245750 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1954449889 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 519653264 ps |
CPU time | 113.2 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:34:23 PM PDT 24 |
Peak memory | 370280 kb |
Host | smart-4ecd6c4a-735c-4a85-a5ba-ad2fc7315da0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954449889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1954449889 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3971088118 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 914305915 ps |
CPU time | 5.36 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:31 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-3d50b2f4-a3d1-4cd8-b97e-6ecba900dbff |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971088118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3971088118 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3719546255 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 186272314 ps |
CPU time | 9.83 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:33:34 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-04c4df83-db3a-4e0c-b2da-0a12a0afdbc4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719546255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3719546255 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.2731872206 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 61906174931 ps |
CPU time | 1399.53 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:56:37 PM PDT 24 |
Peak memory | 375752 kb |
Host | smart-3a0a6e67-1adf-41a5-9d79-be64e140dd06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731872206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.2731872206 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.212074445 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 164611496 ps |
CPU time | 69.17 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:34:22 PM PDT 24 |
Peak memory | 324832 kb |
Host | smart-c6c3f47d-5d8e-49ef-b99c-381ec7913b6a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212074445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.s ram_ctrl_partial_access.212074445 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2375672604 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 8824413192 ps |
CPU time | 335.39 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:38:06 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-ef821297-1e70-4122-953b-18941ddfca13 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375672604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.2375672604 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.4214209189 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 83701833 ps |
CPU time | 0.74 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:32:30 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-1ae4136e-11bc-4547-906a-cea84268033e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214209189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.4214209189 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.1007215635 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 2749882382 ps |
CPU time | 882.11 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:47:25 PM PDT 24 |
Peak memory | 369616 kb |
Host | smart-910cbd2a-4e6e-4407-99aa-fdf710b8cb42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007215635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1007215635 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.1026306654 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 1130309754 ps |
CPU time | 14.4 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:32:47 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-eedbc9e6-c6c0-4205-b59a-bce4e15f5509 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026306654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1026306654 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.2681095744 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 68507361786 ps |
CPU time | 1897.23 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 05:04:22 PM PDT 24 |
Peak memory | 382868 kb |
Host | smart-758c16f8-2859-44a0-9a3d-24e1a33cdfc5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681095744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2681095744 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3602338823 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 320351880 ps |
CPU time | 11.08 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:32:58 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-6339b369-e97a-4f40-9822-7232932601e8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3602338823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3602338823 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1433933728 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 10787033792 ps |
CPU time | 264.86 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:37:03 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-9745151a-6207-4306-8504-4727c655dece |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433933728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.1433933728 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3979434575 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 541784971 ps |
CPU time | 74.31 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:33:57 PM PDT 24 |
Peak memory | 324356 kb |
Host | smart-122ff9c7-578d-43e4-9b90-f4ff6ac0edcc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979434575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3979434575 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.369162408 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 3494702136 ps |
CPU time | 64.04 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:33:42 PM PDT 24 |
Peak memory | 292196 kb |
Host | smart-a8925fa0-da3b-42a1-998e-7f9616bb1c67 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369162408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_access_during_key_req.369162408 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.3629644457 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 22880857 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:32:53 PM PDT 24 |
Finished | Jul 03 04:32:54 PM PDT 24 |
Peak memory | 202504 kb |
Host | smart-070d3bf5-8be5-48e8-8450-77e41aec9b4b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629644457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3629644457 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.1885952414 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 806185600 ps |
CPU time | 44.91 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:33:32 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-8ca19d84-9855-4bfb-9175-1228a8256f7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885952414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .1885952414 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.2990745268 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 55053677141 ps |
CPU time | 816.87 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:46:20 PM PDT 24 |
Peak memory | 358756 kb |
Host | smart-bf654d5d-6ba7-4854-8c53-0bd059236c13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990745268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2990745268 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.457140244 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1902481942 ps |
CPU time | 7.28 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:32:52 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-2e4325eb-1b98-46f6-9370-0a1da5a00975 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457140244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc alation.457140244 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.2751378622 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 120516241 ps |
CPU time | 68.71 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:33:38 PM PDT 24 |
Peak memory | 340608 kb |
Host | smart-04132a07-3cba-4c7f-8518-fe5f86c9242d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751378622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.2751378622 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.3223644810 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 66786903 ps |
CPU time | 4.7 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:33:13 PM PDT 24 |
Peak memory | 210916 kb |
Host | smart-e1b14ef9-150a-4066-8f41-c5b8bbb232ad |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223644810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.3223644810 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.4151210426 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 2423116254 ps |
CPU time | 11.02 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:32:47 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-3a8a5cfd-daab-4beb-9356-3f54efa4fb5b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151210426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.4151210426 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.1680230233 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 22915429508 ps |
CPU time | 1426.6 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:56:29 PM PDT 24 |
Peak memory | 375696 kb |
Host | smart-22fcfff8-758b-4c80-a327-63bc427c61de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680230233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.1680230233 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.4233341473 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 760560257 ps |
CPU time | 38.96 seconds |
Started | Jul 03 04:32:38 PM PDT 24 |
Finished | Jul 03 04:33:17 PM PDT 24 |
Peak memory | 292704 kb |
Host | smart-b4fb4ffe-40e3-4163-a9f3-f40fe82872b0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233341473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.4233341473 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.905642339 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 7635031481 ps |
CPU time | 261.79 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:37:06 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-24d45479-e31f-4217-8468-c182c38eccbd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905642339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.sram_ctrl_partial_access_b2b.905642339 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.2564492139 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 49875591 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:32:49 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-30f00abd-d4ce-4c61-8d98-316d4dd49c7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564492139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2564492139 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.3611722607 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 9492232356 ps |
CPU time | 1150.22 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:51:57 PM PDT 24 |
Peak memory | 372676 kb |
Host | smart-b7adaebd-6821-4522-b992-17983e5e45b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611722607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3611722607 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.520959028 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 433158336 ps |
CPU time | 22.15 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 275080 kb |
Host | smart-3fbb4a26-c6a2-4ddd-ac7c-34e8ec9c584b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520959028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.520959028 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.3732868820 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 44980822211 ps |
CPU time | 2681.56 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 05:17:46 PM PDT 24 |
Peak memory | 376588 kb |
Host | smart-1c6d44bb-2c97-47ab-86c8-bc9f4540e6ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732868820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.3732868820 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3451932112 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 930280122 ps |
CPU time | 183.7 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:35:47 PM PDT 24 |
Peak memory | 365024 kb |
Host | smart-cfaa4f8d-e66f-4329-8380-03bf413e426c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3451932112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3451932112 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.957756657 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 20179646113 ps |
CPU time | 256.12 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:36:53 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-08fd8ce9-7aee-499f-bc7f-eb4dc9469de0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957756657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_stress_pipeline.957756657 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3307040508 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 2406827083 ps |
CPU time | 111.16 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:34:35 PM PDT 24 |
Peak memory | 368700 kb |
Host | smart-c3dc9237-388d-4422-94aa-e66428d4b8bb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307040508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3307040508 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1527042915 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 4518442477 ps |
CPU time | 363.49 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:39:06 PM PDT 24 |
Peak memory | 373648 kb |
Host | smart-9dcd6c6c-0e83-43c7-9213-69e2dbc875d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527042915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.1527042915 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3055338289 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 38897648 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-1dae9054-eeb3-4202-a2df-7a59b48e5b09 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055338289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3055338289 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.46547864 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 24271401139 ps |
CPU time | 63.61 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:33:46 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-4b4b2df8-365d-4e1c-ae1b-0109dd97a03e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46547864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.46547864 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.2742711396 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 2244118834 ps |
CPU time | 7.12 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:32:49 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-7603b5c2-66ca-4caa-8ffc-40287b3a7699 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742711396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.2742711396 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.3396288130 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 79327081 ps |
CPU time | 13.04 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:32:57 PM PDT 24 |
Peak memory | 252964 kb |
Host | smart-aac61633-f9f5-49e5-80f2-7099f559373f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396288130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.3396288130 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1496076700 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 177885885 ps |
CPU time | 6.07 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:32:52 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-56fedc99-3efe-45c6-a1b3-9f08e5a45054 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496076700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.1496076700 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.699333503 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 1399202429 ps |
CPU time | 12 seconds |
Started | Jul 03 04:32:50 PM PDT 24 |
Finished | Jul 03 04:33:02 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-bc6aa58d-b206-4990-a68b-7b76b04b0d7a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699333503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _mem_walk.699333503 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.3983885154 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 32000812767 ps |
CPU time | 1017.1 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:49:45 PM PDT 24 |
Peak memory | 375760 kb |
Host | smart-1762b3d9-f640-4ae5-a902-d42aee0fcdcb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983885154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.3983885154 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.2046900366 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 118660152 ps |
CPU time | 2.54 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:32:50 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-bfc7a3f1-4b23-4eed-8040-e0477f4aa135 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046900366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.2046900366 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.859199798 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 104355811373 ps |
CPU time | 628.03 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:43:11 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-19961f3c-ff4e-449f-8a8c-31bcbcab1e58 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859199798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.sram_ctrl_partial_access_b2b.859199798 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.421038815 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 29501031 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:50 PM PDT 24 |
Finished | Jul 03 04:32:51 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-d610128a-f791-49fc-9a50-ec8a118b7976 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421038815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.421038815 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.1583106098 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 7176652522 ps |
CPU time | 661.37 seconds |
Started | Jul 03 04:32:40 PM PDT 24 |
Finished | Jul 03 04:43:42 PM PDT 24 |
Peak memory | 373096 kb |
Host | smart-85d9d4ab-a73e-4a5e-a7a7-64f64fb1d87c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583106098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1583106098 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.1221313344 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 863274786 ps |
CPU time | 31.93 seconds |
Started | Jul 03 04:32:34 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 302972 kb |
Host | smart-d2148c3b-44e3-430c-a995-76663955cf4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221313344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1221313344 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.2104195339 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 58184683299 ps |
CPU time | 1124.96 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:51:47 PM PDT 24 |
Peak memory | 374696 kb |
Host | smart-06d90fa2-79aa-484f-a253-8d8a5f07da58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104195339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.2104195339 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1485056536 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 3937401440 ps |
CPU time | 87.27 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:34:28 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-c9b5bbe7-cc32-4268-91ca-147dd1b63d0e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485056536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1485056536 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.516281003 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 45521435 ps |
CPU time | 2.21 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:32:48 PM PDT 24 |
Peak memory | 216560 kb |
Host | smart-00b821fc-a9b9-4313-9c32-5a75ef0a985f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516281003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.516281003 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1845676740 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 805780672 ps |
CPU time | 399.22 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 04:38:49 PM PDT 24 |
Peak memory | 365228 kb |
Host | smart-21b2cb97-1478-4a56-927c-bb7e8c4842f9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845676740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.1845676740 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.1353861682 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 40550493 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:28 PM PDT 24 |
Peak memory | 202392 kb |
Host | smart-00251cf3-f198-471a-9e04-8b99f1bd614c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353861682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1353861682 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.1595499104 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 12757408045 ps |
CPU time | 76.48 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-6a440959-4538-4b80-bb16-864d3732e4d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595499104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1595499104 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.2932458493 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 7479937378 ps |
CPU time | 980.1 seconds |
Started | Jul 03 04:32:18 PM PDT 24 |
Finished | Jul 03 04:48:38 PM PDT 24 |
Peak memory | 373916 kb |
Host | smart-acb0880d-5d2d-4a9a-a98d-236b23cd9042 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932458493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.2932458493 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.626101640 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 2842326901 ps |
CPU time | 5.64 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:32:20 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-efebf87f-07fd-4ff2-a681-46ae8d733ca4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626101640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca lation.626101640 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.3280337046 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 134618733 ps |
CPU time | 96.31 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:33:56 PM PDT 24 |
Peak memory | 358948 kb |
Host | smart-5e8fe385-d985-4db4-aa7c-52915270980c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280337046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3280337046 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.89979697 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 149305498 ps |
CPU time | 5.01 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:32:19 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-1cdae8cb-ec99-4361-8f4c-8bd948279535 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89979697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_mem_partial_access.89979697 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.3403861191 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 150364585 ps |
CPU time | 4.27 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:32:30 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-24b744c8-92cc-4b3e-b7e0-fcce4f73125e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403861191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.3403861191 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.2145382033 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 1793640180 ps |
CPU time | 624.86 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:42:53 PM PDT 24 |
Peak memory | 365168 kb |
Host | smart-33add27d-43dc-485f-bfe0-8bcaa5e4ac73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145382033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.2145382033 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.2361153257 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 788799545 ps |
CPU time | 15.16 seconds |
Started | Jul 03 04:32:12 PM PDT 24 |
Finished | Jul 03 04:32:27 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-0cc4ba40-1ae3-4581-8021-58f3cfa148b2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361153257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.2361153257 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4087970738 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 20556639049 ps |
CPU time | 552.71 seconds |
Started | Jul 03 04:32:08 PM PDT 24 |
Finished | Jul 03 04:41:22 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-2b8be708-49e0-451d-b997-c6b0c4fb248a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087970738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.4087970738 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3830439705 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 111662107 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:39 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-542ff38b-c9b1-4ca5-bd67-b4e2bc32cc52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830439705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3830439705 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.3787384895 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 103207689666 ps |
CPU time | 577.25 seconds |
Started | Jul 03 04:32:10 PM PDT 24 |
Finished | Jul 03 04:41:48 PM PDT 24 |
Peak memory | 367072 kb |
Host | smart-d335e976-8d20-43c2-926d-9b2a9e8b2b20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787384895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3787384895 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.750869798 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 828478175 ps |
CPU time | 3.33 seconds |
Started | Jul 03 04:32:12 PM PDT 24 |
Finished | Jul 03 04:32:16 PM PDT 24 |
Peak memory | 222060 kb |
Host | smart-93d23221-62fd-4a5f-8e2d-34402d4af551 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750869798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_sec_cm.750869798 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.3070156469 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 354042394 ps |
CPU time | 17.01 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:40 PM PDT 24 |
Peak memory | 274004 kb |
Host | smart-b780fcb9-9297-4e20-855e-46ece160bad4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070156469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3070156469 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.2319466825 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 154378478919 ps |
CPU time | 3239.04 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 05:26:28 PM PDT 24 |
Peak memory | 376776 kb |
Host | smart-52e8cf43-849c-467f-9095-d8811c8dd68e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319466825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2319466825 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2349474983 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 11612794991 ps |
CPU time | 305.34 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:37:31 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-9fef8bcb-9f56-40f9-b7d5-46a9cebeba6f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349474983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.2349474983 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3986198272 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 421653830 ps |
CPU time | 27.01 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 292988 kb |
Host | smart-2ad9f446-f255-4a41-9674-7f82a9472c72 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986198272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3986198272 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1966648220 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 8093728193 ps |
CPU time | 445.12 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:40:12 PM PDT 24 |
Peak memory | 336008 kb |
Host | smart-e66219bb-0d86-4e3d-88c0-0d22941fb108 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966648220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.1966648220 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.2261292937 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 31511467 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:33:04 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-561b1606-6a9d-43a2-80e8-b663bd8a1ab9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261292937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.2261292937 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.80272018 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 2778068749 ps |
CPU time | 41.71 seconds |
Started | Jul 03 04:32:48 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-ea870b7c-4bae-48a9-90dd-5a1f6fe40c8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80272018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.80272018 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.1496730513 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 6605198288 ps |
CPU time | 326.22 seconds |
Started | Jul 03 04:32:50 PM PDT 24 |
Finished | Jul 03 04:38:17 PM PDT 24 |
Peak memory | 374332 kb |
Host | smart-d470edff-6114-4b78-bcdc-547473afcbaf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496730513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.1496730513 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.3295248520 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 432533054 ps |
CPU time | 5.98 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:32:51 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-980aa4af-8e1b-4889-80a1-9f5e41004e36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295248520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.3295248520 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.3808017840 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 606857234 ps |
CPU time | 136.14 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:35:20 PM PDT 24 |
Peak memory | 369396 kb |
Host | smart-1682bd10-635d-46a2-9dbc-96244f3ef605 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808017840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.3808017840 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1618337850 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 216268173 ps |
CPU time | 4.84 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:32:43 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-3b33a6d1-9e63-4c21-99c2-0684224dcf34 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618337850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.1618337850 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.1085161056 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 139784290 ps |
CPU time | 8 seconds |
Started | Jul 03 04:32:43 PM PDT 24 |
Finished | Jul 03 04:32:52 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-fa76fe66-1c7b-4e95-adf7-9461af430ebe |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085161056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.1085161056 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.578194109 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 239029798 ps |
CPU time | 52.86 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:33:40 PM PDT 24 |
Peak memory | 313240 kb |
Host | smart-4c4e3cfb-9412-4d9e-aa2b-5bc07e167eff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578194109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.578194109 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.3632203988 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1907912929 ps |
CPU time | 9.94 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:33:11 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-08c81480-7598-4724-9968-4ee185fb3506 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632203988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3632203988 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1816810331 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 46869017258 ps |
CPU time | 659.94 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:43:48 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-a83b9f78-cc46-459a-8eb6-827ffab34096 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816810331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.1816810331 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3892667837 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 90468688 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:32:56 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-e05db663-5b0c-444d-884e-decadf0df959 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892667837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3892667837 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.1422293226 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 21067339607 ps |
CPU time | 424.25 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:40:10 PM PDT 24 |
Peak memory | 372660 kb |
Host | smart-d908f7a7-f261-4713-9b82-0c56002a45a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422293226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1422293226 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.812899349 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 1461481692 ps |
CPU time | 25.17 seconds |
Started | Jul 03 04:33:10 PM PDT 24 |
Finished | Jul 03 04:33:36 PM PDT 24 |
Peak memory | 289648 kb |
Host | smart-6dac9ec2-a3e4-478b-b6a6-2956e16f0e84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812899349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.812899349 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.951442852 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 146559999735 ps |
CPU time | 1410.06 seconds |
Started | Jul 03 04:32:40 PM PDT 24 |
Finished | Jul 03 04:56:11 PM PDT 24 |
Peak memory | 372388 kb |
Host | smart-926b9556-9182-4e69-abc0-339a5e518f0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951442852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.951442852 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1768938465 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 549010122 ps |
CPU time | 19.58 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:33:15 PM PDT 24 |
Peak memory | 212180 kb |
Host | smart-eaf3ac3e-9f20-473f-aec9-26eedb7f3b63 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1768938465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1768938465 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2028512061 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 18492633334 ps |
CPU time | 258.47 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:37:15 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-2d621038-faba-415b-97a9-fb3cdb369f7d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028512061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.2028512061 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1785833580 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 121554711 ps |
CPU time | 0.9 seconds |
Started | Jul 03 04:32:32 PM PDT 24 |
Finished | Jul 03 04:32:34 PM PDT 24 |
Peak memory | 202512 kb |
Host | smart-85ea84eb-4403-40b4-a478-ca2c2c21df9e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785833580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1785833580 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.802743955 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 4760235800 ps |
CPU time | 1595.86 seconds |
Started | Jul 03 04:32:52 PM PDT 24 |
Finished | Jul 03 04:59:29 PM PDT 24 |
Peak memory | 373684 kb |
Host | smart-6c440a50-dba8-4b36-bdd3-567a406037d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802743955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.802743955 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.2093397868 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 60916976 ps |
CPU time | 0.69 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:32:44 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-c7ab6123-d83a-416b-b528-ff12ff47cb55 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093397868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2093397868 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3126087576 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 4899880091 ps |
CPU time | 42.95 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:33:46 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-caaceac7-e636-4eea-9856-55caadf854bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126087576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3126087576 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.2164151443 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 2496053108 ps |
CPU time | 640.76 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:43:15 PM PDT 24 |
Peak memory | 367524 kb |
Host | smart-a7711501-7486-4201-85a8-9851aca93079 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164151443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.2164151443 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2912964421 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 4756758932 ps |
CPU time | 7.09 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:33:03 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-8e5e57d0-019c-4147-8dcf-e519171c5ba5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912964421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2912964421 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.693917513 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 265751812 ps |
CPU time | 129.77 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:34:57 PM PDT 24 |
Peak memory | 369416 kb |
Host | smart-8bf7427c-734a-4b07-ae94-af288a5d5043 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693917513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.sram_ctrl_max_throughput.693917513 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3001553578 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 375273828 ps |
CPU time | 5.59 seconds |
Started | Jul 03 04:32:48 PM PDT 24 |
Finished | Jul 03 04:32:54 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-2207008d-3cce-4532-96e2-4537a80cb774 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001553578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.3001553578 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.241466495 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 5986877393 ps |
CPU time | 11.79 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:32:57 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-590d8dd3-c46a-46ab-b46e-c326f9011f21 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241466495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.241466495 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.1776460509 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 28523740055 ps |
CPU time | 1878.7 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 05:04:20 PM PDT 24 |
Peak memory | 375704 kb |
Host | smart-b45714af-5647-4ccc-9256-1b2049844216 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776460509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.1776460509 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1485355828 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 261182385 ps |
CPU time | 128.23 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:35:05 PM PDT 24 |
Peak memory | 368008 kb |
Host | smart-c7ab11ae-4fb0-400e-a664-e320faaa793e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485355828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1485355828 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1309493602 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 63205135917 ps |
CPU time | 385.34 seconds |
Started | Jul 03 04:32:49 PM PDT 24 |
Finished | Jul 03 04:39:15 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-6203cb4e-f1d3-467c-901e-005350c5e966 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309493602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1309493602 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.94239180 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 30983756 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:32:44 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-5a15a736-47fe-4813-b8d6-e5b37dd3f854 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94239180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.94239180 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.2937594642 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 46456146348 ps |
CPU time | 671.15 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:44:17 PM PDT 24 |
Peak memory | 356656 kb |
Host | smart-b252c586-2245-4001-b9e2-c7c5c70cabbd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937594642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2937594642 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.1672746108 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 263539268 ps |
CPU time | 115.91 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:35:02 PM PDT 24 |
Peak memory | 366260 kb |
Host | smart-abc0684e-cd8b-4927-bd91-5481aec3ab9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672746108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1672746108 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.467800914 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 50447101401 ps |
CPU time | 1756.41 seconds |
Started | Jul 03 04:32:57 PM PDT 24 |
Finished | Jul 03 05:02:14 PM PDT 24 |
Peak memory | 376748 kb |
Host | smart-486a4014-f68c-452f-9e2d-7f502b2ea3ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467800914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_stress_all.467800914 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.4124807317 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 4955118008 ps |
CPU time | 24.08 seconds |
Started | Jul 03 04:32:54 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 212780 kb |
Host | smart-1ed0270b-5358-422e-9031-b2bd9a555671 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4124807317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.4124807317 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.973263546 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 1924107661 ps |
CPU time | 192.2 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:36:08 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-65db4696-2a76-457c-a8a3-8a2038201b3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973263546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_stress_pipeline.973263546 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.506653420 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 129533937 ps |
CPU time | 72.16 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:34:08 PM PDT 24 |
Peak memory | 338764 kb |
Host | smart-d3db08a5-386f-4f8e-bd6c-4cb9b744a086 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506653420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.506653420 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.857846518 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 3103622225 ps |
CPU time | 345.92 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:38:31 PM PDT 24 |
Peak memory | 337928 kb |
Host | smart-d9ed837d-4222-4525-bd9d-227f33a8dc72 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857846518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sram_ctrl_access_during_key_req.857846518 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.1627075020 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 16741912 ps |
CPU time | 0.68 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:33:06 PM PDT 24 |
Peak memory | 202564 kb |
Host | smart-d9834ec7-55fe-426e-a8e8-c77e34443f2c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627075020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1627075020 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.2321802256 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 812810735 ps |
CPU time | 49.93 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:33:46 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-cd4b39b8-64ae-443e-aa68-c521a61affa8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321802256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2321802256 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.504737097 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 1744470544 ps |
CPU time | 448.56 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:40:31 PM PDT 24 |
Peak memory | 373532 kb |
Host | smart-15e91672-0096-4dbf-bd66-0ad7ed1702b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504737097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl e.504737097 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.2866753607 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 1172077559 ps |
CPU time | 7.02 seconds |
Started | Jul 03 04:32:59 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-7f54a41e-58b7-471b-a81e-c16fb03f6aeb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866753607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.2866753607 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.3569785901 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 596622192 ps |
CPU time | 138.86 seconds |
Started | Jul 03 04:32:54 PM PDT 24 |
Finished | Jul 03 04:35:13 PM PDT 24 |
Peak memory | 369332 kb |
Host | smart-06a5060c-e408-4b74-bf77-96aea33042b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569785901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.3569785901 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3226008665 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 171537340 ps |
CPU time | 5.39 seconds |
Started | Jul 03 04:32:54 PM PDT 24 |
Finished | Jul 03 04:33:00 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-a8826af2-f148-4126-bb24-b8462cbfc7d1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226008665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3226008665 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.3967507910 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1380766802 ps |
CPU time | 6.23 seconds |
Started | Jul 03 04:32:48 PM PDT 24 |
Finished | Jul 03 04:32:55 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-2cd5242b-156f-488e-93c8-74bb630da366 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967507910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3967507910 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.924871297 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 5036391498 ps |
CPU time | 20.83 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:33:17 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-8e191fcf-be7b-4004-b407-fe4b50684c06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924871297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip le_keys.924871297 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.3675953005 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 72423031 ps |
CPU time | 2.88 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-27bc5adb-0e53-4dcc-a1d8-168bdf15ec2b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675953005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3675953005 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2783570617 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 8493323396 ps |
CPU time | 304.81 seconds |
Started | Jul 03 04:32:39 PM PDT 24 |
Finished | Jul 03 04:37:45 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-b7a7eef9-c94a-4205-a804-6e230db06855 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783570617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.2783570617 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.2636006312 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 47567051 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:32:56 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-f6ec5624-a29d-4af1-94cc-2641607e61b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636006312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2636006312 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.1993308300 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 2339473880 ps |
CPU time | 57.81 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 275808 kb |
Host | smart-fe5cf7f0-aa35-4bce-ab1c-62cdb0abb00c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993308300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1993308300 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.1642460388 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 611364810 ps |
CPU time | 6.52 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:32:53 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-df344dc1-cf59-48e1-be56-4e28ff552ff8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642460388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1642460388 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.1862010532 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 111808677981 ps |
CPU time | 2678.46 seconds |
Started | Jul 03 04:32:53 PM PDT 24 |
Finished | Jul 03 05:17:33 PM PDT 24 |
Peak memory | 382040 kb |
Host | smart-df1abaeb-1e03-4984-adbb-06c04863f692 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862010532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.1862010532 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.837401807 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 2557301578 ps |
CPU time | 221.64 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:36:23 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-9c49d67c-e46e-4af8-96f2-b53b9431f312 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837401807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.837401807 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2978109691 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 1313425860 ps |
CPU time | 13.65 seconds |
Started | Jul 03 04:32:51 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 251620 kb |
Host | smart-4673b48f-972e-48f3-a2e9-cec11049a645 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978109691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2978109691 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1777904028 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 3131492827 ps |
CPU time | 557.85 seconds |
Started | Jul 03 04:32:51 PM PDT 24 |
Finished | Jul 03 04:42:09 PM PDT 24 |
Peak memory | 366488 kb |
Host | smart-555e732a-da06-4ad0-bb23-479d1c1be5ad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777904028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1777904028 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.3055847098 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 13045279 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:33:17 PM PDT 24 |
Peak memory | 202576 kb |
Host | smart-5ab009c5-2d65-435d-9bb4-591b23160f37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055847098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3055847098 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.3582311406 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 1506843594 ps |
CPU time | 47.32 seconds |
Started | Jul 03 04:32:50 PM PDT 24 |
Finished | Jul 03 04:33:38 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-6a82b6e2-b226-494a-9008-4e90ddd65840 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582311406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3582311406 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.5429252 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 20180631404 ps |
CPU time | 1097.7 seconds |
Started | Jul 03 04:33:07 PM PDT 24 |
Finished | Jul 03 04:51:26 PM PDT 24 |
Peak memory | 361364 kb |
Host | smart-b0fec114-2c13-4440-9ae8-aa5a69e8fd2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5429252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.5429252 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.1690633706 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 863715508 ps |
CPU time | 9.73 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:33:08 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-9df7227c-005d-4006-87bf-18826d438ade |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690633706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1690633706 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.1184958468 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 76919752 ps |
CPU time | 20.42 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:33:36 PM PDT 24 |
Peak memory | 268204 kb |
Host | smart-b35385f4-06f9-4583-92a8-c5fd5477a1d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184958468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.1184958468 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1085043021 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 1360690624 ps |
CPU time | 3.53 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:33:02 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-01c5d41e-2b1c-4c5e-af95-6ff3041d1122 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085043021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1085043021 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.2123541109 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 1317849931 ps |
CPU time | 11.96 seconds |
Started | Jul 03 04:32:53 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-94005a9a-523e-4eff-ae09-200dfe9dbe3b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123541109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.2123541109 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.2237496600 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 31700551622 ps |
CPU time | 506.57 seconds |
Started | Jul 03 04:32:44 PM PDT 24 |
Finished | Jul 03 04:41:11 PM PDT 24 |
Peak memory | 321560 kb |
Host | smart-8a2f88f9-c08b-4649-943f-1db935de0c44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237496600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.2237496600 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.3830216304 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 640493309 ps |
CPU time | 8.37 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:33:12 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-ea8813a6-17fa-4497-a72d-23a589abb1b4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830216304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.3830216304 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.632813547 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 74548630759 ps |
CPU time | 420.33 seconds |
Started | Jul 03 04:32:45 PM PDT 24 |
Finished | Jul 03 04:39:46 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-992d74bf-9374-4bd4-ab6e-8cd89a30bd18 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632813547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.sram_ctrl_partial_access_b2b.632813547 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.1952014097 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 51833051 ps |
CPU time | 0.77 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-27fd5ab2-22fc-4135-a638-100c5e0c2ea8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952014097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1952014097 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.694982699 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 2483717647 ps |
CPU time | 895.36 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:47:58 PM PDT 24 |
Peak memory | 375412 kb |
Host | smart-ea772162-5709-4a72-b837-6e9aa71841f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694982699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.694982699 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.3534464308 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 1864614732 ps |
CPU time | 63.69 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:33:47 PM PDT 24 |
Peak memory | 316700 kb |
Host | smart-830cd1e2-32e5-4802-abb3-6d2ff844c54c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534464308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3534464308 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.2081579717 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 86704896555 ps |
CPU time | 1689.13 seconds |
Started | Jul 03 04:32:59 PM PDT 24 |
Finished | Jul 03 05:01:08 PM PDT 24 |
Peak memory | 375780 kb |
Host | smart-65374a21-af00-4ef4-8d2d-f4d511eeb479 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081579717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.2081579717 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1016592858 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 20490058764 ps |
CPU time | 352.27 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:39:09 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-d462914c-ff41-4c4e-8b22-94c571feda65 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016592858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.1016592858 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1924195913 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 242027613 ps |
CPU time | 7.42 seconds |
Started | Jul 03 04:32:53 PM PDT 24 |
Finished | Jul 03 04:33:01 PM PDT 24 |
Peak memory | 236956 kb |
Host | smart-2d68f22e-76ce-4c70-8a7d-a47db7eaa3c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924195913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1924195913 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2797606509 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 2028518345 ps |
CPU time | 726.15 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:45:01 PM PDT 24 |
Peak memory | 372488 kb |
Host | smart-b58b5ec9-33c3-40e2-ad6c-2958945fc939 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797606509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.2797606509 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.2694259506 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 49160850 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:32:57 PM PDT 24 |
Finished | Jul 03 04:32:58 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-a86a6c08-8a26-4161-8142-3be5313ec0c6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694259506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2694259506 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.2944797465 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 4691660075 ps |
CPU time | 70.24 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:34:14 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-99445cdc-5c9b-4e03-86d6-8fd76660178d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944797465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .2944797465 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.316701124 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 7469634560 ps |
CPU time | 978.88 seconds |
Started | Jul 03 04:32:49 PM PDT 24 |
Finished | Jul 03 04:49:08 PM PDT 24 |
Peak memory | 369556 kb |
Host | smart-9f78c371-b1fa-4ece-a58b-688e46400733 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316701124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl e.316701124 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.1226998999 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 590637604 ps |
CPU time | 4.38 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:11 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-f457341d-eed4-4864-afe8-9d928326e078 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226998999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.1226998999 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.2082734262 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 183541796 ps |
CPU time | 111.56 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:35:03 PM PDT 24 |
Peak memory | 366824 kb |
Host | smart-f59c36a3-d37e-4e6d-a2dc-41f83c9bcf04 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082734262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.2082734262 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1316442566 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 87177415 ps |
CPU time | 2.63 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:32:58 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-e8d988cd-4127-4bff-bdeb-cfbdcb474e1d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316442566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1316442566 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.1958126801 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 461004954 ps |
CPU time | 10.74 seconds |
Started | Jul 03 04:32:51 PM PDT 24 |
Finished | Jul 03 04:33:02 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-79d9c295-60e6-4c11-a366-d5f52f2b883d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958126801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1958126801 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3070827545 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 33992579070 ps |
CPU time | 876.71 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:47:43 PM PDT 24 |
Peak memory | 357104 kb |
Host | smart-36bbf5fd-2125-4a83-8275-3f5e7484c3a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070827545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3070827545 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.1561129146 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 545735758 ps |
CPU time | 11.08 seconds |
Started | Jul 03 04:32:55 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-29e7aaf6-ad2c-448d-97c9-bb422518cc8d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561129146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1561129146 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.1124992096 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 26663674 ps |
CPU time | 0.73 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-b7fc1fda-3a48-4afa-b048-db5230d2fac0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124992096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1124992096 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.3788121132 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 59588532234 ps |
CPU time | 1340.27 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:55:02 PM PDT 24 |
Peak memory | 375592 kb |
Host | smart-410c7436-9525-419c-8454-37540242fa77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788121132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3788121132 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.582336966 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 466562835 ps |
CPU time | 7.84 seconds |
Started | Jul 03 04:33:14 PM PDT 24 |
Finished | Jul 03 04:33:23 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-3ea8cc40-f8da-4423-b731-270561255867 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582336966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.582336966 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.535853342 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 170380111879 ps |
CPU time | 1734.37 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 05:01:58 PM PDT 24 |
Peak memory | 375188 kb |
Host | smart-bf64f26f-5866-42bf-baff-c1d6b79c6ca2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535853342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.535853342 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1601139721 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 961589451 ps |
CPU time | 131.52 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:35:14 PM PDT 24 |
Peak memory | 323456 kb |
Host | smart-cd18a45d-44a5-429f-af0f-e6fb0cdb7e52 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1601139721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1601139721 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3525400053 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 3882550068 ps |
CPU time | 392.83 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:39:39 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-0f019d6d-7cc4-4219-bdf7-e0e6b7a45a13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525400053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.3525400053 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1877190261 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 507655144 ps |
CPU time | 33.51 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:46 PM PDT 24 |
Peak memory | 284568 kb |
Host | smart-1d3a0d17-0085-4e2d-afbd-7ca4f2f3b4df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877190261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1877190261 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2214432371 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 9032179349 ps |
CPU time | 779.13 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:46:18 PM PDT 24 |
Peak memory | 370656 kb |
Host | smart-aa0348cf-d8b5-44d2-b1d7-ee7bf7b61f54 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214432371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2214432371 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.4268372256 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 13705604 ps |
CPU time | 0.71 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 04:33:11 PM PDT 24 |
Peak memory | 202540 kb |
Host | smart-5a974380-f7b6-43ea-9d1b-505cfb1e6a9b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268372256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.4268372256 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.780818692 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 6819174390 ps |
CPU time | 77.76 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:34:20 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-0dd8b5f0-5c16-4006-8565-045b42e8d3c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780818692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection. 780818692 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.2555569849 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 1868228282 ps |
CPU time | 147.91 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:35:27 PM PDT 24 |
Peak memory | 344564 kb |
Host | smart-265f7fd8-abcf-42fb-ab65-5ae1b4d6a78e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555569849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.2555569849 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1185238676 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 122415505 ps |
CPU time | 69.1 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:34:23 PM PDT 24 |
Peak memory | 332316 kb |
Host | smart-142fc822-d430-42c8-9afe-e81643ac6736 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185238676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1185238676 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2015749291 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 65449340 ps |
CPU time | 4.68 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:33:08 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-53ca4024-6743-4f10-b876-d63febcfe585 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015749291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.2015749291 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.3805888820 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 366201708 ps |
CPU time | 9.77 seconds |
Started | Jul 03 04:32:51 PM PDT 24 |
Finished | Jul 03 04:33:01 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-b5f7aa6e-a7bd-4d15-8656-e1eb19275ab4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805888820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.3805888820 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.3896079669 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 7587254363 ps |
CPU time | 256.67 seconds |
Started | Jul 03 04:32:46 PM PDT 24 |
Finished | Jul 03 04:37:04 PM PDT 24 |
Peak memory | 331104 kb |
Host | smart-411495c0-b6d2-47f8-981f-0496af6608b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896079669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3896079669 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3555771827 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 383338934 ps |
CPU time | 37.18 seconds |
Started | Jul 03 04:32:57 PM PDT 24 |
Finished | Jul 03 04:33:40 PM PDT 24 |
Peak memory | 290376 kb |
Host | smart-c3213d08-95e9-4562-877f-c9addd793351 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555771827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3555771827 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1721074021 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 17770020443 ps |
CPU time | 385.39 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:39:31 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-688f61b4-04a2-41a5-8f97-7bd97d19c7e1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721074021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.1721074021 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.2933219651 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 47737226 ps |
CPU time | 0.81 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:08 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-ece8b5bb-c756-484e-92ef-d7247c91f013 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933219651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2933219651 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.1055112831 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 7401549256 ps |
CPU time | 674.04 seconds |
Started | Jul 03 04:32:47 PM PDT 24 |
Finished | Jul 03 04:44:02 PM PDT 24 |
Peak memory | 368460 kb |
Host | smart-84004048-df03-4c40-800b-f56338b7f344 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055112831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1055112831 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.845707550 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 443953930 ps |
CPU time | 13.75 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:33:12 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-b27d4b56-ac4c-4da0-be03-3006f5533a0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845707550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.845707550 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.2382329577 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 145816756154 ps |
CPU time | 2502.58 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 05:14:53 PM PDT 24 |
Peak memory | 376336 kb |
Host | smart-b80454ec-181d-493c-ba9f-3701217b5994 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382329577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.2382329577 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1256565741 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1381002765 ps |
CPU time | 125.33 seconds |
Started | Jul 03 04:32:49 PM PDT 24 |
Finished | Jul 03 04:34:55 PM PDT 24 |
Peak memory | 359380 kb |
Host | smart-fe42ffa4-b1dd-424b-b907-76168feb8821 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1256565741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.1256565741 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2509331972 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 3370714200 ps |
CPU time | 241.48 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:36:58 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-cf08019f-e37f-47ca-bb81-32e805ca9174 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509331972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.2509331972 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2450788977 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 367486463 ps |
CPU time | 14.41 seconds |
Started | Jul 03 04:32:52 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 263848 kb |
Host | smart-c5a1ec93-de41-44a0-99b8-1e1ca95ce710 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450788977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2450788977 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2259642063 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 26370922858 ps |
CPU time | 589.56 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:42:52 PM PDT 24 |
Peak memory | 364196 kb |
Host | smart-84a7dd14-bf4c-4edf-89d6-5f3ef9c50c15 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259642063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.2259642063 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.1893406113 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 14619942 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:33:14 PM PDT 24 |
Peak memory | 202468 kb |
Host | smart-812bf35d-fd75-4dad-b46b-843b3c8632be |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893406113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1893406113 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.1640691422 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 15036763891 ps |
CPU time | 80.41 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:34:27 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-4e288c83-f36d-49a1-a24d-5695b48446fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640691422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .1640691422 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.1343264152 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 16396210097 ps |
CPU time | 1427.68 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 04:56:58 PM PDT 24 |
Peak memory | 374736 kb |
Host | smart-17f12fb8-2193-437a-9f5e-a2218ea7aa43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343264152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.1343264152 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.4092071827 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 781583779 ps |
CPU time | 3.56 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-db7792a8-5d8e-47d1-b514-a0f8092e8ee4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092071827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.4092071827 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.2788382959 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 135709002 ps |
CPU time | 135.93 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:35:13 PM PDT 24 |
Peak memory | 369304 kb |
Host | smart-98395b13-f83e-43bc-b473-c1dd554bb929 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788382959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2788382959 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2107728102 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 294714969 ps |
CPU time | 4.99 seconds |
Started | Jul 03 04:33:07 PM PDT 24 |
Finished | Jul 03 04:33:13 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-7264e31c-1c9b-4e66-83ed-9df8877b5826 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107728102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.2107728102 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.1384118380 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 1669266451 ps |
CPU time | 10.74 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:33:13 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-56474b60-2eab-4f81-a5d6-d88ecd0dfa5b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384118380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.1384118380 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.1313239782 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 9668877299 ps |
CPU time | 1010.28 seconds |
Started | Jul 03 04:32:54 PM PDT 24 |
Finished | Jul 03 04:49:45 PM PDT 24 |
Peak memory | 348448 kb |
Host | smart-ba7c3235-35a4-44d7-bf3c-faff810cbe4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313239782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.1313239782 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.242741801 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 2609182790 ps |
CPU time | 91.16 seconds |
Started | Jul 03 04:32:57 PM PDT 24 |
Finished | Jul 03 04:34:28 PM PDT 24 |
Peak memory | 344320 kb |
Host | smart-7ca7a71c-5cd6-4665-a7d2-f058caba466d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242741801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s ram_ctrl_partial_access.242741801 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3640404905 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 322643247124 ps |
CPU time | 593.31 seconds |
Started | Jul 03 04:32:50 PM PDT 24 |
Finished | Jul 03 04:42:44 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-c99799d9-95c0-48b2-b73e-6189ae6d0304 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640404905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3640404905 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.2511511049 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 79501353 ps |
CPU time | 0.8 seconds |
Started | Jul 03 04:32:59 PM PDT 24 |
Finished | Jul 03 04:33:00 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-d903c991-29f8-49df-9faf-0beaf1efdb68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511511049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2511511049 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.2901323088 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 6243770958 ps |
CPU time | 427.85 seconds |
Started | Jul 03 04:33:04 PM PDT 24 |
Finished | Jul 03 04:40:13 PM PDT 24 |
Peak memory | 375904 kb |
Host | smart-bd2a69b2-4916-469e-b267-4c3f46e17f93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901323088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2901323088 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.2584076829 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 8196236640 ps |
CPU time | 17.45 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-e0cffd02-bc3c-429c-90b0-40746944965f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584076829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2584076829 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3309043466 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 10040822532 ps |
CPU time | 269.83 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:37:31 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-99d8e877-4631-4ed3-880e-92c006ff4791 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309043466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.3309043466 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.758268752 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 97885119 ps |
CPU time | 18.39 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:25 PM PDT 24 |
Peak memory | 273316 kb |
Host | smart-7e404fe2-0387-40a4-a766-d6f71380887e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758268752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.758268752 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1332832141 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 1960870999 ps |
CPU time | 683.74 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:44:29 PM PDT 24 |
Peak memory | 375600 kb |
Host | smart-798c02a5-5b28-4c81-92cc-57b248906436 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332832141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1332832141 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.1958978258 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 19302512 ps |
CPU time | 0.7 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-db3182b5-9bf4-4ff4-a4db-5942c06d50eb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958978258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1958978258 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.546369980 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 4555912299 ps |
CPU time | 42.63 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:54 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-5c6dac9d-f723-400f-a00c-6aa1c1db2490 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546369980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 546369980 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.1297732127 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 55555999889 ps |
CPU time | 1093.92 seconds |
Started | Jul 03 04:33:10 PM PDT 24 |
Finished | Jul 03 04:51:24 PM PDT 24 |
Peak memory | 373672 kb |
Host | smart-1b1b181a-4f75-42e6-91ea-5e8706a05993 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297732127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.1297732127 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.80906252 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 502612607 ps |
CPU time | 6.89 seconds |
Started | Jul 03 04:32:50 PM PDT 24 |
Finished | Jul 03 04:32:58 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-a4005492-fe1a-4b0e-9f1b-f8bcc1dda04b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80906252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esca lation.80906252 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3365575588 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 134400753 ps |
CPU time | 36.46 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 04:33:46 PM PDT 24 |
Peak memory | 289800 kb |
Host | smart-be2c3406-d867-4330-b3f8-722eac401c40 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365575588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3365575588 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.4265388800 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 531999175 ps |
CPU time | 3.12 seconds |
Started | Jul 03 04:33:04 PM PDT 24 |
Finished | Jul 03 04:33:08 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-11b74719-ccd1-4da5-9a18-061ae6b29bb5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265388800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.4265388800 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.2643826464 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 590785435 ps |
CPU time | 8.34 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-3718ef2f-a882-4bde-8676-19d4e6797c9b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643826464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.2643826464 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.2954740390 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 29301715577 ps |
CPU time | 436.49 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 04:40:26 PM PDT 24 |
Peak memory | 365880 kb |
Host | smart-bebc83f3-d79d-4ada-8f9b-a6cd01e743ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954740390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.2954740390 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.3571910368 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 656898651 ps |
CPU time | 126.02 seconds |
Started | Jul 03 04:33:10 PM PDT 24 |
Finished | Jul 03 04:35:17 PM PDT 24 |
Peak memory | 368896 kb |
Host | smart-9e1ab926-97fd-4f68-83e5-f8944d6888bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571910368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.3571910368 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.926780002 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 11154093387 ps |
CPU time | 263.59 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:37:31 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-6d989e73-0f30-46af-a565-310d8a6554d0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926780002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.sram_ctrl_partial_access_b2b.926780002 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.938417086 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 86585105 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:33:18 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-b305ac1e-233e-4189-889a-c18f29418c79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938417086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.938417086 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.490821323 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 9327744699 ps |
CPU time | 683.17 seconds |
Started | Jul 03 04:33:04 PM PDT 24 |
Finished | Jul 03 04:44:28 PM PDT 24 |
Peak memory | 351156 kb |
Host | smart-6c88f3c0-3c4e-44ee-887d-e437a81adff2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490821323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.490821323 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.1257601405 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 618669764 ps |
CPU time | 112.81 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:34:57 PM PDT 24 |
Peak memory | 359104 kb |
Host | smart-49470a73-416d-430c-929e-307f85f82cb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257601405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1257601405 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.2066189258 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 50867517345 ps |
CPU time | 643.09 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:43:44 PM PDT 24 |
Peak memory | 376656 kb |
Host | smart-8914381f-cbfa-46bd-a49c-d1d420ce5d4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066189258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.2066189258 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.992918725 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2332972352 ps |
CPU time | 522.74 seconds |
Started | Jul 03 04:32:59 PM PDT 24 |
Finished | Jul 03 04:41:43 PM PDT 24 |
Peak memory | 379308 kb |
Host | smart-617551e5-1948-4c58-b740-d1d483b1acf5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=992918725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.992918725 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2798215342 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 7463845669 ps |
CPU time | 316.33 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:38:21 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-a0317ded-e195-409e-afb0-1371fc7343b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798215342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.2798215342 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4280830522 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 88662458 ps |
CPU time | 14.48 seconds |
Started | Jul 03 04:32:48 PM PDT 24 |
Finished | Jul 03 04:33:03 PM PDT 24 |
Peak memory | 251872 kb |
Host | smart-169d7fac-1074-4147-89b6-8f31b86f21f9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280830522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.4280830522 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.698517619 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 12042896930 ps |
CPU time | 625.39 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:43:40 PM PDT 24 |
Peak memory | 372044 kb |
Host | smart-5a8a1db9-5a31-452f-8e67-ee9d98bc0079 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698517619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sram_ctrl_access_during_key_req.698517619 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.3438942493 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 14917015 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:12 PM PDT 24 |
Peak memory | 202212 kb |
Host | smart-aa19f430-78a8-48aa-9a48-01863fb31bc5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438942493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3438942493 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.2636452330 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 2738600063 ps |
CPU time | 57.92 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:34:11 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-c93a2f3f-d7d1-4e97-a8e3-5249493d0ab8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636452330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2636452330 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.789160649 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 13985366390 ps |
CPU time | 628.32 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:43:41 PM PDT 24 |
Peak memory | 367996 kb |
Host | smart-b68b5a2f-954d-44e6-95fc-ce975db71493 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789160649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl e.789160649 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.3605682259 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 2032366698 ps |
CPU time | 6.63 seconds |
Started | Jul 03 04:32:58 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-63125383-66f6-4b11-ba30-7be52811fd62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605682259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3605682259 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.3762802688 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 387578316 ps |
CPU time | 3.82 seconds |
Started | Jul 03 04:33:14 PM PDT 24 |
Finished | Jul 03 04:33:20 PM PDT 24 |
Peak memory | 221228 kb |
Host | smart-7e237c7e-a2be-4b34-aa8f-1476ecd0f774 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762802688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3762802688 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4156983340 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 86191771 ps |
CPU time | 3.1 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-2f823381-653d-4eb7-bbf6-00204dcfeaf3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156983340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.4156983340 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.4113306720 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 123702391 ps |
CPU time | 5.27 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:27 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-3e48c3f9-c9f5-4317-aef9-ee61d72ad8a2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113306720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.4113306720 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.952047302 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 15872228859 ps |
CPU time | 322.52 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:38:41 PM PDT 24 |
Peak memory | 357580 kb |
Host | smart-97b0f919-e1ed-42be-9fdd-5bc3ab676ce5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952047302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip le_keys.952047302 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.3007844683 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 189860030 ps |
CPU time | 90.25 seconds |
Started | Jul 03 04:33:19 PM PDT 24 |
Finished | Jul 03 04:34:50 PM PDT 24 |
Peak memory | 346900 kb |
Host | smart-c1e5bca8-f1ea-4ef7-b504-19ee78fe2c8c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007844683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.3007844683 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.448226131 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 97192148785 ps |
CPU time | 187.82 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:36:05 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-6f147b2b-9b7d-4639-a51c-1a47d7467e49 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448226131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.sram_ctrl_partial_access_b2b.448226131 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3400523007 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 104632450 ps |
CPU time | 0.77 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-38d8ba46-2d63-46d1-bcf0-eeef48f68fc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400523007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3400523007 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.1310013685 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 12656756535 ps |
CPU time | 312.37 seconds |
Started | Jul 03 04:33:03 PM PDT 24 |
Finished | Jul 03 04:38:16 PM PDT 24 |
Peak memory | 372772 kb |
Host | smart-0453efd1-3871-417d-8bcd-d29a022e7c65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310013685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1310013685 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.2799907294 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 328913783 ps |
CPU time | 12.3 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 247756 kb |
Host | smart-fdb6f94a-b856-4bae-9725-57d20e7b2124 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799907294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2799907294 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.2063143666 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 11646151113 ps |
CPU time | 2600.48 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 05:16:44 PM PDT 24 |
Peak memory | 375728 kb |
Host | smart-5ebb76b4-e216-4656-a294-c6bb9322ba74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063143666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2063143666 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2000097643 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 899610058 ps |
CPU time | 419.56 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:40:00 PM PDT 24 |
Peak memory | 362428 kb |
Host | smart-4e29df8d-8bb2-4271-9b1e-ecaac8a01747 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2000097643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2000097643 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.4036014215 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 4327336363 ps |
CPU time | 203.53 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:36:40 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-825b9a7e-b0b8-42d3-b724-f72bc10e4942 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036014215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.4036014215 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1807586719 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 408410325 ps |
CPU time | 30.34 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:53 PM PDT 24 |
Peak memory | 291436 kb |
Host | smart-f796f460-1229-446d-a51f-7e40606576e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807586719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1807586719 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1523951657 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 3241869955 ps |
CPU time | 1068.58 seconds |
Started | Jul 03 04:32:57 PM PDT 24 |
Finished | Jul 03 04:50:46 PM PDT 24 |
Peak memory | 373660 kb |
Host | smart-ca695c39-11c3-4478-a298-c863406a9747 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523951657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.1523951657 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.2106055816 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 32438792 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:33:04 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-e8274100-b9d8-4a88-a8cd-7f9d728aa929 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106055816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2106055816 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.3313289387 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 3703559114 ps |
CPU time | 80.23 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:34:23 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-71cba386-2954-46a4-b46d-26949d279b39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313289387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .3313289387 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.1464378633 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 13300542934 ps |
CPU time | 1160.61 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:52:29 PM PDT 24 |
Peak memory | 374708 kb |
Host | smart-58be9542-ee31-4590-ba15-00d8dd02c13d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464378633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1464378633 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.1872841573 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 3342795891 ps |
CPU time | 9.59 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-4b73ca97-dc32-4141-b411-6c7fd47f4b3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872841573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.1872841573 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.1455156180 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 472784683 ps |
CPU time | 126.65 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:35:24 PM PDT 24 |
Peak memory | 369404 kb |
Host | smart-f1194eb2-4733-4339-9f6e-c920456c3d09 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455156180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.1455156180 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1679283217 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 398272819 ps |
CPU time | 5.64 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:17 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-23810372-6dbe-4906-8e1e-a73a92d48298 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679283217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1679283217 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.1473810793 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 2632270752 ps |
CPU time | 11.05 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:33:14 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-116a21fc-2334-499b-a4fb-eb18503057ce |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473810793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1473810793 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.4226994548 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 30274181475 ps |
CPU time | 1406.39 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:56:41 PM PDT 24 |
Peak memory | 374712 kb |
Host | smart-148a8e05-d4ea-43b7-8370-e15722840cb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226994548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.4226994548 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.731972866 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 1067447219 ps |
CPU time | 20.14 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:33:34 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-00b95c37-ba59-4ab8-b68a-cf33f52338b0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731972866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s ram_ctrl_partial_access.731972866 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1200446066 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 11680548721 ps |
CPU time | 299.94 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:38:22 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-646345b4-5b84-4d69-a095-74f59312b79f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200446066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1200446066 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.894555807 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 26832379 ps |
CPU time | 0.73 seconds |
Started | Jul 03 04:33:19 PM PDT 24 |
Finished | Jul 03 04:33:20 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-3db602c5-11b0-4055-8eb7-b6f6aadfeacd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894555807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.894555807 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.2487944970 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 21064384908 ps |
CPU time | 257.2 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:37:34 PM PDT 24 |
Peak memory | 374672 kb |
Host | smart-90310f9f-f35f-4831-89d4-c8734d3f9b11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487944970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2487944970 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.3061091548 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 135645370 ps |
CPU time | 98.68 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:35:01 PM PDT 24 |
Peak memory | 356968 kb |
Host | smart-c42eee8c-9c0e-422c-a33c-c38ed5b3968d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061091548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3061091548 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.2468805132 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 370778435369 ps |
CPU time | 2826.91 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 05:20:25 PM PDT 24 |
Peak memory | 374624 kb |
Host | smart-1d365358-97b1-469c-a233-a022c1049028 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468805132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.2468805132 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3864951864 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 32397708361 ps |
CPU time | 209.08 seconds |
Started | Jul 03 04:33:04 PM PDT 24 |
Finished | Jul 03 04:36:34 PM PDT 24 |
Peak memory | 345368 kb |
Host | smart-8c902205-f1ff-476f-8cb0-1bcacf931d11 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3864951864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3864951864 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2661015918 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 2121984394 ps |
CPU time | 144.77 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:35:30 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-d2ca72fd-490d-46ea-852d-a366487103a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661015918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.2661015918 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4214813510 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 1869559482 ps |
CPU time | 96.75 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:34:43 PM PDT 24 |
Peak memory | 350980 kb |
Host | smart-c6374c8f-57ec-4e3f-a2fa-0624cb70a6ea |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214813510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.4214813510 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.732963714 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 10100660759 ps |
CPU time | 871.71 seconds |
Started | Jul 03 04:31:57 PM PDT 24 |
Finished | Jul 03 04:46:29 PM PDT 24 |
Peak memory | 366200 kb |
Host | smart-80d4d4c3-5607-4cc3-ab3d-b961f9d37288 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732963714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_access_during_key_req.732963714 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.2825387040 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 16162590 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:33:03 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-2efee233-0386-4065-8da4-5c097f8b424c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825387040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2825387040 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.3791973967 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 2916935260 ps |
CPU time | 32.63 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:33:05 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-a471a175-08ed-4c94-bd75-199f8bf48589 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791973967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3791973967 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.3450613120 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 13399685431 ps |
CPU time | 884.12 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:47:41 PM PDT 24 |
Peak memory | 373620 kb |
Host | smart-bed63f37-49d3-476d-914b-a9fc01063699 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450613120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.3450613120 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.854015548 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 2016245430 ps |
CPU time | 3.53 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:29 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-6663fd84-fe89-43a3-8f94-09f9ab81e921 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854015548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca lation.854015548 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3081410673 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 572313931 ps |
CPU time | 83.05 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:33:51 PM PDT 24 |
Peak memory | 336104 kb |
Host | smart-344f0522-019f-4f92-968b-eb06d317bffb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081410673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3081410673 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.198627960 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 1360136004 ps |
CPU time | 3.34 seconds |
Started | Jul 03 04:32:06 PM PDT 24 |
Finished | Jul 03 04:32:10 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-bb50be2b-9ef2-4e12-a614-17fe1621367e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198627960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_mem_partial_access.198627960 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.878158424 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 306210179 ps |
CPU time | 5.88 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:33:09 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-698029e1-12f2-4436-92f4-a6d24b220f4e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878158424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.878158424 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.826256146 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 7615624583 ps |
CPU time | 1209.4 seconds |
Started | Jul 03 04:32:00 PM PDT 24 |
Finished | Jul 03 04:52:10 PM PDT 24 |
Peak memory | 375484 kb |
Host | smart-f4c7272d-b8cd-4941-88d9-f792e2eb51f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826256146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.826256146 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.853623185 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 5270487753 ps |
CPU time | 20.93 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:32:58 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-4a2394c6-418d-4c6e-ba69-9ba354d28809 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853623185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.853623185 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3541543587 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 15375904245 ps |
CPU time | 266.88 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:36:59 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-70005c3c-1304-4c94-8865-bca70aaba5dd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541543587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.3541543587 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.757877423 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 186306036 ps |
CPU time | 0.8 seconds |
Started | Jul 03 04:32:08 PM PDT 24 |
Finished | Jul 03 04:32:10 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-d354b2f7-c839-470d-a791-8891d6fa87f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757877423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.757877423 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.2788753138 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 15238775841 ps |
CPU time | 1248.42 seconds |
Started | Jul 03 04:31:58 PM PDT 24 |
Finished | Jul 03 04:52:47 PM PDT 24 |
Peak memory | 374680 kb |
Host | smart-27ad9817-f8f4-4178-a487-1738737f46a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788753138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2788753138 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.509195527 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 221258221 ps |
CPU time | 1.81 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:32:24 PM PDT 24 |
Peak memory | 224408 kb |
Host | smart-e8d711fa-038d-4517-8bb0-0179168e451e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509195527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_sec_cm.509195527 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.1659111218 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 21453198 ps |
CPU time | 0.86 seconds |
Started | Jul 03 04:32:17 PM PDT 24 |
Finished | Jul 03 04:32:18 PM PDT 24 |
Peak memory | 202552 kb |
Host | smart-a907c9af-fa18-418c-ab9f-54fd5573617e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659111218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1659111218 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.2005903094 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 13668452079 ps |
CPU time | 1674.45 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 05:00:04 PM PDT 24 |
Peak memory | 370584 kb |
Host | smart-ee1c2e67-fa70-40d1-8b45-42ed9e454bd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005903094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.2005903094 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.333254288 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 2831928945 ps |
CPU time | 287.66 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:37:08 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-3ceb3a3f-8ab5-4028-9794-edcedaaa2bdd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333254288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.333254288 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1422738179 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 58927390 ps |
CPU time | 2.33 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:32:25 PM PDT 24 |
Peak memory | 217912 kb |
Host | smart-33070634-1934-4734-8556-c696116f4f82 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422738179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1422738179 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1791582796 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 14347159143 ps |
CPU time | 1156.68 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:52:35 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-898fe9a8-dc13-4011-aa32-48510cf33d3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791582796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.1791582796 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.178796871 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 44636064 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:33:18 PM PDT 24 |
Peak memory | 202604 kb |
Host | smart-1588935b-8c1c-45b0-b553-0fe9dc32133b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178796871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.178796871 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.3908840338 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 1102869515 ps |
CPU time | 24.05 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:33:32 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-a993f307-53d8-44f1-9f79-783b4e907070 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908840338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3908840338 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.3993708317 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 4822748607 ps |
CPU time | 1036.22 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:50:36 PM PDT 24 |
Peak memory | 364348 kb |
Host | smart-238ce42f-331c-4918-89df-7558f20b33be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993708317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.3993708317 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.4044804152 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 569272759 ps |
CPU time | 8.22 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:20 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-4cae1381-31f8-4596-b930-ac2ae4066e7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044804152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.4044804152 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.2386240843 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 615991656 ps |
CPU time | 29.48 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 294620 kb |
Host | smart-76aaae66-a5f5-4502-ae0b-c3d4b52562c6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386240843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.2386240843 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1411843440 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 45457492 ps |
CPU time | 2.46 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:24 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-459f3253-3106-40c1-b3e0-679740b138fd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411843440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.1411843440 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.1768021707 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 141886185 ps |
CPU time | 8.48 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:16 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-fa6b9033-2613-4536-8b0c-e3ac70d2592f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768021707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1768021707 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1080411013 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 54769220417 ps |
CPU time | 1317.64 seconds |
Started | Jul 03 04:33:07 PM PDT 24 |
Finished | Jul 03 04:55:05 PM PDT 24 |
Peak memory | 375700 kb |
Host | smart-7d8b67f9-102f-4d2f-aea0-258636d1790c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080411013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1080411013 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.1810574950 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 1006687468 ps |
CPU time | 14.31 seconds |
Started | Jul 03 04:33:04 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 247840 kb |
Host | smart-b0fd21d1-647b-4f20-b676-08934830c9e7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810574950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1810574950 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3056387114 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 18619838189 ps |
CPU time | 370.8 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:39:30 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-8b9e4dba-d761-4cb3-9de4-a62015898870 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056387114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3056387114 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.4212011049 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 85697722 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:33:16 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-d7b93752-f83a-47f9-be7c-fdea417c438c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212011049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.4212011049 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.2523068699 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 1034434446 ps |
CPU time | 125.42 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:35:13 PM PDT 24 |
Peak memory | 319368 kb |
Host | smart-5b6d225b-411b-4825-9a48-8f8b9eb4ebe2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523068699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2523068699 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.689675572 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 369577957 ps |
CPU time | 44.58 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:34:00 PM PDT 24 |
Peak memory | 287044 kb |
Host | smart-c2367670-2dce-41b4-bb54-c3adde7cd063 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689675572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.689675572 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.2381013504 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 20147647670 ps |
CPU time | 987.15 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:49:40 PM PDT 24 |
Peak memory | 381836 kb |
Host | smart-a6217b4f-b43f-4ace-ad97-74c9e88a25e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381013504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.2381013504 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2722483130 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 4666011189 ps |
CPU time | 229.75 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:37:08 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-3c3531a5-4544-4dea-b4e4-f2265b961e8c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722483130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.2722483130 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2345658151 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 147796669 ps |
CPU time | 72.24 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:34:32 PM PDT 24 |
Peak memory | 331780 kb |
Host | smart-d7988888-4d5d-4a5d-a290-666ea8b13f23 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345658151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2345658151 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2961241478 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 3357862076 ps |
CPU time | 1141.14 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:52:26 PM PDT 24 |
Peak memory | 373700 kb |
Host | smart-bd560765-8408-43e8-8e22-592d6a587830 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961241478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2961241478 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.60092202 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 43129281 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:33:04 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-812e1275-1283-4068-b17a-c26600faf982 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60092202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_alert_test.60092202 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.4042079377 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 11897891550 ps |
CPU time | 46.63 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:59 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-bf6884d9-ff4c-47a5-89f9-6fa031a02132 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042079377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .4042079377 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.3524575697 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 59662359572 ps |
CPU time | 842.17 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:47:16 PM PDT 24 |
Peak memory | 375184 kb |
Host | smart-a814b5c4-7298-4965-96f0-c4476e129558 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524575697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.3524575697 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.3396934499 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 663825330 ps |
CPU time | 4.25 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:33:21 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-db73694e-f6e5-4a78-a068-c5141dba01ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396934499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.3396934499 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3107967045 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 524029178 ps |
CPU time | 126.84 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:35:26 PM PDT 24 |
Peak memory | 359004 kb |
Host | smart-e28f8fc2-acb6-4ddc-bd05-e8fc06ef2d20 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107967045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3107967045 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.731958428 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 757185944 ps |
CPU time | 5.63 seconds |
Started | Jul 03 04:33:06 PM PDT 24 |
Finished | Jul 03 04:33:12 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-43d096d0-73e1-49fc-9f97-800e205074ce |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731958428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.731958428 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.1903834178 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1214526009 ps |
CPU time | 6.4 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:33:27 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-0bbfdfdf-ec14-420a-955b-81ff2cffeaa4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903834178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1903834178 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.2557132745 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 590882580 ps |
CPU time | 5.54 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:33:23 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-eddb3f07-ac13-4129-ae54-aa867095795e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557132745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2557132745 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1326475900 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 49856581201 ps |
CPU time | 308.45 seconds |
Started | Jul 03 04:33:05 PM PDT 24 |
Finished | Jul 03 04:38:14 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-c11608a1-ed03-4e5b-98f1-af502dcc91b1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326475900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.1326475900 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.1130198696 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 37554878 ps |
CPU time | 0.82 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-6f9380b2-1a34-4d62-aa27-ea5c54f2855c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130198696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1130198696 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.3195476670 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 10318854416 ps |
CPU time | 626.21 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:43:41 PM PDT 24 |
Peak memory | 356560 kb |
Host | smart-0b372449-75ca-453a-ac5b-200ac2f284a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195476670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3195476670 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1125276112 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 233909350 ps |
CPU time | 15.55 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:33:32 PM PDT 24 |
Peak memory | 258884 kb |
Host | smart-c3532400-670f-40c7-b5da-d9ca0c5d75c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125276112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1125276112 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.923208239 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 33004010842 ps |
CPU time | 1899.13 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 05:04:54 PM PDT 24 |
Peak memory | 375668 kb |
Host | smart-63d3f0a8-556d-43d6-8521-43ebf97d63bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923208239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_stress_all.923208239 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.670227336 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 2117505253 ps |
CPU time | 148.55 seconds |
Started | Jul 03 04:32:56 PM PDT 24 |
Finished | Jul 03 04:35:26 PM PDT 24 |
Peak memory | 344760 kb |
Host | smart-b3834b83-fc37-452e-a890-b9a9aa1a4e2a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=670227336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.670227336 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1847329107 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 1071635958 ps |
CPU time | 94.46 seconds |
Started | Jul 03 04:33:09 PM PDT 24 |
Finished | Jul 03 04:34:44 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-a1c4c275-63d6-4217-adaf-49bb1a493f32 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847329107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.1847329107 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.831862375 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 253991463 ps |
CPU time | 69.83 seconds |
Started | Jul 03 04:33:08 PM PDT 24 |
Finished | Jul 03 04:34:18 PM PDT 24 |
Peak memory | 328064 kb |
Host | smart-28734d4e-d217-43ed-8180-355beb4ef835 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831862375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.831862375 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3600730663 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 12077581720 ps |
CPU time | 762.96 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:46:06 PM PDT 24 |
Peak memory | 373664 kb |
Host | smart-8bee31f5-6130-47e1-beed-c6c7918b2b40 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600730663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.3600730663 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.3827639365 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 12176424 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:33:19 PM PDT 24 |
Finished | Jul 03 04:33:20 PM PDT 24 |
Peak memory | 202244 kb |
Host | smart-11916d94-da39-49e8-93e2-dec92a06ce14 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827639365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3827639365 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.948847787 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 14714067274 ps |
CPU time | 57.42 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-3c12c466-450e-4cb9-9810-bb786780f4fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948847787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 948847787 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.815831397 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 4383721911 ps |
CPU time | 1158.08 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:52:36 PM PDT 24 |
Peak memory | 371328 kb |
Host | smart-1ac19553-b135-460e-b822-39a00c2be21b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815831397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl e.815831397 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.1668079679 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 119822600 ps |
CPU time | 1.72 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:33:15 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-3281c55d-2071-4021-a810-eddf6f18d826 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668079679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1668079679 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.3497540264 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 507663988 ps |
CPU time | 103.56 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:35:01 PM PDT 24 |
Peak memory | 345984 kb |
Host | smart-99e8c87c-88e6-467e-87d1-6c61ff9c1d00 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497540264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.3497540264 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3574578950 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 198501400 ps |
CPU time | 3.48 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:33:28 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-4913055e-3844-45a9-a696-8f42456458a6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574578950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.3574578950 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3963273685 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 200493500 ps |
CPU time | 9.84 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:33:21 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-1eda4b7e-a1e5-49e6-b269-54a16b3a7c3a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963273685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3963273685 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.355896560 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2034589257 ps |
CPU time | 518.26 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:41:38 PM PDT 24 |
Peak memory | 368124 kb |
Host | smart-810f89e3-8779-4381-a4fe-105878edc44e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355896560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip le_keys.355896560 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.2183888892 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 1960038454 ps |
CPU time | 100.35 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:34:54 PM PDT 24 |
Peak memory | 324288 kb |
Host | smart-d0d4284b-e9df-4cbb-8d11-de67e014ab2a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183888892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.2183888892 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1276687307 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 23349750139 ps |
CPU time | 426.44 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:40:30 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-867ac9ee-4c7d-4868-ac55-2def95eddcbb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276687307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.1276687307 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.2131095185 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 82991049 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:33:14 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-5486469e-c9ca-4c95-999c-acf171c0ed14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131095185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2131095185 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.4287656473 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 17087915787 ps |
CPU time | 176.15 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:36:10 PM PDT 24 |
Peak memory | 367908 kb |
Host | smart-6dbe7c26-a7a5-49bb-9a7f-b1ff8f9d62a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287656473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.4287656473 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.315312772 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1346749885 ps |
CPU time | 46.77 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:34:08 PM PDT 24 |
Peak memory | 296244 kb |
Host | smart-57e4114a-0614-481c-ac13-1f7d8fdedac8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315312772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.315312772 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.2337077098 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 123567248827 ps |
CPU time | 2450.43 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 05:14:13 PM PDT 24 |
Peak memory | 373632 kb |
Host | smart-bbf3433f-37b2-492a-9eed-aed022096ee3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337077098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.2337077098 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1002301115 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 301540063 ps |
CPU time | 21.12 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-6b5fdd62-2dcb-4343-b3ab-98cd89a99492 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1002301115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1002301115 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.820136343 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 13100559263 ps |
CPU time | 306.65 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:38:21 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-83894eda-87b6-4d48-8541-41d8a89d1a89 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820136343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_stress_pipeline.820136343 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1914057547 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 292739797 ps |
CPU time | 103.2 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:34:57 PM PDT 24 |
Peak memory | 362348 kb |
Host | smart-03a0dc83-4aab-4b44-a628-5b5cbb8de24b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914057547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1914057547 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3422259122 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 32019048435 ps |
CPU time | 1464.36 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:57:37 PM PDT 24 |
Peak memory | 374324 kb |
Host | smart-9ea7e818-e561-46fc-b4aa-a6cb758501e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422259122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.3422259122 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.975873584 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 24844233 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:33:14 PM PDT 24 |
Finished | Jul 03 04:33:16 PM PDT 24 |
Peak memory | 202284 kb |
Host | smart-b686197a-cb80-4907-ab8e-542e6d16955b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975873584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.975873584 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.1057493782 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 1043445870 ps |
CPU time | 70.57 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:34:36 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-a9e64c16-9496-4171-868e-396bc2a648c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057493782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1057493782 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.2424070616 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 21862204723 ps |
CPU time | 1394.03 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:56:37 PM PDT 24 |
Peak memory | 375740 kb |
Host | smart-24fc655b-b075-45e7-8014-2a2cf9a8cc6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424070616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.2424070616 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.1063522324 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 7316650754 ps |
CPU time | 5.13 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-afc17b08-d03e-468b-bf43-58065ace558f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063522324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.1063522324 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.2177444849 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 212353897 ps |
CPU time | 68.17 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:34:21 PM PDT 24 |
Peak memory | 315940 kb |
Host | smart-c18d9f33-b75e-4ba1-9ed5-5482531a5d13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177444849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2177444849 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1386216021 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 246509839 ps |
CPU time | 4.7 seconds |
Started | Jul 03 04:33:26 PM PDT 24 |
Finished | Jul 03 04:33:31 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-5c0e558c-4487-4903-827f-9160cb19b2f9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386216021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.1386216021 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.4276643424 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 2705295272 ps |
CPU time | 12.18 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:34 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-2c580d2a-bbc0-4853-a69d-2255bc6fedfd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276643424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.4276643424 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.3381425951 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 2975526141 ps |
CPU time | 764.07 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:46:07 PM PDT 24 |
Peak memory | 371204 kb |
Host | smart-dbc4c535-d41a-43fc-953c-a3da0018da8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381425951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.3381425951 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.1960685790 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 2198491725 ps |
CPU time | 9.76 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:33:28 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-838b5e30-504b-4e07-8268-8ecb7f1acba9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960685790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.1960685790 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2306109922 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 87963515990 ps |
CPU time | 560.29 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:42:42 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-b6218f5c-96f2-4dad-ba8f-8a4dbabff22e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306109922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2306109922 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.3109515389 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 40290702 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:33:16 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-eaf20559-cf15-4e73-8e6c-15bfaa7cd3ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109515389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3109515389 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.110165206 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 33769984707 ps |
CPU time | 709.99 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:45:13 PM PDT 24 |
Peak memory | 369296 kb |
Host | smart-a74b5a71-ce5e-4aae-8f9c-cc8a307c9f9d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110165206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.110165206 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.530504469 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 1984859428 ps |
CPU time | 8.02 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:33:25 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-f4a3f80f-a21b-465a-aca0-bee1c9b23703 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530504469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.530504469 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3700345322 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 19235125020 ps |
CPU time | 2442.44 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 05:14:01 PM PDT 24 |
Peak memory | 375832 kb |
Host | smart-c2ca1c06-a83c-4ba3-af87-91c912499731 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700345322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3700345322 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3041273193 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 4012541069 ps |
CPU time | 165.42 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:36:03 PM PDT 24 |
Peak memory | 365984 kb |
Host | smart-f4c1bd66-6533-4565-b091-14b305431044 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3041273193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3041273193 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1294318196 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 9511552454 ps |
CPU time | 183.03 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:36:23 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-4d31e86b-9f47-4f44-a221-bf60d814c01f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294318196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.1294318196 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1261126808 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 591050881 ps |
CPU time | 13.99 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:33:38 PM PDT 24 |
Peak memory | 261020 kb |
Host | smart-5d756daa-f1ee-4c2f-937d-901d955d35a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261126808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1261126808 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2180700311 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 10883044066 ps |
CPU time | 539.82 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:42:23 PM PDT 24 |
Peak memory | 360180 kb |
Host | smart-6109ad18-bae0-4ff7-9da5-a2f603869454 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180700311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.2180700311 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2670762028 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 16920130 ps |
CPU time | 0.69 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 202596 kb |
Host | smart-41825fc8-99ff-4964-970a-d7e6455cf282 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670762028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2670762028 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.644161583 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 11281257356 ps |
CPU time | 65.44 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:34:21 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-7da4d76c-fb72-4bd7-8a5e-2627a8db96cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644161583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 644161583 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.1140523162 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 3826428748 ps |
CPU time | 1173.24 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:52:57 PM PDT 24 |
Peak memory | 373756 kb |
Host | smart-9f229eeb-a48f-4124-82bb-1cdd8009decc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140523162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1140523162 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.2485919276 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 4006318360 ps |
CPU time | 4.14 seconds |
Started | Jul 03 04:33:10 PM PDT 24 |
Finished | Jul 03 04:33:15 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-b43b728a-98b9-42fa-8674-2ae8a87ac4b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485919276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.2485919276 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.2235338156 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 124833891 ps |
CPU time | 76.02 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:34:40 PM PDT 24 |
Peak memory | 357536 kb |
Host | smart-bbadcd08-58ae-42b1-8a51-772727e765c8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235338156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2235338156 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2798097833 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 647321358 ps |
CPU time | 4.9 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:33:23 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-2a37179a-ddee-4a0c-b5da-da344addb6bb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798097833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2798097833 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.1034585320 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 265667912 ps |
CPU time | 5.98 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:33:26 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-a1af4a49-3a70-4b04-972e-e7d6b00abf95 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034585320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.1034585320 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1904252205 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 61301265787 ps |
CPU time | 1304.48 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:55:06 PM PDT 24 |
Peak memory | 374700 kb |
Host | smart-ab5431ec-630e-4721-a1af-20470191e6ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904252205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1904252205 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.3543906558 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 2718231848 ps |
CPU time | 139.58 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:35:43 PM PDT 24 |
Peak memory | 364096 kb |
Host | smart-041665e0-7ee0-4464-a439-c8fc63124f36 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543906558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.3543906558 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3223579985 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 3580863272 ps |
CPU time | 227.83 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:37:08 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-43855030-1dde-445c-82b7-b713efd1a4df |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223579985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.3223579985 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.714098487 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 29518484 ps |
CPU time | 0.81 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-d7ca74ad-6fdb-4b4c-9a5e-ac4fb7b12159 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714098487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.714098487 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1153597215 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 145976103 ps |
CPU time | 1.32 seconds |
Started | Jul 03 04:33:12 PM PDT 24 |
Finished | Jul 03 04:33:15 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-85ef6366-dac5-4124-974b-d9cb49064093 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153597215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1153597215 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.559423769 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 22710754622 ps |
CPU time | 3295.53 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 05:28:21 PM PDT 24 |
Peak memory | 376772 kb |
Host | smart-1d3da140-91dd-4e02-aeb2-2e633a5078c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559423769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_stress_all.559423769 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.434120349 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 9516637226 ps |
CPU time | 1042.46 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:50:48 PM PDT 24 |
Peak memory | 383060 kb |
Host | smart-9c718877-5561-4b94-aacb-7b6aa6410c57 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=434120349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.434120349 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1389610132 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 7979954457 ps |
CPU time | 217.04 seconds |
Started | Jul 03 04:33:15 PM PDT 24 |
Finished | Jul 03 04:36:53 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-d48b2396-63a4-4331-bfdd-db7c75b4e34b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389610132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.1389610132 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3332667310 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 98060492 ps |
CPU time | 3.79 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:33:22 PM PDT 24 |
Peak memory | 220176 kb |
Host | smart-c9d5c56c-1a91-45cd-b1b8-195660338662 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332667310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3332667310 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1598635914 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 5477977816 ps |
CPU time | 303.14 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:38:29 PM PDT 24 |
Peak memory | 323328 kb |
Host | smart-3ab6916c-c0cb-41ae-b78f-9bc75ad26d5f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598635914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.1598635914 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.1214153078 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 31185166 ps |
CPU time | 0.62 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:33:25 PM PDT 24 |
Peak memory | 202472 kb |
Host | smart-759b8d34-6967-4a55-994b-e1f171ecd7d5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214153078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1214153078 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.763301900 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 1560388560 ps |
CPU time | 26.44 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:33:52 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-88cce4ac-5338-4ade-8abf-76cb0c663a71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763301900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection. 763301900 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.2150589370 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 1884323838 ps |
CPU time | 63.49 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:34:29 PM PDT 24 |
Peak memory | 294836 kb |
Host | smart-043f9243-0af3-498e-ab64-ff911391c37a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150589370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2150589370 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.1351849333 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 1436545486 ps |
CPU time | 7.97 seconds |
Started | Jul 03 04:33:29 PM PDT 24 |
Finished | Jul 03 04:33:38 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-cf7260b0-a0d8-4269-9b2d-d738862fcac9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351849333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.1351849333 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.135858698 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 576282014 ps |
CPU time | 129.06 seconds |
Started | Jul 03 04:33:14 PM PDT 24 |
Finished | Jul 03 04:35:25 PM PDT 24 |
Peak memory | 367300 kb |
Host | smart-93c59115-f330-4383-80df-48cf657a9c2d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135858698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_max_throughput.135858698 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3801571482 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 109246589 ps |
CPU time | 3.07 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:33:26 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-809f4660-0045-4554-953a-3ce67fa8257b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801571482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3801571482 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.1401405593 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 232301128 ps |
CPU time | 5.67 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:33:28 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-41c30e95-069f-41c3-b4bc-d9b033cf6fce |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401405593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.1401405593 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.1942161264 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 18546521851 ps |
CPU time | 1251.39 seconds |
Started | Jul 03 04:33:11 PM PDT 24 |
Finished | Jul 03 04:54:04 PM PDT 24 |
Peak memory | 371240 kb |
Host | smart-c3e63eb0-6935-4373-b593-9e9ba865e4c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942161264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.1942161264 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3351056370 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 109674286 ps |
CPU time | 3.59 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:33:29 PM PDT 24 |
Peak memory | 211868 kb |
Host | smart-83b02f80-f710-4813-9a86-cb65cc27b10a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351056370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3351056370 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4196295655 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 82769406259 ps |
CPU time | 530.2 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:42:13 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-e2595084-b4a4-49b2-9953-9fcdcb774a60 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196295655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.4196295655 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.4091090242 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 280765172 ps |
CPU time | 0.82 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:33:24 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-e4f15d89-168a-4735-8745-a508ae790f2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091090242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.4091090242 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.733355109 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1914248799 ps |
CPU time | 184.24 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:36:31 PM PDT 24 |
Peak memory | 366208 kb |
Host | smart-7cdc0125-0013-410e-9e02-4363db03ca6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733355109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.733355109 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.4137273026 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 611530399 ps |
CPU time | 6.67 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:33:32 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-47774bb0-19af-4c24-9156-7beb821e2678 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137273026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4137273026 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.3455726879 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 4458238407 ps |
CPU time | 1569.8 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:59:34 PM PDT 24 |
Peak memory | 382944 kb |
Host | smart-9fe111f0-041c-413c-b5c9-3df90255620f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455726879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.3455726879 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3948064692 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 4404222627 ps |
CPU time | 227.7 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:37:11 PM PDT 24 |
Peak memory | 372440 kb |
Host | smart-998d3eae-e8f1-4bc4-8e49-9307d91a6e6a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3948064692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3948064692 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2068902054 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 2465961960 ps |
CPU time | 243.48 seconds |
Started | Jul 03 04:33:20 PM PDT 24 |
Finished | Jul 03 04:37:24 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-ec2cf09d-5d7a-444e-b204-6a47b87591d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068902054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.2068902054 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4193038033 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 250986308 ps |
CPU time | 66.87 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:34:34 PM PDT 24 |
Peak memory | 325528 kb |
Host | smart-ad3de785-917d-4738-841c-d18bdd59800d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193038033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4193038033 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1953001235 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 891819129 ps |
CPU time | 55.66 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:34:20 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-362737c2-f4e2-413c-9e57-7acfccaf4db3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953001235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.1953001235 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1550063059 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 13035675 ps |
CPU time | 0.62 seconds |
Started | Jul 03 04:33:18 PM PDT 24 |
Finished | Jul 03 04:33:19 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-0548a082-9bef-4a0f-881a-3fe9bffdb8d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550063059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1550063059 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.516577210 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 20738069576 ps |
CPU time | 90.11 seconds |
Started | Jul 03 04:33:16 PM PDT 24 |
Finished | Jul 03 04:34:48 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-a52f9f22-0837-45d0-9a79-bc86df63a4fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516577210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection. 516577210 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.3619882852 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 11153377499 ps |
CPU time | 761.64 seconds |
Started | Jul 03 04:33:28 PM PDT 24 |
Finished | Jul 03 04:46:10 PM PDT 24 |
Peak memory | 370608 kb |
Host | smart-414d45d5-91c0-4b9c-8e1d-537f794a5e71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619882852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3619882852 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.960372710 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 894343637 ps |
CPU time | 4.1 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-97f26ea9-ba92-40fa-a5e8-f725cab8345f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960372710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esc alation.960372710 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.1685328595 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 395192332 ps |
CPU time | 46.44 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:34:11 PM PDT 24 |
Peak memory | 306024 kb |
Host | smart-ff487dcd-0e44-45fb-80c3-36c6a73d93b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685328595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.1685328595 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3676746110 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 834412712 ps |
CPU time | 5.96 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:33:29 PM PDT 24 |
Peak memory | 210928 kb |
Host | smart-9be1c6c8-0972-4a6a-855d-40bb3524e58e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676746110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.3676746110 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.785217271 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 527578470 ps |
CPU time | 5.31 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:33:33 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-55234ce4-b393-405f-aa82-9a4fa0d913cb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785217271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _mem_walk.785217271 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.754995302 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 6235483680 ps |
CPU time | 652.32 seconds |
Started | Jul 03 04:33:17 PM PDT 24 |
Finished | Jul 03 04:44:10 PM PDT 24 |
Peak memory | 371324 kb |
Host | smart-d9f75558-d4b5-4fd1-869d-588f41e51613 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754995302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip le_keys.754995302 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.4170492273 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 142276625 ps |
CPU time | 27.74 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:33:52 PM PDT 24 |
Peak memory | 282860 kb |
Host | smart-237003dc-ac01-48f1-8b60-700f40f377f0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170492273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.4170492273 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2347398805 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 8087249272 ps |
CPU time | 520.81 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:42:06 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-5a4af0a1-7532-4519-b9d3-1b8a9b5c0fa4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347398805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2347398805 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.3189421944 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 91441907 ps |
CPU time | 0.74 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:33:26 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-c19fbe30-9fd8-4bfc-b269-b8dd96c8354c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189421944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3189421944 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.1291498026 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 3195721191 ps |
CPU time | 822.4 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:47:05 PM PDT 24 |
Peak memory | 374948 kb |
Host | smart-d9c19783-bc7b-46aa-b576-bea57c76a8fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291498026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1291498026 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.2297326252 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 245238580 ps |
CPU time | 2.42 seconds |
Started | Jul 03 04:33:13 PM PDT 24 |
Finished | Jul 03 04:33:17 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-f53cd9eb-8151-4067-bed3-cab678a6996e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297326252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2297326252 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.3764863332 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 19495241401 ps |
CPU time | 1666.99 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 05:01:11 PM PDT 24 |
Peak memory | 375736 kb |
Host | smart-37e3350f-8f83-4e3b-9976-ba234c94e920 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764863332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.3764863332 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3959503778 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 3153948460 ps |
CPU time | 48.43 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 228444 kb |
Host | smart-99e1bf0a-7e14-43a4-b144-2c8b6ffb2916 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3959503778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3959503778 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.882518753 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 8340278674 ps |
CPU time | 201.24 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:36:49 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-eee81936-55a7-494c-9438-41c56ee13ef2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882518753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_stress_pipeline.882518753 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2387215776 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 498140329 ps |
CPU time | 5.65 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 227972 kb |
Host | smart-a6bd37e5-ca39-41d5-bd47-0df4e619ddc9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387215776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2387215776 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2655981908 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2829530703 ps |
CPU time | 1084.95 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:51:29 PM PDT 24 |
Peak memory | 374620 kb |
Host | smart-bac536e9-cc38-4656-b0af-39bff356a9e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655981908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.2655981908 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.3459799803 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 14726681 ps |
CPU time | 0.63 seconds |
Started | Jul 03 04:33:28 PM PDT 24 |
Finished | Jul 03 04:33:29 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-cb575810-15e5-4c4c-8fe1-b0cdb7a9b7c5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459799803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3459799803 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.2825513235 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 4186050085 ps |
CPU time | 72.52 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:34:36 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-55585270-43c8-4256-8104-35b23d163d93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825513235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .2825513235 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.281540031 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 5490508709 ps |
CPU time | 1089.49 seconds |
Started | Jul 03 04:33:31 PM PDT 24 |
Finished | Jul 03 04:51:41 PM PDT 24 |
Peak memory | 374708 kb |
Host | smart-f78c7a7d-1b0e-41e3-a025-3086813a0b11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281540031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl e.281540031 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.1137686528 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 983664291 ps |
CPU time | 5.77 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:33:29 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-0eb7ca0d-5569-48f7-817c-956c7dba0453 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137686528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.1137686528 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.1214082059 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 83999737 ps |
CPU time | 19.74 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:33:45 PM PDT 24 |
Peak memory | 276856 kb |
Host | smart-bd2787c9-ce0a-4f9c-88de-efa6541c470b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214082059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.1214082059 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.456514705 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 347024372 ps |
CPU time | 3.09 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:33:27 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-69cff659-c2cb-43c1-a9f2-9f17f3e2d55d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456514705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.456514705 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.133031691 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 338996895 ps |
CPU time | 5.99 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-cbeea9d3-8f3f-431c-ab55-b499e6cb55f4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133031691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.133031691 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.3986289606 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 5509545200 ps |
CPU time | 101.25 seconds |
Started | Jul 03 04:33:28 PM PDT 24 |
Finished | Jul 03 04:35:10 PM PDT 24 |
Peak memory | 306400 kb |
Host | smart-ec76cc3b-b2cd-4218-8021-3f88b240bc10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986289606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.3986289606 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.2503581534 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 1151453478 ps |
CPU time | 63.93 seconds |
Started | Jul 03 04:33:22 PM PDT 24 |
Finished | Jul 03 04:34:28 PM PDT 24 |
Peak memory | 322372 kb |
Host | smart-b41261fe-3937-4641-b868-9b8dd2ffee10 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503581534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2503581534 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1532874224 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 19035803449 ps |
CPU time | 396.76 seconds |
Started | Jul 03 04:33:26 PM PDT 24 |
Finished | Jul 03 04:40:03 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-05214fa2-76cf-40e9-956b-f223586745a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532874224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.1532874224 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2188001945 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 27363763 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:33:27 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-dabdd235-272c-4163-ab9d-dae738a4eaf4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188001945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2188001945 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3950927408 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 6442238393 ps |
CPU time | 377.33 seconds |
Started | Jul 03 04:33:25 PM PDT 24 |
Finished | Jul 03 04:39:43 PM PDT 24 |
Peak memory | 367824 kb |
Host | smart-ce02df38-7865-4149-9971-1c11b625318d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950927408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3950927408 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.252952347 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 207144450 ps |
CPU time | 1.78 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:33:30 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-3fb60114-30c4-42e0-9ca4-11adca7ad159 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252952347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.252952347 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3435143964 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 12139213771 ps |
CPU time | 339.98 seconds |
Started | Jul 03 04:33:21 PM PDT 24 |
Finished | Jul 03 04:39:02 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-f6221f62-e451-4939-8650-efa3414529e2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435143964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.3435143964 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1851504270 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 238074607 ps |
CPU time | 51.3 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:34:16 PM PDT 24 |
Peak memory | 305764 kb |
Host | smart-6ea32e59-25aa-44e4-9c2c-460d4ef26c6e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851504270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1851504270 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2431510744 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 2698062803 ps |
CPU time | 285.86 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:38:13 PM PDT 24 |
Peak memory | 346984 kb |
Host | smart-141e0ceb-0317-4006-bfaf-396399b54e40 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431510744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.2431510744 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.1150864186 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 13782365 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:33:34 PM PDT 24 |
Peak memory | 202504 kb |
Host | smart-f773e225-365c-4692-8510-4c6800a83ccd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150864186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1150864186 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2196744077 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 1434026424 ps |
CPU time | 24.92 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:33:50 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-507c7097-7d57-4118-ac93-a6a751763a7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196744077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2196744077 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.3950470843 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 18586792363 ps |
CPU time | 650.88 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:44:19 PM PDT 24 |
Peak memory | 339880 kb |
Host | smart-327c7683-c67f-44a5-94cb-1f1c743e938a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950470843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.3950470843 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.2844611333 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 40135834 ps |
CPU time | 1.11 seconds |
Started | Jul 03 04:33:28 PM PDT 24 |
Finished | Jul 03 04:33:29 PM PDT 24 |
Peak memory | 202604 kb |
Host | smart-0cd3e7b6-a2be-4a02-9575-9d40dfddaef6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844611333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2844611333 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.2158962704 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 56791855 ps |
CPU time | 6.33 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:33:34 PM PDT 24 |
Peak memory | 235540 kb |
Host | smart-1e5f665f-b6d3-4f58-81cc-0899fc6a3b47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158962704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.2158962704 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.154162385 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 323957456 ps |
CPU time | 5.85 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:33:40 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-c31f4c05-8f17-487f-b353-0a6f991ca28e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154162385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_mem_partial_access.154162385 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.2652028401 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 882190836 ps |
CPU time | 10.97 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:33:38 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-307434f9-49fd-4524-a701-16dfabbbeb39 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652028401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.2652028401 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.4194594038 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 29028581281 ps |
CPU time | 636.94 seconds |
Started | Jul 03 04:33:31 PM PDT 24 |
Finished | Jul 03 04:44:09 PM PDT 24 |
Peak memory | 366368 kb |
Host | smart-39a4d075-ca11-460b-b6f5-3860c7b6d299 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194594038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.4194594038 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.1984683824 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 404482167 ps |
CPU time | 11.79 seconds |
Started | Jul 03 04:33:32 PM PDT 24 |
Finished | Jul 03 04:33:45 PM PDT 24 |
Peak memory | 238332 kb |
Host | smart-c5981a1d-5ded-4209-92a8-37a00653635c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984683824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.1984683824 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2739934545 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 9149960020 ps |
CPU time | 205.82 seconds |
Started | Jul 03 04:33:29 PM PDT 24 |
Finished | Jul 03 04:36:55 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-01eabfe7-b6a2-40f9-8c2d-9b1dad5f0bab |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739934545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.2739934545 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.929392990 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 30241556 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:33:32 PM PDT 24 |
Finished | Jul 03 04:33:33 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-6f0e7927-52d3-4849-9a0e-879ca3a36c58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929392990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.929392990 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.4289091593 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 13193235659 ps |
CPU time | 502.06 seconds |
Started | Jul 03 04:33:23 PM PDT 24 |
Finished | Jul 03 04:41:47 PM PDT 24 |
Peak memory | 368540 kb |
Host | smart-02481fba-f832-42af-8e8b-c3de54a40dce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289091593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.4289091593 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.638148093 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 4879190830 ps |
CPU time | 19.06 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:33:47 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-f2f9071b-1a65-46bc-8740-683f20f587d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638148093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.638148093 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.1338488104 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 15672175855 ps |
CPU time | 2696.56 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 05:18:24 PM PDT 24 |
Peak memory | 376736 kb |
Host | smart-4f5cf781-c78b-4721-917c-0770d356ef79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338488104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.1338488104 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.705587043 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1318472143 ps |
CPU time | 19.52 seconds |
Started | Jul 03 04:33:36 PM PDT 24 |
Finished | Jul 03 04:33:56 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-ba6117f8-a71a-421d-95df-9c301db71da2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=705587043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.705587043 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2824377538 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2929802157 ps |
CPU time | 283.16 seconds |
Started | Jul 03 04:33:28 PM PDT 24 |
Finished | Jul 03 04:38:12 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-9e363c8f-d351-4b6d-8f69-5c2e412fe9d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824377538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.2824377538 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3373180562 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 693962527 ps |
CPU time | 103.05 seconds |
Started | Jul 03 04:33:31 PM PDT 24 |
Finished | Jul 03 04:35:15 PM PDT 24 |
Peak memory | 356528 kb |
Host | smart-89ad7014-adbe-4f40-a075-ef66efef8d70 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373180562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3373180562 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.615517014 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 3346500525 ps |
CPU time | 870.65 seconds |
Started | Jul 03 04:33:30 PM PDT 24 |
Finished | Jul 03 04:48:01 PM PDT 24 |
Peak memory | 367264 kb |
Host | smart-98e97d6c-007c-44a2-9406-04fb18dfd227 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615517014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.615517014 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.1366371909 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 20707930 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:33:31 PM PDT 24 |
Finished | Jul 03 04:33:32 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-ca16e48e-f9cd-4270-92b9-4bd5ab11c192 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366371909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1366371909 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.872527180 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 1903120085 ps |
CPU time | 42.35 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:34:16 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-3633afbd-299e-43d8-a73d-9f25dea82289 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872527180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection. 872527180 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.846178140 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 24291586871 ps |
CPU time | 1350.99 seconds |
Started | Jul 03 04:33:34 PM PDT 24 |
Finished | Jul 03 04:56:06 PM PDT 24 |
Peak memory | 375384 kb |
Host | smart-2a8f4f5f-f76c-43eb-8d00-8c4b94fdb571 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846178140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl e.846178140 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.1221073543 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 1421133832 ps |
CPU time | 6.06 seconds |
Started | Jul 03 04:33:28 PM PDT 24 |
Finished | Jul 03 04:33:35 PM PDT 24 |
Peak memory | 214440 kb |
Host | smart-ede38a6a-f06f-46a6-8fd4-7a63d591776c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221073543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.1221073543 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.3659483734 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 445574207 ps |
CPU time | 84.27 seconds |
Started | Jul 03 04:33:27 PM PDT 24 |
Finished | Jul 03 04:34:51 PM PDT 24 |
Peak memory | 335600 kb |
Host | smart-8f43db6f-c090-4fc2-bc71-ef97a47aa7e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659483734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.3659483734 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2174097554 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 119505531 ps |
CPU time | 4.28 seconds |
Started | Jul 03 04:33:35 PM PDT 24 |
Finished | Jul 03 04:33:40 PM PDT 24 |
Peak memory | 210904 kb |
Host | smart-b30c4cb7-9b51-4531-8dda-ecc38bd5a18e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174097554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.2174097554 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.2344268866 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1376662880 ps |
CPU time | 10.37 seconds |
Started | Jul 03 04:33:32 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-73a9eb86-5f0c-40cd-aa9d-82bec6e054be |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344268866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.2344268866 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.490958908 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 26192463453 ps |
CPU time | 938.44 seconds |
Started | Jul 03 04:33:34 PM PDT 24 |
Finished | Jul 03 04:49:13 PM PDT 24 |
Peak memory | 364740 kb |
Host | smart-ee2f9fce-c790-4ac9-a226-543c4d8e5e1c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490958908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip le_keys.490958908 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.4223570147 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 238119864 ps |
CPU time | 12.88 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:33:47 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-125c2d8c-d294-4d2c-a199-2824bafa26cc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223570147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.4223570147 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1835049177 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 8358052538 ps |
CPU time | 145.82 seconds |
Started | Jul 03 04:33:24 PM PDT 24 |
Finished | Jul 03 04:35:51 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-c654e28b-a3bc-4597-8064-872c4427d838 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835049177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.1835049177 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.3731224895 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 67601956 ps |
CPU time | 0.79 seconds |
Started | Jul 03 04:33:30 PM PDT 24 |
Finished | Jul 03 04:33:31 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-0692077a-afd4-4a55-9452-720f13ff8e5b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731224895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3731224895 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.3014754014 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 18437276804 ps |
CPU time | 1221.03 seconds |
Started | Jul 03 04:33:34 PM PDT 24 |
Finished | Jul 03 04:53:55 PM PDT 24 |
Peak memory | 374692 kb |
Host | smart-51b72d17-4cec-4031-951e-ec9b2eab8dd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014754014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3014754014 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.133171444 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1282490797 ps |
CPU time | 95 seconds |
Started | Jul 03 04:33:34 PM PDT 24 |
Finished | Jul 03 04:35:09 PM PDT 24 |
Peak memory | 348912 kb |
Host | smart-d6949caf-9cb1-4975-a628-8a77291dce9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133171444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.133171444 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.852437803 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 10560177400 ps |
CPU time | 2612.67 seconds |
Started | Jul 03 04:33:32 PM PDT 24 |
Finished | Jul 03 05:17:05 PM PDT 24 |
Peak memory | 371628 kb |
Host | smart-c1ffaa58-3279-4f5a-840c-5b4138899dea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852437803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_stress_all.852437803 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.337557314 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1924041547 ps |
CPU time | 46.56 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:34:20 PM PDT 24 |
Peak memory | 304472 kb |
Host | smart-5b39cf6b-1cb9-4961-a6e7-731e11ed68d8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=337557314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.337557314 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.137419021 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 7446501689 ps |
CPU time | 205.74 seconds |
Started | Jul 03 04:33:34 PM PDT 24 |
Finished | Jul 03 04:37:00 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-63351613-1f4e-4649-8354-17dd9be357be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137419021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_stress_pipeline.137419021 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3193470094 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 134437345 ps |
CPU time | 94.93 seconds |
Started | Jul 03 04:33:34 PM PDT 24 |
Finished | Jul 03 04:35:09 PM PDT 24 |
Peak memory | 330132 kb |
Host | smart-3fae005a-8977-44a2-a2d4-d7f30f42ad4d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193470094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3193470094 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3740715324 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 11599238797 ps |
CPU time | 1043.32 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:49:51 PM PDT 24 |
Peak memory | 368880 kb |
Host | smart-09d96927-4f5e-4fa9-9752-68661e92aa57 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740715324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3740715324 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.3615371950 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 36249132 ps |
CPU time | 0.62 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:32:33 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-fe8237b8-74e9-434c-9807-9647b0a63bc3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615371950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3615371950 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.2960281545 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 21700284189 ps |
CPU time | 66.09 seconds |
Started | Jul 03 04:32:12 PM PDT 24 |
Finished | Jul 03 04:33:18 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-e87331d2-eb72-43bb-8a79-14a2e6f562d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960281545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 2960281545 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.3521407493 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 19353684687 ps |
CPU time | 1541.33 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:58:10 PM PDT 24 |
Peak memory | 374624 kb |
Host | smart-58731988-c271-4617-b8d3-316a59868eb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521407493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.3521407493 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.3949554389 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 160413456 ps |
CPU time | 1.7 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:27 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-ef858db1-1141-4f6f-99aa-b701ca68975c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949554389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.3949554389 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.3472957909 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 272635221 ps |
CPU time | 12.69 seconds |
Started | Jul 03 04:33:00 PM PDT 24 |
Finished | Jul 03 04:33:14 PM PDT 24 |
Peak memory | 251876 kb |
Host | smart-75ac06d1-2b45-4e74-83c4-be58a48377eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472957909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.3472957909 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3069568740 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 310676519 ps |
CPU time | 3.03 seconds |
Started | Jul 03 04:32:05 PM PDT 24 |
Finished | Jul 03 04:32:09 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-135018f5-e90d-47fa-9518-e92044510d22 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069568740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.3069568740 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.1857573350 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 338752313 ps |
CPU time | 5.85 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:32:28 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-d87b1023-071d-45b7-ae11-adadb0b386bf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857573350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.1857573350 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.481883016 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 6169276283 ps |
CPU time | 399.03 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:39:12 PM PDT 24 |
Peak memory | 367752 kb |
Host | smart-f12a71fa-e3ea-4d93-98ec-2994194abdb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481883016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.481883016 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.3745742781 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 2340687044 ps |
CPU time | 6.6 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:32:21 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-7584921c-6f37-4a01-86fb-97b4b89e8b03 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745742781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.3745742781 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.739415645 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 18730422069 ps |
CPU time | 439.34 seconds |
Started | Jul 03 04:31:58 PM PDT 24 |
Finished | Jul 03 04:39:18 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-176c139a-ef2a-4966-bf75-617aa316f652 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739415645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.sram_ctrl_partial_access_b2b.739415645 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.2786441169 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 43959471 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:29 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-2887edfc-a126-495a-a30a-cb40eb294fe3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786441169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2786441169 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.3199720663 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 5517318573 ps |
CPU time | 553.03 seconds |
Started | Jul 03 04:33:02 PM PDT 24 |
Finished | Jul 03 04:42:16 PM PDT 24 |
Peak memory | 373680 kb |
Host | smart-a60ebbec-9083-4cba-a9e9-7dac69057ec4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199720663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3199720663 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.3634209643 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 447146782 ps |
CPU time | 3.05 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:32:25 PM PDT 24 |
Peak memory | 224544 kb |
Host | smart-3e55c9f7-6744-4232-9eff-56e8b38ca4ac |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634209643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3634209643 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.729115245 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 2646895959 ps |
CPU time | 9.59 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:33 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-0f24d113-0a89-40f5-a260-8ef297b65f19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729115245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.729115245 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.1087287954 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 23799257799 ps |
CPU time | 1562.14 seconds |
Started | Jul 03 04:32:18 PM PDT 24 |
Finished | Jul 03 04:58:21 PM PDT 24 |
Peak memory | 374760 kb |
Host | smart-79bc324c-d920-4bde-95e8-46ee3d395108 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087287954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.1087287954 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2372222441 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1288890315 ps |
CPU time | 77.63 seconds |
Started | Jul 03 04:32:08 PM PDT 24 |
Finished | Jul 03 04:33:27 PM PDT 24 |
Peak memory | 300724 kb |
Host | smart-d0b5cc80-6c15-46ec-898d-816aff60cc7b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2372222441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2372222441 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3348862843 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 7304684560 ps |
CPU time | 365.82 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:38:37 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-51e1639d-d1bf-4288-b111-0e1a6383b2cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348862843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3348862843 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.729125027 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 596305252 ps |
CPU time | 107 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:34:28 PM PDT 24 |
Peak memory | 369484 kb |
Host | smart-a615e109-2a88-48c1-acc6-4ddd1daf1fee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729125027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.729125027 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.895111297 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 2952947732 ps |
CPU time | 761.9 seconds |
Started | Jul 03 04:33:37 PM PDT 24 |
Finished | Jul 03 04:46:20 PM PDT 24 |
Peak memory | 360392 kb |
Host | smart-54b96f0a-c62e-4e5c-8eba-9112e9364a2b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895111297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.sram_ctrl_access_during_key_req.895111297 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.2058907453 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 15862101 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:33:53 PM PDT 24 |
Finished | Jul 03 04:33:54 PM PDT 24 |
Peak memory | 202516 kb |
Host | smart-b0427532-667c-46ee-9628-16420f9c8ff5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058907453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.2058907453 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.3331454389 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 586228658 ps |
CPU time | 35.93 seconds |
Started | Jul 03 04:33:31 PM PDT 24 |
Finished | Jul 03 04:34:08 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-c690ebc8-38e6-42f3-b6b2-325230468ee3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331454389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .3331454389 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.4292036832 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 104695910907 ps |
CPU time | 1830.19 seconds |
Started | Jul 03 04:33:41 PM PDT 24 |
Finished | Jul 03 05:04:11 PM PDT 24 |
Peak memory | 372680 kb |
Host | smart-cdf12c67-4613-46a4-b68c-c797b55b39ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292036832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.4292036832 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.3149192186 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 996432316 ps |
CPU time | 3.08 seconds |
Started | Jul 03 04:33:40 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-cea0dd81-e4f2-45d5-8c50-98c47830d475 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149192186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.3149192186 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.4177935275 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1152401233 ps |
CPU time | 70.14 seconds |
Started | Jul 03 04:33:32 PM PDT 24 |
Finished | Jul 03 04:34:42 PM PDT 24 |
Peak memory | 345856 kb |
Host | smart-ee7f6057-27b1-4fe4-b9c0-9a8e91504526 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177935275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.4177935275 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.422883444 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 118048156 ps |
CPU time | 3.16 seconds |
Started | Jul 03 04:33:48 PM PDT 24 |
Finished | Jul 03 04:33:51 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-5844e996-5610-49ab-9ae2-94c559cfda43 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422883444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.422883444 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.3801960408 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 673394699 ps |
CPU time | 11.45 seconds |
Started | Jul 03 04:33:43 PM PDT 24 |
Finished | Jul 03 04:33:55 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-71e1d721-b705-45ab-b775-fb84809ce3cb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801960408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.3801960408 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.3837718155 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 28420240601 ps |
CPU time | 374.75 seconds |
Started | Jul 03 04:33:35 PM PDT 24 |
Finished | Jul 03 04:39:50 PM PDT 24 |
Peak memory | 368684 kb |
Host | smart-d7049601-c3c6-4838-be10-ce54844ee330 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837718155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3837718155 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.628472777 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 182365707 ps |
CPU time | 3.85 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:33:37 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-46215a35-1707-4ed2-961b-8c70c7918742 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628472777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.628472777 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4056777847 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 8971667030 ps |
CPU time | 234.73 seconds |
Started | Jul 03 04:33:32 PM PDT 24 |
Finished | Jul 03 04:37:27 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-319e7939-0472-4eaa-9cf0-f3e055d11791 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056777847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.4056777847 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2982971460 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 89457584 ps |
CPU time | 0.77 seconds |
Started | Jul 03 04:33:37 PM PDT 24 |
Finished | Jul 03 04:33:38 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-56f99439-3beb-49e5-9493-643bab060ddb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982971460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2982971460 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.3452907813 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 1863408217 ps |
CPU time | 463.98 seconds |
Started | Jul 03 04:33:39 PM PDT 24 |
Finished | Jul 03 04:41:24 PM PDT 24 |
Peak memory | 368136 kb |
Host | smart-a56d60cf-576e-49e1-8bad-5ef3f88516ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452907813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3452907813 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.960117846 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 265446184 ps |
CPU time | 13.99 seconds |
Started | Jul 03 04:33:35 PM PDT 24 |
Finished | Jul 03 04:33:49 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-1927b617-01f2-42e9-ac19-3fd54ff83dae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960117846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.960117846 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.2673481934 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 229674206521 ps |
CPU time | 3753.86 seconds |
Started | Jul 03 04:33:37 PM PDT 24 |
Finished | Jul 03 05:36:12 PM PDT 24 |
Peak memory | 384436 kb |
Host | smart-7ca1c3c1-c2d7-4447-80f1-b89ec284852d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673481934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.2673481934 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1941062556 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 1503081332 ps |
CPU time | 667.47 seconds |
Started | Jul 03 04:33:39 PM PDT 24 |
Finished | Jul 03 04:44:47 PM PDT 24 |
Peak memory | 366592 kb |
Host | smart-b087318e-6ee4-4b68-be50-65bf02d3046c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1941062556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1941062556 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1381427164 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 3775437184 ps |
CPU time | 362.41 seconds |
Started | Jul 03 04:33:33 PM PDT 24 |
Finished | Jul 03 04:39:35 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-bb23be7c-3b2c-4365-a040-0d84f551a88b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381427164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1381427164 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3237779990 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 75732524 ps |
CPU time | 11.87 seconds |
Started | Jul 03 04:33:39 PM PDT 24 |
Finished | Jul 03 04:33:51 PM PDT 24 |
Peak memory | 251568 kb |
Host | smart-f66fee0e-1d15-4c6b-8d76-a14d6dae173c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237779990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3237779990 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1747104248 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 5089097132 ps |
CPU time | 506.35 seconds |
Started | Jul 03 04:33:38 PM PDT 24 |
Finished | Jul 03 04:42:05 PM PDT 24 |
Peak memory | 369028 kb |
Host | smart-9a97d07b-5cfc-44db-a717-b1f623d6818f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747104248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.1747104248 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.1358588030 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 19491744 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:33:50 PM PDT 24 |
Finished | Jul 03 04:33:51 PM PDT 24 |
Peak memory | 202472 kb |
Host | smart-28d76396-0842-44bc-8068-551c66da534d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358588030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1358588030 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.811494946 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 8046525004 ps |
CPU time | 63.75 seconds |
Started | Jul 03 04:33:38 PM PDT 24 |
Finished | Jul 03 04:34:42 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-cc1307ef-a251-405e-b9b8-35de91a6c53c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811494946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 811494946 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.1194589106 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 23827194555 ps |
CPU time | 1138.55 seconds |
Started | Jul 03 04:33:40 PM PDT 24 |
Finished | Jul 03 04:52:39 PM PDT 24 |
Peak memory | 375288 kb |
Host | smart-f23c3bd0-a65c-40f7-a3ad-f69c5c55968d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194589106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.1194589106 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.2874816222 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 2156992752 ps |
CPU time | 7.33 seconds |
Started | Jul 03 04:33:40 PM PDT 24 |
Finished | Jul 03 04:33:48 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-db60adbb-0028-4fc6-8b5e-3d33a92a3c21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874816222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.2874816222 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.2182574052 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 87930343 ps |
CPU time | 37.4 seconds |
Started | Jul 03 04:33:48 PM PDT 24 |
Finished | Jul 03 04:34:26 PM PDT 24 |
Peak memory | 288784 kb |
Host | smart-fb3130ab-aa78-4c14-95f8-a9ba920eb67e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182574052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.2182574052 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4134119282 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 239845180 ps |
CPU time | 4.84 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:33:47 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-9eb24af5-aff5-4c15-82e7-f45add135b1f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134119282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.4134119282 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.3986757069 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 75328339 ps |
CPU time | 4.7 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:33:47 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-71f38372-f4e3-4c3d-b5c7-e98dbfed50e2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986757069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.3986757069 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.9355975 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 61406633984 ps |
CPU time | 919.57 seconds |
Started | Jul 03 04:33:39 PM PDT 24 |
Finished | Jul 03 04:48:59 PM PDT 24 |
Peak memory | 372604 kb |
Host | smart-f97b2e4a-b152-4857-be05-070ee9942dd0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9355975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple _keys.9355975 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.1539205145 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 1109041005 ps |
CPU time | 14.68 seconds |
Started | Jul 03 04:33:37 PM PDT 24 |
Finished | Jul 03 04:33:51 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-de3a033d-098a-4acc-b77e-b91173769710 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539205145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.1539205145 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1655101843 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 12267027367 ps |
CPU time | 229.72 seconds |
Started | Jul 03 04:33:39 PM PDT 24 |
Finished | Jul 03 04:37:29 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-63fa2cfc-2e02-4b1d-8e9e-2cb29bd34a3b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655101843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.1655101843 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.4143822697 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 32498719 ps |
CPU time | 0.81 seconds |
Started | Jul 03 04:33:55 PM PDT 24 |
Finished | Jul 03 04:33:56 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-5d6f4e34-b6cc-4963-9544-b875e148dce9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143822697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4143822697 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.2728188913 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 400540346 ps |
CPU time | 108.75 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:35:31 PM PDT 24 |
Peak memory | 324756 kb |
Host | smart-f043a1ed-64ff-4524-b997-9b1dbe60881e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728188913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2728188913 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.1802097274 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 572880907 ps |
CPU time | 9.24 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:33:51 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-e14f5922-fa37-48e7-8c4b-57b26b354b31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802097274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1802097274 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.522302230 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 48824795300 ps |
CPU time | 2232.22 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 05:11:05 PM PDT 24 |
Peak memory | 383340 kb |
Host | smart-b27bdc86-f5db-420c-942d-48133dca003c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522302230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_stress_all.522302230 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3074166407 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 640180361 ps |
CPU time | 19.15 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:34:01 PM PDT 24 |
Peak memory | 212560 kb |
Host | smart-6f041dab-694a-4eac-9c9d-2666b5d49065 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3074166407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3074166407 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3288053739 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 10770528769 ps |
CPU time | 280.05 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:38:32 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-a02914d7-1ee8-4ed9-ae47-40388ee15e5b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288053739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.3288053739 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2100220890 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 607623196 ps |
CPU time | 129.43 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:35:52 PM PDT 24 |
Peak memory | 369428 kb |
Host | smart-72683ce7-146e-45cc-a85a-ffa734521a11 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100220890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2100220890 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.410841604 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 10604587488 ps |
CPU time | 864.71 seconds |
Started | Jul 03 04:33:44 PM PDT 24 |
Finished | Jul 03 04:48:09 PM PDT 24 |
Peak memory | 374672 kb |
Host | smart-459a9e3e-4d3d-464a-9f06-0e75e40ad722 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410841604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sram_ctrl_access_during_key_req.410841604 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.939373012 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 32194426 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:34:07 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-c5b6d6a1-9d1c-4a92-83ef-399e7c3893de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939373012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.939373012 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3061186197 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 43867099463 ps |
CPU time | 51.25 seconds |
Started | Jul 03 04:33:49 PM PDT 24 |
Finished | Jul 03 04:34:40 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-a8290a54-c8fb-4374-94c2-ee333a41e3b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061186197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3061186197 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.1586504970 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 10009587263 ps |
CPU time | 568.19 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:43:21 PM PDT 24 |
Peak memory | 368028 kb |
Host | smart-f86dfd08-b602-46c3-b0c6-30cb668178ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586504970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.1586504970 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.1596514138 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 109947443 ps |
CPU time | 1.53 seconds |
Started | Jul 03 04:33:41 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-7cf8491a-554c-42c7-97af-7fe210eeca79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596514138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.1596514138 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.3240532817 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 232221246 ps |
CPU time | 7.45 seconds |
Started | Jul 03 04:33:44 PM PDT 24 |
Finished | Jul 03 04:33:52 PM PDT 24 |
Peak memory | 240360 kb |
Host | smart-42cb32e3-c1ba-4250-a33d-d7d047503557 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240532817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.3240532817 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.421025440 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 402189451 ps |
CPU time | 3.07 seconds |
Started | Jul 03 04:34:02 PM PDT 24 |
Finished | Jul 03 04:34:05 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-682fd0cf-6a0d-4711-b24d-f90216d1bc30 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421025440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_mem_partial_access.421025440 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.4289097805 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 137398787 ps |
CPU time | 9.01 seconds |
Started | Jul 03 04:33:46 PM PDT 24 |
Finished | Jul 03 04:33:55 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-610a6340-99b2-4996-9163-314794b492d3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289097805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.4289097805 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.1519082092 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 36382100787 ps |
CPU time | 748.65 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:46:11 PM PDT 24 |
Peak memory | 371760 kb |
Host | smart-44418489-d00d-4616-b3bc-480f0956f15c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519082092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.1519082092 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.3823244781 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 792042060 ps |
CPU time | 7.18 seconds |
Started | Jul 03 04:33:44 PM PDT 24 |
Finished | Jul 03 04:33:52 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-cfe5c488-e251-4a6a-973e-bbffbb942a5f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823244781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.3823244781 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2677672632 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 14646717012 ps |
CPU time | 265.03 seconds |
Started | Jul 03 04:33:43 PM PDT 24 |
Finished | Jul 03 04:38:09 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-979a6eec-4bfd-44fc-b006-29566dae309c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677672632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.2677672632 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.1031962830 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 40692406 ps |
CPU time | 0.82 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:33:43 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-3f8eae8b-b97e-44aa-bd1e-1ef98407a3fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031962830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1031962830 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.297613794 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 7301534224 ps |
CPU time | 1376.88 seconds |
Started | Jul 03 04:33:40 PM PDT 24 |
Finished | Jul 03 04:56:37 PM PDT 24 |
Peak memory | 375028 kb |
Host | smart-52bf8a23-44df-4faf-9297-3bae7a4e24b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297613794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.297613794 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.41269335 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 338544107 ps |
CPU time | 6.16 seconds |
Started | Jul 03 04:33:45 PM PDT 24 |
Finished | Jul 03 04:33:52 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-ca460e07-a3a4-4c3c-81fa-f591d331f0f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.41269335 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.4132397492 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 32414521073 ps |
CPU time | 1744.77 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 05:02:56 PM PDT 24 |
Peak memory | 375696 kb |
Host | smart-aa3335eb-6b8c-46d8-9700-0adc1eb44e99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132397492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.4132397492 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3730314740 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 2554881749 ps |
CPU time | 22.92 seconds |
Started | Jul 03 04:33:43 PM PDT 24 |
Finished | Jul 03 04:34:06 PM PDT 24 |
Peak memory | 212288 kb |
Host | smart-f72caabf-5b6b-4231-ab59-c6ad7f58ccdc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3730314740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3730314740 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1147892861 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 6191202718 ps |
CPU time | 291.41 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:38:34 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-f187d76b-0932-4038-b3d6-3bfc9665dedc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147892861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1147892861 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.715952037 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 393015270 ps |
CPU time | 17.43 seconds |
Started | Jul 03 04:33:44 PM PDT 24 |
Finished | Jul 03 04:34:02 PM PDT 24 |
Peak memory | 274628 kb |
Host | smart-13a6d69d-e89d-4734-995e-7838e8621e39 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715952037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.715952037 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.854647459 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 26093302483 ps |
CPU time | 1271.74 seconds |
Started | Jul 03 04:33:49 PM PDT 24 |
Finished | Jul 03 04:55:01 PM PDT 24 |
Peak memory | 372616 kb |
Host | smart-b0920b26-7d78-465d-8fb1-61814e93cd21 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854647459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sram_ctrl_access_during_key_req.854647459 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.2677822851 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 16389889 ps |
CPU time | 0.65 seconds |
Started | Jul 03 04:33:54 PM PDT 24 |
Finished | Jul 03 04:33:55 PM PDT 24 |
Peak memory | 202280 kb |
Host | smart-926e855c-5647-4c7c-bdaf-7e1f0adc319c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677822851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2677822851 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.3597654595 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 796261370 ps |
CPU time | 26.1 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:34:25 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-e6bf9efe-0191-4415-8920-485c1441d603 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597654595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .3597654595 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.3285175296 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 3043791818 ps |
CPU time | 989.17 seconds |
Started | Jul 03 04:33:49 PM PDT 24 |
Finished | Jul 03 04:50:19 PM PDT 24 |
Peak memory | 374396 kb |
Host | smart-d51ae79d-4b1b-401c-83ae-025d3507e831 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285175296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3285175296 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.1088517323 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 440513460 ps |
CPU time | 6.12 seconds |
Started | Jul 03 04:33:46 PM PDT 24 |
Finished | Jul 03 04:33:53 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-40b0cc61-c5ba-4e7a-a6c7-4ba7327c8aff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088517323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.1088517323 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.2008982980 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 138958199 ps |
CPU time | 134.23 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 04:36:06 PM PDT 24 |
Peak memory | 369412 kb |
Host | smart-017a4ff8-c29b-4e72-b5f1-ba31d65b9d70 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008982980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.2008982980 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3894832251 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 225316806 ps |
CPU time | 2.81 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:33:55 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-ce6b7917-be26-4482-97bd-62ca5024c220 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894832251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.3894832251 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.3309010061 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 298866831 ps |
CPU time | 5.84 seconds |
Started | Jul 03 04:33:47 PM PDT 24 |
Finished | Jul 03 04:33:53 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-cdef17df-85e3-4878-b957-2d825bb2f91f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309010061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3309010061 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2643792713 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 4063542161 ps |
CPU time | 1044.44 seconds |
Started | Jul 03 04:34:01 PM PDT 24 |
Finished | Jul 03 04:51:26 PM PDT 24 |
Peak memory | 373184 kb |
Host | smart-f01787dc-71c6-4a6a-b31f-9a34a44d0424 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643792713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2643792713 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.2014709734 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 2727976341 ps |
CPU time | 13.14 seconds |
Started | Jul 03 04:33:43 PM PDT 24 |
Finished | Jul 03 04:33:57 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-7949add6-7310-453d-a447-35c7dffed1e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014709734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.2014709734 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4186282860 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 92914491321 ps |
CPU time | 372.24 seconds |
Started | Jul 03 04:33:47 PM PDT 24 |
Finished | Jul 03 04:40:00 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-c097b019-7dfd-43be-94ae-191cc50c1f64 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186282860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.4186282860 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.359797023 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 114556329 ps |
CPU time | 0.79 seconds |
Started | Jul 03 04:33:46 PM PDT 24 |
Finished | Jul 03 04:33:47 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-2c1a8fb8-a5ef-4a2a-8283-158dfd1ac4d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359797023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.359797023 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.976954848 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 911782252 ps |
CPU time | 347.12 seconds |
Started | Jul 03 04:33:50 PM PDT 24 |
Finished | Jul 03 04:39:37 PM PDT 24 |
Peak memory | 346628 kb |
Host | smart-58ea0f33-72a3-46ad-94bf-3dafcc8c5d0c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976954848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.976954848 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.819177585 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 642212178 ps |
CPU time | 145.32 seconds |
Started | Jul 03 04:33:43 PM PDT 24 |
Finished | Jul 03 04:36:08 PM PDT 24 |
Peak memory | 366312 kb |
Host | smart-a9a0562c-0433-4eba-a2d4-2f3a0865ddac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819177585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.819177585 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.1988820165 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 20708160947 ps |
CPU time | 1072.64 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:51:46 PM PDT 24 |
Peak memory | 375172 kb |
Host | smart-e84850a1-e172-49a4-9a08-c3ebec03a9c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988820165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.1988820165 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1884793666 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 691331100 ps |
CPU time | 290.44 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 04:38:43 PM PDT 24 |
Peak memory | 378536 kb |
Host | smart-28ee20a9-58a6-49ee-ade8-fd7f312fce5b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1884793666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1884793666 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1525954382 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 26010614926 ps |
CPU time | 202.91 seconds |
Started | Jul 03 04:33:42 PM PDT 24 |
Finished | Jul 03 04:37:05 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-c5c99223-e1b8-4414-8f07-29302c2c96ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525954382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1525954382 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.894428317 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 420553219 ps |
CPU time | 17.36 seconds |
Started | Jul 03 04:33:53 PM PDT 24 |
Finished | Jul 03 04:34:11 PM PDT 24 |
Peak memory | 276424 kb |
Host | smart-ab70ae8a-ebdf-4df0-b2e9-6213138c70f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894428317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.894428317 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3858828569 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 5665341559 ps |
CPU time | 1571.03 seconds |
Started | Jul 03 04:33:49 PM PDT 24 |
Finished | Jul 03 05:00:00 PM PDT 24 |
Peak memory | 372604 kb |
Host | smart-5a94ad8c-8d8d-4b8c-bb0e-01910a1ef217 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858828569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3858828569 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.4221356962 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 45557397 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:33:54 PM PDT 24 |
Finished | Jul 03 04:33:55 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-dd41eba6-d877-4deb-a18a-377168040ffb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221356962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.4221356962 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.2549030501 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 4612855997 ps |
CPU time | 53.08 seconds |
Started | Jul 03 04:33:45 PM PDT 24 |
Finished | Jul 03 04:34:38 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-ccc66a53-8c0f-4fb4-bce2-f59326b5703a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549030501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2549030501 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.1331324335 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 9726399365 ps |
CPU time | 920.5 seconds |
Started | Jul 03 04:33:48 PM PDT 24 |
Finished | Jul 03 04:49:09 PM PDT 24 |
Peak memory | 368508 kb |
Host | smart-865d3edb-3a2d-4cb8-919e-c48fb9ff6758 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331324335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.1331324335 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2104582277 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1838371887 ps |
CPU time | 3.58 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:33:56 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-d58494c3-3cc2-4d8d-9838-af9db98ac47d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104582277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2104582277 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.3649016781 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 114920693 ps |
CPU time | 12.18 seconds |
Started | Jul 03 04:33:46 PM PDT 24 |
Finished | Jul 03 04:33:59 PM PDT 24 |
Peak memory | 257060 kb |
Host | smart-64cfd30b-a4dd-45bb-a622-433c3a4851ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649016781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.3649016781 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1928275048 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 3328073387 ps |
CPU time | 6.78 seconds |
Started | Jul 03 04:33:50 PM PDT 24 |
Finished | Jul 03 04:33:57 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-4cfb3926-693f-46a2-86bd-da33658772b4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928275048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1928275048 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.3346914698 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 1820955104 ps |
CPU time | 11.03 seconds |
Started | Jul 03 04:33:55 PM PDT 24 |
Finished | Jul 03 04:34:07 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-c5625bd0-ac0c-40cc-9d36-6ce05a01ba27 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346914698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3346914698 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.4256004588 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 75352973131 ps |
CPU time | 1133.73 seconds |
Started | Jul 03 04:33:50 PM PDT 24 |
Finished | Jul 03 04:52:44 PM PDT 24 |
Peak memory | 370576 kb |
Host | smart-d3eb3e3e-c3c1-4250-97a1-bdc66e5c590e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256004588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.4256004588 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.2071473122 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 601299299 ps |
CPU time | 15.95 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 04:34:08 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-bfd15a38-369c-4823-b2b1-449dc52b226f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071473122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.2071473122 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1375346384 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 5629919601 ps |
CPU time | 441.01 seconds |
Started | Jul 03 04:33:46 PM PDT 24 |
Finished | Jul 03 04:41:08 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-793d3959-7a45-4ff1-b008-5b626dbce2b9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375346384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1375346384 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.859680859 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 28176574 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:33:49 PM PDT 24 |
Finished | Jul 03 04:33:50 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-136e5a71-8c6c-4dc8-9a4f-c10f2925f943 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859680859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.859680859 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.3621944625 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 4413941920 ps |
CPU time | 308.7 seconds |
Started | Jul 03 04:33:47 PM PDT 24 |
Finished | Jul 03 04:38:56 PM PDT 24 |
Peak memory | 373716 kb |
Host | smart-99a0054e-5db3-4635-9eb0-4e65e6470e64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621944625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3621944625 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.4199440211 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 40370454 ps |
CPU time | 4.27 seconds |
Started | Jul 03 04:33:48 PM PDT 24 |
Finished | Jul 03 04:33:52 PM PDT 24 |
Peak memory | 223112 kb |
Host | smart-6c2c9250-764b-4ca2-85c9-c01a0d2b2a68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199440211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.4199440211 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.1271147480 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 194988108598 ps |
CPU time | 2233.34 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 05:11:05 PM PDT 24 |
Peak memory | 376200 kb |
Host | smart-dc0ed49e-7de1-4559-ba21-d8b0d3bc8270 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271147480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.1271147480 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2722386346 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 312234352 ps |
CPU time | 115.7 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:35:49 PM PDT 24 |
Peak memory | 327880 kb |
Host | smart-b847d2bd-b067-4a05-8daf-bbe9fe3a1f80 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2722386346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2722386346 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2039551678 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 10195040954 ps |
CPU time | 253.76 seconds |
Started | Jul 03 04:33:50 PM PDT 24 |
Finished | Jul 03 04:38:04 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-b2109daa-bc70-4913-8d66-bbce328e1b44 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039551678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.2039551678 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4140376122 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 394312277 ps |
CPU time | 36.22 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:34:29 PM PDT 24 |
Peak memory | 287612 kb |
Host | smart-2b45954e-a6c3-4532-b33f-4744c3bd0882 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140376122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.4140376122 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.4091327812 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 1778309561 ps |
CPU time | 539.75 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:42:52 PM PDT 24 |
Peak memory | 372500 kb |
Host | smart-b41ff3a9-af75-4c8b-9032-19bee4d2d183 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091327812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.4091327812 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.4026907438 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 21010819 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:33:57 PM PDT 24 |
Finished | Jul 03 04:33:58 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-151c5a3a-5efb-4e6d-8235-b5cb7b2980dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026907438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.4026907438 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.2995804841 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 8078649106 ps |
CPU time | 49.69 seconds |
Started | Jul 03 04:33:53 PM PDT 24 |
Finished | Jul 03 04:34:43 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-3b95e4b6-bb90-4581-a0e1-bdf0ca495091 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995804841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2995804841 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.7769898 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 12036888474 ps |
CPU time | 611.07 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 04:44:03 PM PDT 24 |
Peak memory | 370608 kb |
Host | smart-fdbcd65f-f25c-430f-850c-d301fd40538d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7769898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.7769898 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1278110017 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 505650909 ps |
CPU time | 5.59 seconds |
Started | Jul 03 04:33:55 PM PDT 24 |
Finished | Jul 03 04:34:01 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-51b66248-fa37-432a-8148-60d0660ac8df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278110017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1278110017 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.749008676 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 204566230 ps |
CPU time | 26.65 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:34:26 PM PDT 24 |
Peak memory | 300032 kb |
Host | smart-eda97a95-7558-4e63-b4d2-ee856f09b556 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749008676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_max_throughput.749008676 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4223516014 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 67613419 ps |
CPU time | 4.54 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:33:57 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-35a25f91-d9b1-4b0c-bcbf-e1c665041768 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223516014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.4223516014 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.1448230862 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 580222418 ps |
CPU time | 4.67 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:33:57 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-ec50bec0-cccd-4571-b007-0646ba9fefa9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448230862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.1448230862 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.4155027861 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 75970669755 ps |
CPU time | 915.73 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:49:16 PM PDT 24 |
Peak memory | 371764 kb |
Host | smart-16256cb5-563d-4260-8fbd-9cf7563a0d8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155027861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.4155027861 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.3261431394 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1047453594 ps |
CPU time | 12.76 seconds |
Started | Jul 03 04:33:51 PM PDT 24 |
Finished | Jul 03 04:34:05 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-6a0b6d0e-d73c-4b90-849d-856cd7996f2e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261431394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3261431394 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.603080029 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 5184912485 ps |
CPU time | 352.19 seconds |
Started | Jul 03 04:33:55 PM PDT 24 |
Finished | Jul 03 04:39:47 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-cb983863-b79d-4fa4-a2b9-b486f085bc68 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603080029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.603080029 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.2463471000 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 92182542 ps |
CPU time | 0.83 seconds |
Started | Jul 03 04:33:54 PM PDT 24 |
Finished | Jul 03 04:33:55 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-ecfceb76-9adb-4522-b9af-28b4a70a5504 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463471000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2463471000 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.2249823912 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 15039563216 ps |
CPU time | 1058.75 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:51:38 PM PDT 24 |
Peak memory | 374236 kb |
Host | smart-93841c71-75e9-4169-a7f2-efa6b1bf635d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249823912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2249823912 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.3396837935 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 3829523328 ps |
CPU time | 20.99 seconds |
Started | Jul 03 04:33:52 PM PDT 24 |
Finished | Jul 03 04:34:14 PM PDT 24 |
Peak memory | 263908 kb |
Host | smart-8939ba46-e38e-402d-9494-b7f2bfc93cb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396837935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3396837935 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.2907946426 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 271169753713 ps |
CPU time | 3546.1 seconds |
Started | Jul 03 04:33:49 PM PDT 24 |
Finished | Jul 03 05:32:56 PM PDT 24 |
Peak memory | 376752 kb |
Host | smart-7a633c82-f8e4-4944-b3a4-3873068dd514 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907946426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.2907946426 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2924106705 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 2509032247 ps |
CPU time | 237.71 seconds |
Started | Jul 03 04:33:55 PM PDT 24 |
Finished | Jul 03 04:37:53 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-fbb5d28e-f8cc-443d-b9e0-b9355edca2dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924106705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2924106705 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1204045196 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 162453885 ps |
CPU time | 127.03 seconds |
Started | Jul 03 04:33:56 PM PDT 24 |
Finished | Jul 03 04:36:03 PM PDT 24 |
Peak memory | 369292 kb |
Host | smart-a83c8aa9-5891-409c-86e8-05df4a99202e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204045196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1204045196 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3344725887 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 2211777210 ps |
CPU time | 684.51 seconds |
Started | Jul 03 04:34:04 PM PDT 24 |
Finished | Jul 03 04:45:29 PM PDT 24 |
Peak memory | 366664 kb |
Host | smart-fd748d75-c977-4283-a6a1-ffd03fbbe8eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344725887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.3344725887 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1547584372 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 49948372 ps |
CPU time | 0.72 seconds |
Started | Jul 03 04:33:57 PM PDT 24 |
Finished | Jul 03 04:33:58 PM PDT 24 |
Peak memory | 202272 kb |
Host | smart-e0594585-f664-4dc7-be25-ab871cfc2e26 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547584372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1547584372 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.488270249 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 5372643148 ps |
CPU time | 73.3 seconds |
Started | Jul 03 04:33:56 PM PDT 24 |
Finished | Jul 03 04:35:10 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-4de6e7dc-ba58-465f-9ec3-a623b57e591f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488270249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection. 488270249 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.1347842411 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 4345364860 ps |
CPU time | 289.57 seconds |
Started | Jul 03 04:34:05 PM PDT 24 |
Finished | Jul 03 04:38:55 PM PDT 24 |
Peak memory | 367932 kb |
Host | smart-e4b1242d-b1e4-417d-8947-1ddcd41db419 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347842411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1347842411 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.2566135900 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 1034059092 ps |
CPU time | 6 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:34:06 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-7370198e-0d13-4fef-a7be-5dc8060134a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566135900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.2566135900 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.3337159753 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 236941277 ps |
CPU time | 90.79 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:35:37 PM PDT 24 |
Peak memory | 353076 kb |
Host | smart-14f3587d-dabe-4199-9f4a-b85893936c5e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337159753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3337159753 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.78859401 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 105600391 ps |
CPU time | 3.47 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:34:04 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-729d7cb6-d53d-4dcc-9c4b-fdb24b0d0040 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78859401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_mem_partial_access.78859401 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.1461431475 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 123931695 ps |
CPU time | 5.21 seconds |
Started | Jul 03 04:34:03 PM PDT 24 |
Finished | Jul 03 04:34:08 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-a97220c1-ad9f-4bbc-8865-e30220f10c19 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461431475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1461431475 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.2908829720 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 14801583687 ps |
CPU time | 700.7 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:45:40 PM PDT 24 |
Peak memory | 375696 kb |
Host | smart-7d62b3f9-c539-4f6c-bd53-a16559428c83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908829720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.2908829720 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3242414010 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 419312277 ps |
CPU time | 5.59 seconds |
Started | Jul 03 04:33:57 PM PDT 24 |
Finished | Jul 03 04:34:03 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-1298da20-e961-4544-8d5a-15d868010559 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242414010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3242414010 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3449752641 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 26839888945 ps |
CPU time | 314.72 seconds |
Started | Jul 03 04:33:58 PM PDT 24 |
Finished | Jul 03 04:39:13 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-e105f1ad-2038-4ce4-a0cc-02a94dc2b1b5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449752641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.3449752641 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.577425773 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 29839087 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:33:58 PM PDT 24 |
Finished | Jul 03 04:33:59 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-976a405e-54f7-47d6-9522-6ffa004461de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577425773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.577425773 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.1436312759 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 38275620015 ps |
CPU time | 1446.66 seconds |
Started | Jul 03 04:34:01 PM PDT 24 |
Finished | Jul 03 04:58:08 PM PDT 24 |
Peak memory | 373656 kb |
Host | smart-b1885842-1864-4198-8b51-465c7608b937 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436312759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1436312759 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.1773741218 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 506049614 ps |
CPU time | 5.59 seconds |
Started | Jul 03 04:33:56 PM PDT 24 |
Finished | Jul 03 04:34:02 PM PDT 24 |
Peak memory | 222816 kb |
Host | smart-39502c9c-b6f5-4a6f-8fd8-eceb94bac651 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773741218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1773741218 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.271828175 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 475832483029 ps |
CPU time | 4775.18 seconds |
Started | Jul 03 04:33:58 PM PDT 24 |
Finished | Jul 03 05:53:34 PM PDT 24 |
Peak memory | 378472 kb |
Host | smart-f6b78e47-36a8-46ab-8b83-714db8a6e943 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271828175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_stress_all.271828175 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.818781617 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 896574218 ps |
CPU time | 56.18 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:34:56 PM PDT 24 |
Peak memory | 301496 kb |
Host | smart-984abd8d-f23f-4355-a743-0c8e88e34b6c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=818781617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.818781617 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.4213656551 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 7819988004 ps |
CPU time | 196.39 seconds |
Started | Jul 03 04:33:57 PM PDT 24 |
Finished | Jul 03 04:37:14 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-1e727075-da06-4f94-9c7c-9415e80312b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213656551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.4213656551 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3481240984 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 55154865 ps |
CPU time | 1.51 seconds |
Started | Jul 03 04:33:57 PM PDT 24 |
Finished | Jul 03 04:33:59 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-f15b5f82-d962-4c4a-9310-2aa84ec6cf7d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481240984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3481240984 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2566383650 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 12372159741 ps |
CPU time | 1120.25 seconds |
Started | Jul 03 04:34:05 PM PDT 24 |
Finished | Jul 03 04:52:46 PM PDT 24 |
Peak memory | 374704 kb |
Host | smart-f70c33d7-cf94-44ed-b47d-a400df4af5bd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566383650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.2566383650 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.4189646145 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 14867585 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:34:03 PM PDT 24 |
Finished | Jul 03 04:34:04 PM PDT 24 |
Peak memory | 202564 kb |
Host | smart-d12030e7-de21-4d17-bf1f-379007007021 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189646145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.4189646145 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.2597215722 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 21981514460 ps |
CPU time | 74.7 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:35:14 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-a9f94c2d-9648-466b-8c57-555a061a3144 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597215722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2597215722 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.3109946852 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 16114178608 ps |
CPU time | 721.83 seconds |
Started | Jul 03 04:34:01 PM PDT 24 |
Finished | Jul 03 04:46:04 PM PDT 24 |
Peak memory | 361368 kb |
Host | smart-91b9d191-b905-47c0-b657-e5e764ade3ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109946852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.3109946852 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.492348969 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 2838943044 ps |
CPU time | 9.9 seconds |
Started | Jul 03 04:34:02 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-9db3e7b4-b18f-44e0-aada-47523cc559aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492348969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc alation.492348969 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2223306460 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 300452778 ps |
CPU time | 15.44 seconds |
Started | Jul 03 04:34:05 PM PDT 24 |
Finished | Jul 03 04:34:21 PM PDT 24 |
Peak memory | 263064 kb |
Host | smart-183c63c2-e82e-4828-865c-57ab7b387cc5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223306460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2223306460 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1118016977 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 298428319 ps |
CPU time | 2.88 seconds |
Started | Jul 03 04:34:01 PM PDT 24 |
Finished | Jul 03 04:34:05 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-e9dd4426-fafa-4714-a35f-5190313e6a45 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118016977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.1118016977 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.1506821139 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 147354673 ps |
CPU time | 4.63 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:34:05 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-abcbda97-dc43-4236-8892-da74af75ad7f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506821139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.1506821139 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.1711522673 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 39236579332 ps |
CPU time | 653.71 seconds |
Started | Jul 03 04:33:58 PM PDT 24 |
Finished | Jul 03 04:44:52 PM PDT 24 |
Peak memory | 375612 kb |
Host | smart-60d208a6-2be8-4d36-b4c9-1dd243bac02a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711522673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1711522673 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.1837210987 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 265356051 ps |
CPU time | 4.88 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:34:05 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-7a9df0a2-43c3-484d-9b1f-cd09a7aa3f95 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837210987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1837210987 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4054196394 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 6924045631 ps |
CPU time | 167.94 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:36:49 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-f4cbf23b-2f28-41b5-906f-1f9a114a5a3c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054196394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.4054196394 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.112850812 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 34035221 ps |
CPU time | 0.79 seconds |
Started | Jul 03 04:34:02 PM PDT 24 |
Finished | Jul 03 04:34:03 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-62e8a154-9bb8-49a8-8831-61613ab7dd8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112850812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.112850812 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.1070564433 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 77068569784 ps |
CPU time | 844.35 seconds |
Started | Jul 03 04:34:08 PM PDT 24 |
Finished | Jul 03 04:48:13 PM PDT 24 |
Peak memory | 375428 kb |
Host | smart-9170bc03-f261-456a-989b-5314874f3389 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070564433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1070564433 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.325135620 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 708049377 ps |
CPU time | 11.74 seconds |
Started | Jul 03 04:33:57 PM PDT 24 |
Finished | Jul 03 04:34:09 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-82bc3b75-2de1-481a-a617-90f83f26bdfd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325135620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.325135620 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.587354903 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 11213596132 ps |
CPU time | 545.26 seconds |
Started | Jul 03 04:34:04 PM PDT 24 |
Finished | Jul 03 04:43:10 PM PDT 24 |
Peak memory | 375728 kb |
Host | smart-f5521a98-6ac1-4b5b-b746-a972889deb4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587354903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.587354903 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3721553475 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 7385044116 ps |
CPU time | 157.09 seconds |
Started | Jul 03 04:34:08 PM PDT 24 |
Finished | Jul 03 04:36:45 PM PDT 24 |
Peak memory | 335732 kb |
Host | smart-61bf6185-84ff-408c-be7f-a7c097ce589e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3721553475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3721553475 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2337564001 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 1861581969 ps |
CPU time | 168.52 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:36:49 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-271bbd8e-0a60-417e-95f7-842d0e29234c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337564001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.2337564001 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.653919632 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 68110994 ps |
CPU time | 0.87 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:34:07 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-9907ffa9-8326-4a1f-9005-0816c59fad18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653919632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.653919632 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1359890512 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 3214233056 ps |
CPU time | 696.57 seconds |
Started | Jul 03 04:34:08 PM PDT 24 |
Finished | Jul 03 04:45:45 PM PDT 24 |
Peak memory | 374252 kb |
Host | smart-4bc67522-06ca-4bad-87d0-fbffe34188dc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359890512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.1359890512 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.1106593013 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 13973392 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:34:08 PM PDT 24 |
Finished | Jul 03 04:34:09 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-7e33192e-897d-4f97-897a-0f8958c9fb9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106593013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1106593013 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.323634887 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 484515681 ps |
CPU time | 30.63 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:34:37 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-c5d84933-4fc6-4e36-808e-86ee91119f53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323634887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection. 323634887 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.919764251 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 4030072174 ps |
CPU time | 1550.3 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:59:57 PM PDT 24 |
Peak memory | 372568 kb |
Host | smart-cbfb8862-b6ee-4037-848d-18c9eae15383 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919764251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl e.919764251 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.2586014658 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 430844234 ps |
CPU time | 5.47 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-bd94ff9b-5bd1-4d36-9f7d-140ad72964ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586014658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.2586014658 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.162715980 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 449609209 ps |
CPU time | 109.1 seconds |
Started | Jul 03 04:33:59 PM PDT 24 |
Finished | Jul 03 04:35:49 PM PDT 24 |
Peak memory | 346116 kb |
Host | smart-a495ef64-8f4e-4005-a18a-066255a3795b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162715980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.sram_ctrl_max_throughput.162715980 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.480303230 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 194335219 ps |
CPU time | 3.38 seconds |
Started | Jul 03 04:34:08 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-02e3745e-1148-4090-b746-042a1906129e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480303230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_mem_partial_access.480303230 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.1854062376 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 553502875 ps |
CPU time | 9.07 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:34:17 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-5b47c380-3cfa-4fc4-bb78-d4b495863452 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854062376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1854062376 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.1086941677 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2340443317 ps |
CPU time | 1072.21 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:51:59 PM PDT 24 |
Peak memory | 373404 kb |
Host | smart-b2719e70-00f5-4070-8db7-2ab480c94676 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086941677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.1086941677 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1691246296 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 5126237450 ps |
CPU time | 115.83 seconds |
Started | Jul 03 04:34:05 PM PDT 24 |
Finished | Jul 03 04:36:02 PM PDT 24 |
Peak memory | 362328 kb |
Host | smart-5a70e5c8-457c-40de-81f9-c8c5b5b7e6fd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691246296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1691246296 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2707322681 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 8879545309 ps |
CPU time | 223.85 seconds |
Started | Jul 03 04:34:00 PM PDT 24 |
Finished | Jul 03 04:37:45 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-64ee40b5-cbd2-45f7-8258-5d6469e3943b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707322681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.2707322681 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.3543269814 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 48799115 ps |
CPU time | 0.82 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:34:09 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-b66eb38c-e52a-4762-8b23-5a2898ce611f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543269814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3543269814 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.322387682 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 4779768970 ps |
CPU time | 564.41 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:43:33 PM PDT 24 |
Peak memory | 374240 kb |
Host | smart-c3b7543f-4126-44ec-bb80-044b5e0714b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322387682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.322387682 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.664065644 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 875994364 ps |
CPU time | 13.56 seconds |
Started | Jul 03 04:34:03 PM PDT 24 |
Finished | Jul 03 04:34:17 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-71e6d28c-9867-41c0-b40c-b3ff443f880f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664065644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.664065644 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.1185108093 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 89300122585 ps |
CPU time | 4501.1 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 05:49:10 PM PDT 24 |
Peak memory | 376040 kb |
Host | smart-8174f694-ac2a-4208-9700-6b80f22d533d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185108093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.1185108093 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3153130969 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 717598086 ps |
CPU time | 326.61 seconds |
Started | Jul 03 04:34:09 PM PDT 24 |
Finished | Jul 03 04:39:36 PM PDT 24 |
Peak memory | 376424 kb |
Host | smart-aaacfb28-bf4f-4618-8682-f584b258889d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3153130969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3153130969 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.486266526 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 1667511947 ps |
CPU time | 153.98 seconds |
Started | Jul 03 04:34:05 PM PDT 24 |
Finished | Jul 03 04:36:39 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-652f5ddd-c439-4fe2-adeb-3fd06142fb99 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486266526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_stress_pipeline.486266526 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3915337057 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 474953290 ps |
CPU time | 5.27 seconds |
Started | Jul 03 04:34:02 PM PDT 24 |
Finished | Jul 03 04:34:07 PM PDT 24 |
Peak memory | 227360 kb |
Host | smart-287630ed-fbb3-4dd1-bd27-24d715c22b99 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915337057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3915337057 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4180331836 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 2275331958 ps |
CPU time | 1053.84 seconds |
Started | Jul 03 04:34:06 PM PDT 24 |
Finished | Jul 03 04:51:41 PM PDT 24 |
Peak memory | 374032 kb |
Host | smart-4e5ac83a-201e-48de-9346-f2e42f4f5d05 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180331836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.4180331836 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.1163081729 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 19847319 ps |
CPU time | 0.61 seconds |
Started | Jul 03 04:34:17 PM PDT 24 |
Finished | Jul 03 04:34:18 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-37a69e77-8ba9-435a-aa05-c930b5a08184 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163081729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.1163081729 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.392116201 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 2896821983 ps |
CPU time | 65.85 seconds |
Started | Jul 03 04:34:13 PM PDT 24 |
Finished | Jul 03 04:35:19 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-d7e3faf3-1e00-47ac-9578-e0c381f8914a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392116201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection. 392116201 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.2575665017 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 5594148417 ps |
CPU time | 707.73 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:45:55 PM PDT 24 |
Peak memory | 361164 kb |
Host | smart-db8c6c21-f9f2-44bb-8203-6a2f165f13ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575665017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2575665017 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1079815275 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 220543181 ps |
CPU time | 1.98 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:34:09 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-8d06977e-20fd-4504-a89a-2912ee823719 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079815275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1079815275 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.520047435 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 517267674 ps |
CPU time | 141.26 seconds |
Started | Jul 03 04:34:09 PM PDT 24 |
Finished | Jul 03 04:36:30 PM PDT 24 |
Peak memory | 366272 kb |
Host | smart-bd32898d-d0ef-416a-bb6a-94965946256c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520047435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.520047435 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1230145151 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 584583138 ps |
CPU time | 3.18 seconds |
Started | Jul 03 04:34:08 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-bf1d7801-eb5f-47a4-99a0-a256cb2ca2d5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230145151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.1230145151 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.3507229764 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 139394199 ps |
CPU time | 8.28 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:34:16 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-0d919477-7895-4289-a580-e8f48816e5b6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507229764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3507229764 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.3212412921 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 16169001768 ps |
CPU time | 1447.71 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:58:16 PM PDT 24 |
Peak memory | 375640 kb |
Host | smart-17204ab5-4763-4e66-9be5-a2757e81e0ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212412921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.3212412921 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.2029869884 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 1514515324 ps |
CPU time | 14.52 seconds |
Started | Jul 03 04:34:12 PM PDT 24 |
Finished | Jul 03 04:34:27 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-82af63e9-22f6-4e2b-9672-1fc8d2728347 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029869884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.2029869884 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1202843830 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 12466437722 ps |
CPU time | 330.45 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:39:39 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-a6da10d8-9486-4cce-8e3b-11134c7966f8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202843830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1202843830 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.3777919260 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 45363450 ps |
CPU time | 0.77 seconds |
Started | Jul 03 04:34:09 PM PDT 24 |
Finished | Jul 03 04:34:10 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-7d46f7b4-cad7-4053-90e1-d32827e17625 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777919260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3777919260 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.2101656512 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 87570041048 ps |
CPU time | 1314.77 seconds |
Started | Jul 03 04:34:07 PM PDT 24 |
Finished | Jul 03 04:56:03 PM PDT 24 |
Peak memory | 368620 kb |
Host | smart-80690239-b9b7-45ab-9d41-41a82998227e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101656512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2101656512 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.609667812 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 235806590 ps |
CPU time | 15.3 seconds |
Started | Jul 03 04:34:12 PM PDT 24 |
Finished | Jul 03 04:34:27 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-09e79164-8ab6-49b4-9aeb-58834c9b6566 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609667812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.609667812 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.32263595 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 405862113170 ps |
CPU time | 7536.29 seconds |
Started | Jul 03 04:34:12 PM PDT 24 |
Finished | Jul 03 06:39:49 PM PDT 24 |
Peak memory | 383776 kb |
Host | smart-fca31556-1237-4a19-83f7-084363b14430 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32263595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.sram_ctrl_stress_all.32263595 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3285874106 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 5472705491 ps |
CPU time | 27.7 seconds |
Started | Jul 03 04:34:14 PM PDT 24 |
Finished | Jul 03 04:34:42 PM PDT 24 |
Peak memory | 211256 kb |
Host | smart-74814290-f0de-44bc-86be-fae48cec88c9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3285874106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3285874106 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.503232107 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 3742405689 ps |
CPU time | 183.7 seconds |
Started | Jul 03 04:34:10 PM PDT 24 |
Finished | Jul 03 04:37:14 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-9bdc5a55-bc87-44e6-9256-3149b5ece2ed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503232107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_stress_pipeline.503232107 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1899442879 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 54907882 ps |
CPU time | 3.59 seconds |
Started | Jul 03 04:34:09 PM PDT 24 |
Finished | Jul 03 04:34:12 PM PDT 24 |
Peak memory | 219220 kb |
Host | smart-87337c8a-664a-445a-8e15-5eeba02babd2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899442879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1899442879 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3022918395 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 6969981596 ps |
CPU time | 1104.93 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:50:46 PM PDT 24 |
Peak memory | 373672 kb |
Host | smart-c065e63a-2e74-4a55-a1dc-349e2ecc9cee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022918395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3022918395 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.1125126625 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 13726886 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:28 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-4de69be9-e63a-4d29-bc9f-3fb7029b41bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125126625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1125126625 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.2591508475 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 1325255794 ps |
CPU time | 44.02 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-92b28ffd-d463-47f8-a77c-841557e6fea6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591508475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 2591508475 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.2630545603 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 780720608 ps |
CPU time | 112.75 seconds |
Started | Jul 03 04:32:23 PM PDT 24 |
Finished | Jul 03 04:34:16 PM PDT 24 |
Peak memory | 359772 kb |
Host | smart-c40a3229-eb35-400c-ab3e-765adce420f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630545603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.2630545603 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.3744004318 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 167522932 ps |
CPU time | 2.47 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:32:22 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-6b41b7ac-1e08-4743-a201-e70ac212b5c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744004318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.3744004318 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.3410322568 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 87835118 ps |
CPU time | 2.98 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:32:17 PM PDT 24 |
Peak memory | 219116 kb |
Host | smart-e8de201d-b99c-40d4-9f23-d6bb5eef0ceb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410322568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.3410322568 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1209447846 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 249496332 ps |
CPU time | 4.22 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:34 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-aac089c5-c538-43cf-8b51-0ddf1758d223 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209447846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.1209447846 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.1728572881 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 519288774 ps |
CPU time | 10.4 seconds |
Started | Jul 03 04:32:09 PM PDT 24 |
Finished | Jul 03 04:32:20 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-ba74a246-5b13-495d-8ab5-3e3052a458bd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728572881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.1728572881 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.3893290765 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 9564407537 ps |
CPU time | 697.96 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:44:08 PM PDT 24 |
Peak memory | 372648 kb |
Host | smart-3a6cda65-0276-48fd-8a28-6383809dba98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893290765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.3893290765 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.11263630 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 248647960 ps |
CPU time | 60.79 seconds |
Started | Jul 03 04:32:10 PM PDT 24 |
Finished | Jul 03 04:33:11 PM PDT 24 |
Peak memory | 319892 kb |
Host | smart-dc6d5d19-a8e6-4d16-b1de-b28911cd09ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11263630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sra m_ctrl_partial_access.11263630 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1503824620 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 3539486212 ps |
CPU time | 247.66 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:36:27 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-d489af07-828f-46ae-92d2-1948a8dcecea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503824620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.1503824620 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2524549898 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 27245826 ps |
CPU time | 0.79 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:29 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-ef152c00-cf3f-4dd8-9690-7e83791cafe5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524549898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2524549898 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2306748059 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 11226536070 ps |
CPU time | 273.88 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:36:59 PM PDT 24 |
Peak memory | 355972 kb |
Host | smart-d0fd549e-bf50-4dcd-b173-be767efbfbbc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306748059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2306748059 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.3888697520 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 661379957 ps |
CPU time | 160.76 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:35:10 PM PDT 24 |
Peak memory | 368428 kb |
Host | smart-c9df55ac-0e72-42ba-be05-931f58bbae39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888697520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3888697520 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.2907879417 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 28584790405 ps |
CPU time | 1972.33 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 05:05:17 PM PDT 24 |
Peak memory | 374640 kb |
Host | smart-bbbb3d8a-49ff-4fb9-96a4-352d47d39c18 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907879417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.2907879417 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.601226691 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 3186132601 ps |
CPU time | 512.96 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:40:56 PM PDT 24 |
Peak memory | 378444 kb |
Host | smart-bf438c47-8b76-464c-8117-fdbba74a512f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=601226691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.601226691 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2578036470 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 4815480186 ps |
CPU time | 232.88 seconds |
Started | Jul 03 04:32:23 PM PDT 24 |
Finished | Jul 03 04:36:17 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-40423abf-e145-46b7-a69e-e55b68cbd7a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578036470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2578036470 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.654320841 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 311019536 ps |
CPU time | 13.46 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:32:33 PM PDT 24 |
Peak memory | 262364 kb |
Host | smart-f1d6a34e-ed86-4a08-9e30-95f76a891a43 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654320841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.654320841 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2058905992 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 8515033037 ps |
CPU time | 1075.74 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:50:19 PM PDT 24 |
Peak memory | 373712 kb |
Host | smart-5f4f7ed9-9b1d-4405-832c-bdb397d91562 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058905992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2058905992 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.2815830657 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 33819929 ps |
CPU time | 0.69 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:39 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-8262c897-038a-4942-b6ca-52b66455c677 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815830657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.2815830657 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.1211459884 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 13727770006 ps |
CPU time | 52.82 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:33:16 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-09094527-3b47-40f3-8b4a-6d6cf2c7dd47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211459884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 1211459884 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.1178579875 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 31476648350 ps |
CPU time | 1121.92 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:51:07 PM PDT 24 |
Peak memory | 374172 kb |
Host | smart-99703519-8cf3-4f65-8121-97b5163c2d08 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178579875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1178579875 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.198902654 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 16998795852 ps |
CPU time | 11.02 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:32:41 PM PDT 24 |
Peak memory | 215208 kb |
Host | smart-a7e313cf-6124-494d-b116-df954739ff4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198902654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca lation.198902654 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.3938879516 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 163221587 ps |
CPU time | 7.91 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:32:33 PM PDT 24 |
Peak memory | 240996 kb |
Host | smart-2db6b383-0dd0-433e-9d85-dd162b62c8e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938879516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.3938879516 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.292933386 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 301569600 ps |
CPU time | 5.25 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:28 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-a4f871d6-398a-4eb9-b5ef-9be0ec75df81 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292933386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_mem_partial_access.292933386 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.1181094142 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 1777283627 ps |
CPU time | 10.88 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-81ed7c69-dc8d-407b-96e1-75118139f000 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181094142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1181094142 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.3978425254 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 2886099125 ps |
CPU time | 1035.07 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:49:42 PM PDT 24 |
Peak memory | 371596 kb |
Host | smart-2e07c112-4a25-43f0-9e20-5b12dedb656d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978425254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.3978425254 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.1292942991 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 1348040547 ps |
CPU time | 6.2 seconds |
Started | Jul 03 04:32:16 PM PDT 24 |
Finished | Jul 03 04:32:23 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-3ab41e93-487d-42c9-a8cb-af7979eafdbb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292942991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1292942991 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3016514875 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 11407273266 ps |
CPU time | 294.15 seconds |
Started | Jul 03 04:32:13 PM PDT 24 |
Finished | Jul 03 04:37:08 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-bac8ba6c-9bff-4049-a2b7-9f53bf07556d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016514875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.3016514875 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2080256852 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 25364437 ps |
CPU time | 0.75 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:32:30 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-8f241658-ce1d-43f4-a03a-754d1dc6c8bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080256852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2080256852 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.864223065 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 3825912829 ps |
CPU time | 1643.91 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:59:50 PM PDT 24 |
Peak memory | 374568 kb |
Host | smart-06e2c08a-a89b-4884-a5f6-414f4d77053a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864223065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.864223065 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.1087597206 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 139757443 ps |
CPU time | 123.54 seconds |
Started | Jul 03 04:32:12 PM PDT 24 |
Finished | Jul 03 04:34:17 PM PDT 24 |
Peak memory | 368412 kb |
Host | smart-7f4fd16e-9d58-412b-bc87-a4145f5b397e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087597206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1087597206 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.714891824 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 15523234375 ps |
CPU time | 665.17 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:43:33 PM PDT 24 |
Peak memory | 373184 kb |
Host | smart-abd74f47-362e-4f75-8ec7-ca06ea21f6d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714891824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.714891824 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1099696211 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 43796642137 ps |
CPU time | 88.49 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:33:50 PM PDT 24 |
Peak memory | 295108 kb |
Host | smart-6bec9ccf-1307-49af-a701-27de1dde7bc7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1099696211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1099696211 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.615098062 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 5917449977 ps |
CPU time | 249.34 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:36:35 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-fd0d0be1-59e0-489d-9eb5-11141bc8976a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615098062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.615098062 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4293476145 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 159499844 ps |
CPU time | 2.12 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:32:24 PM PDT 24 |
Peak memory | 214668 kb |
Host | smart-9d656aba-3d53-479c-930e-c0391aa92fe5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293476145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.4293476145 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1504945389 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 4010865501 ps |
CPU time | 1631.31 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:59:36 PM PDT 24 |
Peak memory | 373660 kb |
Host | smart-cb761eb9-9250-4c7d-8476-e15af5399c75 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504945389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1504945389 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.1070449935 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 13851836 ps |
CPU time | 0.66 seconds |
Started | Jul 03 04:32:23 PM PDT 24 |
Finished | Jul 03 04:32:25 PM PDT 24 |
Peak memory | 202252 kb |
Host | smart-1e30b431-53f6-4372-b9eb-b193c89c3b30 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070449935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1070449935 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.1078021557 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 9989343182 ps |
CPU time | 82.05 seconds |
Started | Jul 03 04:32:32 PM PDT 24 |
Finished | Jul 03 04:33:57 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-d98bbc55-d23f-46a6-b8c2-78e30d62b5da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078021557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1078021557 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.3936931442 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1269646051 ps |
CPU time | 248.58 seconds |
Started | Jul 03 04:32:16 PM PDT 24 |
Finished | Jul 03 04:36:26 PM PDT 24 |
Peak memory | 342764 kb |
Host | smart-86c456dc-1ae0-4837-820c-ac2366dee167 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936931442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.3936931442 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.3063479551 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 208259100 ps |
CPU time | 3.17 seconds |
Started | Jul 03 04:32:23 PM PDT 24 |
Finished | Jul 03 04:32:27 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-5196cd51-70c8-4eae-902e-81f172e63d74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063479551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.3063479551 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.2202702824 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 228355882 ps |
CPU time | 8.58 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:35 PM PDT 24 |
Peak memory | 244092 kb |
Host | smart-1fb3b978-d3b4-4b00-887a-e1b8b67e8428 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202702824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2202702824 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3688079319 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 680903228 ps |
CPU time | 6.21 seconds |
Started | Jul 03 04:32:36 PM PDT 24 |
Finished | Jul 03 04:32:43 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-0e4ee873-12c6-41ec-ae97-eafa93790f21 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688079319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.3688079319 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2220960274 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 1198996650 ps |
CPU time | 6.38 seconds |
Started | Jul 03 04:32:18 PM PDT 24 |
Finished | Jul 03 04:32:25 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-257e0c89-baa1-4d17-b4a4-91a102e95dd5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220960274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2220960274 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.2523508032 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 2543534118 ps |
CPU time | 561.72 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:41:48 PM PDT 24 |
Peak memory | 374612 kb |
Host | smart-210434ef-0c8a-45e0-b3b0-7886220b12ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523508032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2523508032 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.1978822314 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 405642696 ps |
CPU time | 16.36 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:47 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-2acba5a5-a8a8-4d12-9e69-7b9b96a1520a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978822314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.1978822314 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.889476035 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 102306143472 ps |
CPU time | 481.07 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:40:26 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-58561738-8126-4b1c-b00a-48fddaa1d4bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889476035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.889476035 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.2929204633 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 84090002 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:32:28 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-51ec9b42-1c05-4f3d-b4cd-989f509a199a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929204633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2929204633 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.209761963 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 81865819702 ps |
CPU time | 1151.42 seconds |
Started | Jul 03 04:32:32 PM PDT 24 |
Finished | Jul 03 04:51:44 PM PDT 24 |
Peak memory | 374716 kb |
Host | smart-f1913d30-a4b2-4e74-92c5-8be6ce78ffd2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209761963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.209761963 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.885814877 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 710292417 ps |
CPU time | 1.83 seconds |
Started | Jul 03 04:32:20 PM PDT 24 |
Finished | Jul 03 04:32:22 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-2726bf2e-00f6-4ce3-91e8-3f3886161744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885814877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.885814877 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2602982674 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 6077493207 ps |
CPU time | 40.4 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:33:10 PM PDT 24 |
Peak memory | 223452 kb |
Host | smart-0e44ee69-b734-47e6-87ab-e82f23e42ee6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2602982674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2602982674 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2437653914 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 11764456940 ps |
CPU time | 258.41 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:36:45 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-fbc3efba-a9ae-466a-9e24-41e71c6cdd02 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437653914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.2437653914 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2006840269 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 405002710 ps |
CPU time | 80.47 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:33:49 PM PDT 24 |
Peak memory | 351592 kb |
Host | smart-0d1e3b0f-c0c0-4978-8912-e843a45fa566 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006840269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2006840269 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2722965875 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 11111226309 ps |
CPU time | 932.95 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:47:53 PM PDT 24 |
Peak memory | 375728 kb |
Host | smart-5ef4b4ea-ed61-46bf-bee6-bfe81257f95f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722965875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.2722965875 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.2566719989 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 45740828 ps |
CPU time | 0.67 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:32:32 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-836c164c-bb0a-4b8e-882e-616f22ca8311 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566719989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2566719989 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.4276101469 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 2282874081 ps |
CPU time | 36.23 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:33:07 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-987f9a43-46fb-4a4b-9ac3-3ca58e71c732 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276101469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 4276101469 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.2874377174 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 40002603223 ps |
CPU time | 956.53 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:48:29 PM PDT 24 |
Peak memory | 374272 kb |
Host | smart-fcfe86b9-8a63-451b-b528-16dbe3a638e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874377174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.2874377174 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.835973242 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 302743615 ps |
CPU time | 3.34 seconds |
Started | Jul 03 04:32:52 PM PDT 24 |
Finished | Jul 03 04:32:56 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-fd2c8107-dcfd-4038-8d66-f11142200d27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835973242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca lation.835973242 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.1568466080 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 81633377 ps |
CPU time | 13.04 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 260092 kb |
Host | smart-12a8b7f2-c16a-46f6-bc26-416fb76ad336 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568466080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1568466080 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.318231264 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 75216532 ps |
CPU time | 4.57 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:32:24 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-bd384fcb-b45b-40ee-a1b3-a301ab883208 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318231264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.318231264 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.698397459 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 7260975024 ps |
CPU time | 1107.88 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:50:51 PM PDT 24 |
Peak memory | 374676 kb |
Host | smart-4923f8f3-523d-4714-bab4-04d5006a9430 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698397459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl e_keys.698397459 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.1064703193 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 1124037518 ps |
CPU time | 15.87 seconds |
Started | Jul 03 04:33:07 PM PDT 24 |
Finished | Jul 03 04:33:23 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-339b8bbc-5cf0-4fae-8b18-d103368df7d4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064703193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1064703193 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2605518604 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 33864053789 ps |
CPU time | 391.51 seconds |
Started | Jul 03 04:32:24 PM PDT 24 |
Finished | Jul 03 04:38:55 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-7ed12736-a0d2-425b-9020-b289a476fdf4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605518604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.2605518604 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3082764559 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 27054124 ps |
CPU time | 0.76 seconds |
Started | Jul 03 04:32:41 PM PDT 24 |
Finished | Jul 03 04:32:42 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-09b53829-cd8e-4abe-bfd1-94094ee8222a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082764559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3082764559 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.1728732696 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 9372639326 ps |
CPU time | 667.44 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:43:37 PM PDT 24 |
Peak memory | 372440 kb |
Host | smart-b1e2efe5-e26e-4de3-a7c4-58c1cb1d73ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728732696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1728732696 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.96175681 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 646134428 ps |
CPU time | 113.27 seconds |
Started | Jul 03 04:32:21 PM PDT 24 |
Finished | Jul 03 04:34:15 PM PDT 24 |
Peak memory | 369872 kb |
Host | smart-55316487-11e6-4f79-83e9-5812ad197d8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96175681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.96175681 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1871828247 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1203723775 ps |
CPU time | 228.74 seconds |
Started | Jul 03 04:32:30 PM PDT 24 |
Finished | Jul 03 04:36:21 PM PDT 24 |
Peak memory | 361636 kb |
Host | smart-4f8423c0-850a-4f80-9a41-6076b2cff69b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1871828247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1871828247 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2776907282 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 2787360397 ps |
CPU time | 223.74 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:36:17 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-2172d3cc-447d-4533-afc9-c58f80187816 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776907282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.2776907282 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.513030566 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 120581216 ps |
CPU time | 17.65 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:40 PM PDT 24 |
Peak memory | 270188 kb |
Host | smart-c25b189b-bd1a-44f0-b44c-b420f695dccd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513030566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_throughput_w_partial_write.513030566 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1620016202 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 7833272599 ps |
CPU time | 698.46 seconds |
Started | Jul 03 04:32:32 PM PDT 24 |
Finished | Jul 03 04:44:14 PM PDT 24 |
Peak memory | 372808 kb |
Host | smart-e76529ad-81a8-4d29-8fc0-25eaf59c9a2f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620016202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.1620016202 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.2548872573 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 35219521 ps |
CPU time | 0.64 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:32:36 PM PDT 24 |
Peak memory | 202524 kb |
Host | smart-9aba372e-6eb0-49c1-9427-d3fb118d3844 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548872573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2548872573 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.3734151836 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 3203649012 ps |
CPU time | 34.68 seconds |
Started | Jul 03 04:32:22 PM PDT 24 |
Finished | Jul 03 04:32:57 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-1177070c-ef51-4304-824d-dbb04d4703f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734151836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3734151836 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.1685068289 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 9525669265 ps |
CPU time | 1395.55 seconds |
Started | Jul 03 04:32:31 PM PDT 24 |
Finished | Jul 03 04:55:48 PM PDT 24 |
Peak memory | 375096 kb |
Host | smart-438bf339-8682-4164-aae8-d840f11c1d97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685068289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1685068289 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.2537476470 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 851560562 ps |
CPU time | 6.28 seconds |
Started | Jul 03 04:32:29 PM PDT 24 |
Finished | Jul 03 04:32:37 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-14498c6f-cea6-4b48-bcbd-210bd587c6a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537476470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.2537476470 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.2737431509 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 105847437 ps |
CPU time | 1.37 seconds |
Started | Jul 03 04:32:19 PM PDT 24 |
Finished | Jul 03 04:32:21 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-82705b48-3bf3-4efc-b1ae-c9e4274576e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737431509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.2737431509 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2686437044 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 582236179 ps |
CPU time | 5.48 seconds |
Started | Jul 03 04:32:35 PM PDT 24 |
Finished | Jul 03 04:32:41 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-68a652a1-9d2f-435c-bd18-ff1e7806b4ee |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686437044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2686437044 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.490030784 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 1209373473 ps |
CPU time | 6.13 seconds |
Started | Jul 03 04:32:37 PM PDT 24 |
Finished | Jul 03 04:32:44 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-5c378fe1-a7af-4622-86ef-56bd8ee1a41f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490030784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ mem_walk.490030784 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.1531426263 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 18598234435 ps |
CPU time | 830.13 seconds |
Started | Jul 03 04:32:11 PM PDT 24 |
Finished | Jul 03 04:46:02 PM PDT 24 |
Peak memory | 372772 kb |
Host | smart-9d60e539-b54b-47b6-8077-e4c6e7e10333 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531426263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1531426263 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.2690828483 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 524964897 ps |
CPU time | 55.28 seconds |
Started | Jul 03 04:32:28 PM PDT 24 |
Finished | Jul 03 04:33:24 PM PDT 24 |
Peak memory | 332552 kb |
Host | smart-5f9e88f0-9ff1-4d04-8cda-354cb8a6a700 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690828483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.2690828483 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3223279624 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 5730285841 ps |
CPU time | 403.28 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:39:12 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-f9548069-775f-45c4-99d7-8f68c4f90301 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223279624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.3223279624 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.235135692 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 49425280 ps |
CPU time | 0.78 seconds |
Started | Jul 03 04:32:26 PM PDT 24 |
Finished | Jul 03 04:32:27 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-bbacd153-4bec-47a2-b6af-72bf2ca4c44a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235135692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.235135692 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.1055042123 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 9319961332 ps |
CPU time | 103.38 seconds |
Started | Jul 03 04:32:33 PM PDT 24 |
Finished | Jul 03 04:34:17 PM PDT 24 |
Peak memory | 344068 kb |
Host | smart-99a5a039-8d5c-45b2-a772-8b57bc9d5843 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055042123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1055042123 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.2824321755 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 1102107424 ps |
CPU time | 94.15 seconds |
Started | Jul 03 04:32:27 PM PDT 24 |
Finished | Jul 03 04:34:02 PM PDT 24 |
Peak memory | 345104 kb |
Host | smart-a08c8bad-c03c-427c-b75a-d207861fc701 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824321755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2824321755 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.1571362010 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 39642777247 ps |
CPU time | 3132.22 seconds |
Started | Jul 03 04:32:38 PM PDT 24 |
Finished | Jul 03 05:24:51 PM PDT 24 |
Peak memory | 375044 kb |
Host | smart-0ef6ec89-5cb2-4e09-baa8-61c9c92ace3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571362010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.1571362010 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.729877288 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1012636980 ps |
CPU time | 24.41 seconds |
Started | Jul 03 04:32:25 PM PDT 24 |
Finished | Jul 03 04:32:51 PM PDT 24 |
Peak memory | 219336 kb |
Host | smart-6c37c5cf-5dc2-44ee-a51a-09ef4ed94fc1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=729877288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.729877288 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1818980542 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 4902028059 ps |
CPU time | 120.49 seconds |
Started | Jul 03 04:33:01 PM PDT 24 |
Finished | Jul 03 04:35:03 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-d27375f2-9926-40a0-9be9-3fb2dd3429f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818980542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1818980542 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1228227736 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 416280236 ps |
CPU time | 17.8 seconds |
Started | Jul 03 04:32:42 PM PDT 24 |
Finished | Jul 03 04:33:00 PM PDT 24 |
Peak memory | 269148 kb |
Host | smart-d06284e9-4202-46d4-a9d3-f60a16ed16b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228227736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1228227736 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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