Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14265756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60173782

1

T1

186682

T3

3762

T4

121

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37116189	1			T1	102413		T3	2310		T4	866
values[0x0]	17225438	1			T1	49117		T3	1058		T4	342
values[0x1]	20097911	1			T1	53563		T3	1259		T4	768

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7104404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67335134

1

T1

195948

T3

4202

T4

954

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	263285	1			T1	862		T3	8		T4	6
valid_sources[0x01]	288523	1			T1	850		T3	16		T4	12
valid_sources[0x02]	300670	1			T1	750		T3	27		T4	4
valid_sources[0x03]	256152	1			T1	848		T3	14		T4	6
valid_sources[0x04]	284319	1			T1	848		T3	23		T4	7
valid_sources[0x05]	303946	1			T1	822		T3	21		T4	1
valid_sources[0x06]	298623	1			T1	681		T3	21		T10	24
valid_sources[0x07]	270985	1			T1	817		T3	25		T6	1
valid_sources[0x08]	292663	1			T1	791		T3	12		T4	12
valid_sources[0x09]	314754	1			T1	763		T3	15		T4	23
valid_sources[0x0a]	284843	1			T1	847		T3	18		T4	4
valid_sources[0x0b]	268853	1			T1	769		T3	14		T4	10
valid_sources[0x0c]	272015	1			T1	753		T3	15		T4	18
valid_sources[0x0d]	319317	1			T1	822		T3	10		T4	3
valid_sources[0x0e]	376284	1			T1	765		T3	14		T4	7
valid_sources[0x0f]	282437	1			T1	798		T3	14		T4	4
valid_sources[0x10]	267623	1			T1	784		T3	21		T4	4
valid_sources[0x11]	357951	1			T1	852		T3	15		T11	5
valid_sources[0x12]	318432	1			T1	848		T3	11		T4	6
valid_sources[0x13]	263342	1			T1	869		T3	23		T4	8
valid_sources[0x14]	327323	1			T1	817		T3	23		T4	3
valid_sources[0x15]	306525	1			T1	850		T3	8		T4	14
valid_sources[0x16]	323211	1			T1	798		T3	21		T4	2
valid_sources[0x17]	402441	1			T1	818		T3	12		T4	6
valid_sources[0x18]	263481	1			T1	877		T3	29		T4	8
valid_sources[0x19]	270873	1			T1	790		T3	15		T4	5
valid_sources[0x1a]	285066	1			T1	910		T3	18		T4	9
valid_sources[0x1b]	258733	1			T1	763		T3	9		T4	1
valid_sources[0x1c]	272723	1			T1	823		T3	23		T4	2
valid_sources[0x1d]	264550	1			T1	781		T3	32		T4	2
valid_sources[0x1e]	294994	1			T1	766		T3	3		T4	13
valid_sources[0x1f]	270865	1			T1	868		T3	23		T4	2
valid_sources[0x20]	264599	1			T1	750		T3	20		T4	9
valid_sources[0x21]	278788	1			T1	839		T3	10		T4	12
valid_sources[0x22]	263877	1			T1	873		T3	13		T4	5
valid_sources[0x23]	303394	1			T1	804		T3	42		T4	7
valid_sources[0x24]	258449	1			T1	804		T3	20		T4	16
valid_sources[0x25]	283445	1			T1	867		T3	16		T4	24
valid_sources[0x26]	280119	1			T1	755		T3	21		T4	9
valid_sources[0x27]	287497	1			T1	832		T3	27		T4	14
valid_sources[0x28]	333514	1			T1	817		T3	14		T4	2
valid_sources[0x29]	254253	1			T1	822		T3	23		T4	5
valid_sources[0x2a]	252516	1			T1	768		T3	20		T4	5
valid_sources[0x2b]	249454	1			T1	889		T3	16		T4	17
valid_sources[0x2c]	251017	1			T1	808		T3	26		T4	22
valid_sources[0x2d]	287437	1			T1	709		T3	13		T4	9
valid_sources[0x2e]	341195	1			T1	751		T3	17		T4	23
valid_sources[0x2f]	252888	1			T1	813		T3	18		T4	7
valid_sources[0x30]	328084	1			T1	902		T3	12		T4	1
valid_sources[0x31]	261838	1			T1	882		T3	14		T4	9
valid_sources[0x32]	313920	1			T1	838		T3	15		T4	1
valid_sources[0x33]	306746	1			T1	711		T3	20		T4	4
valid_sources[0x34]	255412	1			T1	781		T3	9		T4	1
valid_sources[0x35]	284305	1			T1	770		T3	22		T4	10
valid_sources[0x36]	276671	1			T1	808		T3	19		T4	3
valid_sources[0x37]	311832	1			T1	850		T3	15		T4	8
valid_sources[0x38]	264723	1			T1	757		T3	15		T4	4
valid_sources[0x39]	255230	1			T1	870		T3	13		T4	7
valid_sources[0x3a]	312857	1			T1	779		T3	14		T4	15
valid_sources[0x3b]	285281	1			T1	773		T3	21		T4	10
valid_sources[0x3c]	281303	1			T1	735		T3	16		T4	1
valid_sources[0x3d]	263943	1			T1	881		T3	27		T4	1
valid_sources[0x3e]	289805	1			T1	783		T3	19		T4	25
valid_sources[0x3f]	334841	1			T1	719		T3	13		T4	10
valid_sources[0x40]	253843	1			T1	796		T3	13		T4	15
valid_sources[0x41]	311014	1			T1	847		T3	17		T4	2
valid_sources[0x42]	248359	1			T1	767		T3	31		T4	18
valid_sources[0x43]	276336	1			T1	759		T3	8		T4	12
valid_sources[0x44]	323520	1			T1	845		T3	17		T4	4
valid_sources[0x45]	271637	1			T1	912		T3	18		T4	5
valid_sources[0x46]	262188	1			T1	772		T3	29		T4	9
valid_sources[0x47]	267443	1			T1	715		T3	21		T4	11
valid_sources[0x48]	290214	1			T1	844		T3	21		T6	1
valid_sources[0x49]	277040	1			T1	778		T3	30		T4	2
valid_sources[0x4a]	312301	1			T1	769		T3	15		T10	16
valid_sources[0x4b]	309878	1			T1	766		T3	8		T4	10
valid_sources[0x4c]	282289	1			T1	736		T3	17		T4	7
valid_sources[0x4d]	302720	1			T1	915		T3	26		T4	3
valid_sources[0x4e]	298591	1			T1	801		T3	10		T4	7
valid_sources[0x4f]	306663	1			T1	816		T3	13		T10	40
valid_sources[0x50]	263528	1			T1	807		T3	16		T4	9
valid_sources[0x51]	416930	1			T1	869		T3	27		T4	2
valid_sources[0x52]	254149	1			T1	793		T3	14		T4	6
valid_sources[0x53]	263676	1			T1	752		T3	26		T4	2
valid_sources[0x54]	274391	1			T1	765		T3	24		T4	5
valid_sources[0x55]	255904	1			T1	701		T3	5		T4	10
valid_sources[0x56]	286502	1			T1	707		T3	17		T4	11
valid_sources[0x57]	387504	1			T1	735		T3	13		T4	2
valid_sources[0x58]	276320	1			T1	836		T3	5		T4	8
valid_sources[0x59]	283098	1			T1	791		T3	12		T4	9
valid_sources[0x5a]	259729	1			T1	867		T3	21		T4	8
valid_sources[0x5b]	246271	1			T1	792		T3	29		T4	1
valid_sources[0x5c]	285324	1			T1	772		T3	22		T4	15
valid_sources[0x5d]	305919	1			T1	870		T3	21		T4	8
valid_sources[0x5e]	396755	1			T1	774		T3	22		T4	8
valid_sources[0x5f]	292323	1			T1	740		T3	14		T4	8
valid_sources[0x60]	263546	1			T1	787		T3	23		T4	5
valid_sources[0x61]	272095	1			T1	825		T3	12		T4	4
valid_sources[0x62]	255425	1			T1	801		T3	25		T4	2
valid_sources[0x63]	293709	1			T1	720		T3	12		T4	17
valid_sources[0x64]	252391	1			T1	868		T3	20		T4	3
valid_sources[0x65]	308316	1			T1	768		T3	21		T4	18
valid_sources[0x66]	283393	1			T1	800		T3	19		T4	7
valid_sources[0x67]	421496	1			T1	951		T3	22		T4	9
valid_sources[0x68]	267123	1			T1	843		T3	16		T4	4
valid_sources[0x69]	314395	1			T1	869		T3	24		T4	17
valid_sources[0x6a]	267686	1			T1	810		T3	21		T4	3
valid_sources[0x6b]	302399	1			T1	872		T3	14		T4	3
valid_sources[0x6c]	300877	1			T1	785		T3	21		T4	6
valid_sources[0x6d]	256994	1			T1	770		T3	11		T4	11
valid_sources[0x6e]	263806	1			T1	795		T3	24		T4	4
valid_sources[0x6f]	294097	1			T1	753		T3	16		T4	14
valid_sources[0x70]	258168	1			T1	951		T3	21		T4	6
valid_sources[0x71]	312842	1			T1	799		T3	28		T4	12
valid_sources[0x72]	312851	1			T1	712		T3	5		T4	4
valid_sources[0x73]	257388	1			T1	754		T3	21		T10	154
valid_sources[0x74]	289753	1			T1	888		T3	28		T4	7
valid_sources[0x75]	296856	1			T1	764		T3	12		T4	1
valid_sources[0x76]	246604	1			T1	848		T3	20		T4	9
valid_sources[0x77]	259659	1			T1	842		T3	9		T4	14
valid_sources[0x78]	334049	1			T1	808		T3	23		T4	13
valid_sources[0x79]	260565	1			T1	703		T3	21		T4	17
valid_sources[0x7a]	265782	1			T1	913		T3	19		T4	1
valid_sources[0x7b]	282737	1			T1	812		T3	10		T4	6
valid_sources[0x7c]	261864	1			T1	854		T3	15		T4	4
valid_sources[0x7d]	249253	1			T1	808		T3	6		T4	11
valid_sources[0x7e]	255356	1			T1	882		T3	11		T4	9
valid_sources[0x7f]	287265	1			T1	797		T3	25		T10	47
valid_sources[0x80]	297434	1			T1	800		T3	24		T4	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29985591

1

T1

93240

T3

1870

T4

5

values[0x0]

all_enables

biggest_size

15087497

1

T1

46387

T3

917

T4

64

values[0x1]

all_enables

biggest_size

15100694

1

T1

47055

T3

975

T4

52

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123113

1

T1

13

T2

1

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46066	1			T6	3		T7	61		T8	32
values[0x0]	54335	1			T1	21		T3	1		T4	2
values[0x1]	58151	1			T1	23		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

131632

1

T1

17

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	802	1			T1	1		T7	2		T8	1
valid_sources[0x01]	676	1			T7	4		T8	1		T20	4
valid_sources[0x02]	884	1			T8	1		T20	3		T25	12
valid_sources[0x03]	461	1			T1	1		T20	5		T25	6
valid_sources[0x04]	526	1			T8	1		T20	3		T25	4
valid_sources[0x05]	580	1			T20	6		T25	5		T21	2
valid_sources[0x06]	781	1			T20	4		T25	3		T21	143
valid_sources[0x07]	780	1			T20	6		T25	5		T21	131
valid_sources[0x08]	820	1			T20	8		T25	9		T21	1
valid_sources[0x09]	423	1			T24	1		T20	2		T25	4
valid_sources[0x0a]	582	1			T1	1		T20	2		T25	13
valid_sources[0x0b]	909	1			T20	1		T21	1		T143	2
valid_sources[0x0c]	708	1			T20	3		T42	1		T25	19
valid_sources[0x0d]	903	1			T8	1		T20	7		T25	7
valid_sources[0x0e]	528	1			T20	4		T21	2		T56	11
valid_sources[0x0f]	489	1			T20	12		T25	11		T43	3
valid_sources[0x10]	705	1			T7	1		T8	1		T20	11
valid_sources[0x11]	469	1			T1	1		T20	5		T25	4
valid_sources[0x12]	609	1			T20	1		T25	3		T21	52
valid_sources[0x13]	672	1			T7	2		T20	9		T25	10
valid_sources[0x14]	594	1			T1	1		T7	1		T20	9
valid_sources[0x15]	463	1			T8	1		T20	4		T25	5
valid_sources[0x16]	570	1			T20	3		T42	1		T25	3
valid_sources[0x17]	500	1			T7	1		T20	2		T42	1
valid_sources[0x18]	607	1			T1	1		T7	1		T20	6
valid_sources[0x19]	394	1			T20	3		T25	4		T57	1
valid_sources[0x1a]	468	1			T1	1		T20	4		T25	6
valid_sources[0x1b]	460	1			T7	2		T20	1		T25	6
valid_sources[0x1c]	602	1			T144	1		T20	3		T25	7
valid_sources[0x1d]	572	1			T7	2		T20	2		T42	1
valid_sources[0x1e]	577	1			T88	5		T20	7		T25	3
valid_sources[0x1f]	745	1			T20	6		T25	9		T21	4
valid_sources[0x20]	599	1			T1	1		T7	1		T20	11
valid_sources[0x21]	689	1			T20	12		T25	2		T21	125
valid_sources[0x22]	523	1			T8	1		T20	9		T25	2
valid_sources[0x23]	679	1			T1	1		T8	1		T20	3
valid_sources[0x24]	641	1			T12	2		T8	1		T20	5
valid_sources[0x25]	482	1			T7	1		T145	1		T20	1
valid_sources[0x26]	468	1			T7	1		T20	4		T42	1
valid_sources[0x27]	628	1			T24	1		T7	1		T20	5
valid_sources[0x28]	1094	1			T1	1		T7	2		T20	10
valid_sources[0x29]	458	1			T20	3		T25	8		T57	6
valid_sources[0x2a]	631	1			T7	1		T20	4		T25	8
valid_sources[0x2b]	703	1			T19	20		T8	1		T20	3
valid_sources[0x2c]	492	1			T25	7		T143	1		T57	17
valid_sources[0x2d]	662	1			T7	1		T20	1		T25	4
valid_sources[0x2e]	376	1			T7	2		T20	1		T25	3
valid_sources[0x2f]	421	1			T47	4		T20	10		T25	3
valid_sources[0x30]	576	1			T1	1		T20	6		T25	5
valid_sources[0x31]	562	1			T20	2		T25	3		T21	2
valid_sources[0x32]	476	1			T7	2		T8	1		T20	3
valid_sources[0x33]	571	1			T4	1		T7	4		T8	3
valid_sources[0x34]	656	1			T8	1		T20	2		T25	6
valid_sources[0x35]	440	1			T20	9		T25	6		T21	3
valid_sources[0x36]	992	1			T20	5		T25	6		T21	208
valid_sources[0x37]	447	1			T8	1		T20	3		T146	1
valid_sources[0x38]	802	1			T7	1		T8	1		T20	3
valid_sources[0x39]	629	1			T20	3		T25	4		T21	7
valid_sources[0x3a]	680	1			T20	7		T25	7		T21	5
valid_sources[0x3b]	573	1			T7	2		T20	1		T42	1
valid_sources[0x3c]	663	1			T9	1		T20	7		T25	3
valid_sources[0x3d]	495	1			T20	12		T25	4		T57	14
valid_sources[0x3e]	386	1			T1	1		T7	1		T20	3
valid_sources[0x3f]	513	1			T20	3		T25	5		T21	4
valid_sources[0x40]	647	1			T7	1		T20	6		T25	2
valid_sources[0x41]	722	1			T20	5		T25	8		T135	2
valid_sources[0x42]	710	1			T20	2		T25	4		T57	2
valid_sources[0x43]	576	1			T7	1		T20	11		T25	6
valid_sources[0x44]	505	1			T7	1		T25	9		T57	3
valid_sources[0x45]	758	1			T20	10		T42	1		T25	10
valid_sources[0x46]	477	1			T1	1		T8	1		T20	7
valid_sources[0x47]	506	1			T20	4		T25	8		T57	4
valid_sources[0x48]	593	1			T25	5		T136	1		T147	1
valid_sources[0x49]	744	1			T20	7		T25	8		T21	90
valid_sources[0x4a]	658	1			T25	1		T57	8		T77	1
valid_sources[0x4b]	937	1			T7	1		T20	3		T42	2
valid_sources[0x4c]	1322	1			T7	1		T8	1		T20	3
valid_sources[0x4d]	801	1			T7	2		T8	1		T20	13
valid_sources[0x4e]	643	1			T1	1		T26	1		T7	1
valid_sources[0x4f]	1154	1			T1	1		T20	5		T25	2
valid_sources[0x50]	563	1			T1	1		T20	5		T25	2
valid_sources[0x51]	559	1			T8	1		T20	2		T25	7
valid_sources[0x52]	445	1			T20	1		T25	7		T21	1
valid_sources[0x53]	563	1			T20	5		T25	5		T21	1
valid_sources[0x54]	735	1			T20	5		T25	5		T148	1
valid_sources[0x55]	696	1			T20	5		T25	7		T22	4
valid_sources[0x56]	883	1			T8	2		T20	3		T25	6
valid_sources[0x57]	402	1			T7	1		T20	2		T57	2
valid_sources[0x58]	466	1			T20	4		T25	7		T65	1
valid_sources[0x59]	551	1			T20	3		T25	7		T112	1
valid_sources[0x5a]	868	1			T26	1		T20	6		T25	6
valid_sources[0x5b]	1033	1			T7	2		T20	10		T25	9
valid_sources[0x5c]	646	1			T1	1		T8	2		T20	6
valid_sources[0x5d]	632	1			T39	3		T8	1		T42	1
valid_sources[0x5e]	694	1			T7	3		T8	1		T20	3
valid_sources[0x5f]	638	1			T20	3		T25	2		T57	7
valid_sources[0x60]	547	1			T8	1		T20	2		T42	1
valid_sources[0x61]	654	1			T1	1		T4	1		T7	1
valid_sources[0x62]	569	1			T1	1		T7	1		T20	2
valid_sources[0x63]	733	1			T1	1		T8	2		T20	5
valid_sources[0x64]	755	1			T7	1		T20	10		T25	5
valid_sources[0x65]	556	1			T6	8		T20	4		T25	4
valid_sources[0x66]	763	1			T3	1		T20	3		T25	6
valid_sources[0x67]	469	1			T7	2		T20	11		T42	1
valid_sources[0x68]	442	1			T1	1		T8	1		T20	2
valid_sources[0x69]	487	1			T20	3		T25	7		T57	2
valid_sources[0x6a]	662	1			T11	2		T20	4		T42	1
valid_sources[0x6b]	657	1			T7	1		T20	3		T25	3
valid_sources[0x6c]	839	1			T7	1		T8	1		T20	6
valid_sources[0x6d]	618	1			T1	1		T7	1		T20	6
valid_sources[0x6e]	504	1			T20	5		T25	10		T21	1
valid_sources[0x6f]	555	1			T20	10		T25	2		T21	1
valid_sources[0x70]	901	1			T8	1		T20	2		T25	4
valid_sources[0x71]	432	1			T1	1		T20	5		T42	1
valid_sources[0x72]	464	1			T7	3		T20	3		T25	5
valid_sources[0x73]	451	1			T7	1		T20	2		T42	2
valid_sources[0x74]	586	1			T2	1		T20	2		T25	5
valid_sources[0x75]	563	1			T20	5		T42	1		T25	4
valid_sources[0x76]	464	1			T8	1		T20	6		T25	1
valid_sources[0x77]	530	1			T8	2		T20	1		T25	10
valid_sources[0x78]	665	1			T1	1		T5	7		T13	19
valid_sources[0x79]	450	1			T20	5		T25	5		T21	3
valid_sources[0x7a]	679	1			T7	1		T20	1		T25	6
valid_sources[0x7b]	551	1			T1	1		T7	1		T20	3
valid_sources[0x7c]	1138	1			T20	8		T25	10		T21	194
valid_sources[0x7d]	456	1			T7	1		T20	6		T25	5
valid_sources[0x7e]	484	1			T8	2		T20	5		T25	5
valid_sources[0x7f]	644	1			T20	8		T25	3		T21	59
valid_sources[0x80]	502	1			T8	1		T20	5		T25	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33704

1

T7

31

T8

14

T20

286

values[0x0]

all_enables

biggest_size

45863

1

T1

7

T10

1

T5

1

values[0x1]

all_enables

biggest_size

43546

1

T1

6

T2

1

T10

1