Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13929600

1

T1

14750

T3

865

T4

1855

full_word

55102500

1

T1

149266

T3

3762

T4

121

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69031820	1			T1	164016		T3	4627		T4	1976
auto[TlIntgErrCmd]	99	1			T61	5		T62	4		T63	2
auto[TlIntgErrData]	89	1			T61	3		T62	2		T63	3
auto[TlIntgErrBoth]	92	1			T61	2		T62	4		T63	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31668337

1

T1

61336

T3

2310

T4

866

auto[1]

37363763

1

T1

102680

T3

2317

T4

1110

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6665994	1			T1	5512		T3	440		T4	861
auto[TlIntgErrNone]	partial	auto[1]	7263343	1			T1	9238		T3	425		T4	994
auto[TlIntgErrNone]	full_word	auto[0]	25002221	1			T1	55824		T3	1870		T4	5
auto[TlIntgErrNone]	full_word	auto[1]	30100262	1			T1	93442		T3	1892		T4	116
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T61	2		T62	1		T63	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T61	3		T62	3		T122	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T129	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T63	1		T130	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T61	2		T62	2		T122	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T61	1		T63	3		T122	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T125	1		T131	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T124	1		T123	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T61	2		T62	1		T63	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T62	3		T63	3		T122	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T123	1		T132	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T122	1		T120	1		T127	1