Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
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Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mem_bkdr_scb 100.00 1 100 1 64 64




Group Instance : mem_bkdr_scb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mem_bkdr_scb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group Instance mem_bkdr_scb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
b2b_access_types_cp 4 0 4 100.00 100 1 1 4
b2b_partial_types_cp 4 0 4 100.00 100 1 1 4
raw_hazard_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance mem_bkdr_scb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_cross 32 0 32 100.00 100 1 1 0


Summary for Variable b2b_access_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_access_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 773716 1 T1 1780 T40 4652 T39 112
auto[1] 10859933 1 T1 398 T3 2310 T6 48
auto[2] 636997 1 T1 1505 T40 3341 T7 1
auto[3] 10726838 1 T1 245 T3 2316 T6 34



Summary for Variable b2b_partial_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_partial_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14710928 1 T1 3080 T3 3074 T6 73
auto[1] 2221667 1 T1 442 T3 687 T6 3
auto[2] 2232805 1 T1 356 T3 700 T6 6
auto[3] 3832084 1 T1 50 T3 165 T11 787



Summary for Variable raw_hazard_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for raw_hazard_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8928258 1 T1 3926 T3 4622 T6 82
auto[1] 14069226 1 T1 2 T3 4 T12 9



Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for all_cross

Bins
raw_hazard_cpb2b_access_types_cpb2b_partial_types_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 315096 1 T1 1464 T40 1 T88 1
auto[0] auto[0] auto[1] 32609 1 T1 160 T8 1 T45 607
auto[0] auto[0] auto[2] 32591 1 T1 143 T88 1 T8 4
auto[0] auto[0] auto[3] 8340 1 T1 12 T39 110 T88 5
auto[0] auto[1] auto[0] 3359372 1 T1 227 T3 1525 T6 45
auto[0] auto[1] auto[1] 354117 1 T1 131 T3 342 T11 2
auto[0] auto[1] auto[2] 340775 1 T1 22 T3 355 T6 3
auto[0] auto[1] auto[3] 69039 1 T1 18 T3 85 T11 311
auto[0] auto[2] auto[0] 271298 1 T1 1270 T7 1 T8 20
auto[0] auto[2] auto[1] 27651 1 T1 132 T39 7 T8 2
auto[0] auto[2] auto[2] 29869 1 T1 92 T39 1 T8 3
auto[0] auto[2] auto[3] 7169 1 T1 10 T39 75 T88 1
auto[0] auto[3] auto[0] 3321649 1 T1 117 T3 1546 T6 28
auto[0] auto[3] auto[1] 336178 1 T1 19 T3 344 T6 3
auto[0] auto[3] auto[2] 351987 1 T1 99 T3 345 T6 3
auto[0] auto[3] auto[3] 70518 1 T1 10 T3 80 T11 476
auto[1] auto[0] auto[0] 13032 1 T1 1 T40 160 T88 1148
auto[1] auto[0] auto[1] 56961 1 T40 684 T88 5259 T45 1
auto[1] auto[0] auto[2] 57311 1 T40 732 T88 5296 T136 7
auto[1] auto[0] auto[3] 257776 1 T40 3075 T39 2 T88 24252
auto[1] auto[1] auto[0] 3714877 1 T3 3 T12 1 T24 1
auto[1] auto[1] auto[1] 698999 1 T12 1 T24 1 T26 5572
auto[1] auto[1] auto[2] 686980 1 T12 1 T26 6090 T41 1
auto[1] auto[1] auto[3] 1635774 1 T26 522 T40 10387 T7 1
auto[1] auto[2] auto[0] 9985 1 T1 1 T88 1114 T45 8
auto[1] auto[2] auto[1] 43781 1 T88 5002 T136 1 T139 3242
auto[1] auto[2] auto[2] 44705 1 T40 612 T88 3568 T46 1
auto[1] auto[2] auto[3] 202539 1 T40 2729 T88 16357 T140 1
auto[1] auto[3] auto[0] 3705619 1 T12 4 T26 62201 T41 6
auto[1] auto[3] auto[1] 671371 1 T3 1 T12 2 T26 6151
auto[1] auto[3] auto[2] 688587 1 T26 5547 T40 2306 T7 14
auto[1] auto[3] auto[3] 1580929 1 T26 544 T40 10226 T39 2

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