Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	337404158	184656	0	0
ctrl_regwen_rd_A	337404158	3531	0	0
exec_rd_A	337404158	3569	0	0
exec_regwen_rd_A	337404158	4138	0	0
readback_rd_A	337404158	3067	0	0
readback_regwen_rd_A	337404158	2629	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337404158	184656	0	0
T20	51377	1583	0	0
T21	156534	8233	0	0
T22	361924	0	0	0
T25	39254	2420	0	0
T42	393588	0	0	0
T48	0	2242	0	0
T49	0	4320	0	0
T57	0	1501	0	0
T59	0	5566	0	0
T60	0	1094	0	0
T70	0	3403	0	0
T71	0	4484	0	0
T72	303164	0	0	0
T73	15020	0	0	0
T74	2650	0	0	0
T75	239727	0	0	0
T76	14504	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337404158	3531	0	0
T20	51377	96	0	0
T21	156534	0	0	0
T22	361924	0	0	0
T25	39254	0	0	0
T42	393588	0	0	0
T48	0	137	0	0
T70	0	132	0	0
T71	0	289	0	0
T72	303164	0	0	0
T73	15020	0	0	0
T74	2650	0	0	0
T75	239727	0	0	0
T76	14504	0	0	0
T114	0	125	0	0
T115	0	228	0	0
T116	0	440	0	0
T117	0	93	0	0
T118	0	102	0	0
T119	0	336	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337404158	3569	0	0
T20	51377	142	0	0
T21	156534	0	0	0
T22	361924	0	0	0
T25	39254	0	0	0
T42	393588	0	0	0
T48	0	192	0	0
T70	0	117	0	0
T71	0	207	0	0
T72	303164	0	0	0
T73	15020	0	0	0
T74	2650	0	0	0
T75	239727	0	0	0
T76	14504	0	0	0
T114	0	79	0	0
T115	0	304	0	0
T116	0	518	0	0
T117	0	63	0	0
T118	0	78	0	0
T119	0	313	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337404158	4138	0	0
T20	51377	152	0	0
T21	156534	0	0	0
T22	361924	0	0	0
T25	39254	0	0	0
T42	393588	0	0	0
T48	0	254	0	0
T70	0	152	0	0
T71	0	275	0	0
T72	303164	0	0	0
T73	15020	0	0	0
T74	2650	0	0	0
T75	239727	0	0	0
T76	14504	0	0	0
T114	0	112	0	0
T115	0	343	0	0
T116	0	558	0	0
T117	0	61	0	0
T118	0	97	0	0
T119	0	323	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337404158	3067	0	0
T20	51377	142	0	0
T21	156534	0	0	0
T22	361924	0	0	0
T25	39254	0	0	0
T42	393588	0	0	0
T48	0	172	0	0
T70	0	104	0	0
T71	0	155	0	0
T72	303164	0	0	0
T73	15020	0	0	0
T74	2650	0	0	0
T75	239727	0	0	0
T76	14504	0	0	0
T114	0	36	0	0
T115	0	309	0	0
T116	0	374	0	0
T117	0	80	0	0
T118	0	45	0	0
T119	0	329	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337404158	2629	0	0
T20	51377	104	0	0
T21	156534	0	0	0
T22	361924	0	0	0
T25	39254	0	0	0
T42	393588	0	0	0
T48	0	209	0	0
T70	0	76	0	0
T71	0	175	0	0
T72	303164	0	0	0
T73	15020	0	0	0
T74	2650	0	0	0
T75	239727	0	0	0
T76	14504	0	0	0
T114	0	56	0	0
T115	0	214	0	0
T116	0	433	0	0
T117	0	42	0	0
T118	0	45	0	0
T119	0	239	0	0