| T794 |
/workspace/coverage/default/45.sram_ctrl_alert_test.677883416 |
|
|
Jul 04 07:19:31 PM PDT 24 |
Jul 04 07:19:32 PM PDT 24 |
20405872 ps |
| T795 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2782541821 |
|
|
Jul 04 07:16:32 PM PDT 24 |
Jul 04 07:33:48 PM PDT 24 |
9073157619 ps |
| T796 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2452131007 |
|
|
Jul 04 07:18:51 PM PDT 24 |
Jul 04 07:19:07 PM PDT 24 |
950503484 ps |
| T797 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3245195194 |
|
|
Jul 04 07:18:38 PM PDT 24 |
Jul 04 07:19:25 PM PDT 24 |
412210068 ps |
| T798 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3359092344 |
|
|
Jul 04 07:19:08 PM PDT 24 |
Jul 04 07:19:15 PM PDT 24 |
451780316 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2304599550 |
|
|
Jul 04 07:16:30 PM PDT 24 |
Jul 04 07:17:02 PM PDT 24 |
102609612 ps |
| T800 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2122050663 |
|
|
Jul 04 07:15:05 PM PDT 24 |
Jul 04 07:35:23 PM PDT 24 |
93208788788 ps |
| T801 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.222620170 |
|
|
Jul 04 07:16:19 PM PDT 24 |
Jul 04 07:17:52 PM PDT 24 |
4389071827 ps |
| T802 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1788982100 |
|
|
Jul 04 07:17:31 PM PDT 24 |
Jul 04 07:21:54 PM PDT 24 |
5185152813 ps |
| T803 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.794060461 |
|
|
Jul 04 07:16:00 PM PDT 24 |
Jul 04 07:24:54 PM PDT 24 |
21598182146 ps |
| T804 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1882416874 |
|
|
Jul 04 07:19:39 PM PDT 24 |
Jul 04 07:19:59 PM PDT 24 |
666706857 ps |
| T805 |
/workspace/coverage/default/46.sram_ctrl_partial_access.85364620 |
|
|
Jul 04 07:19:30 PM PDT 24 |
Jul 04 07:20:02 PM PDT 24 |
231144144 ps |
| T806 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.831469152 |
|
|
Jul 04 07:15:28 PM PDT 24 |
Jul 04 07:15:32 PM PDT 24 |
245897765 ps |
| T807 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2156524875 |
|
|
Jul 04 07:15:07 PM PDT 24 |
Jul 04 07:15:11 PM PDT 24 |
305583008 ps |
| T808 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.3907122269 |
|
|
Jul 04 07:19:30 PM PDT 24 |
Jul 04 07:19:36 PM PDT 24 |
194144322 ps |
| T809 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.750730713 |
|
|
Jul 04 07:20:02 PM PDT 24 |
Jul 04 07:20:03 PM PDT 24 |
40653529 ps |
| T810 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2003020260 |
|
|
Jul 04 07:17:19 PM PDT 24 |
Jul 04 07:17:33 PM PDT 24 |
169659310 ps |
| T811 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1771794625 |
|
|
Jul 04 07:17:32 PM PDT 24 |
Jul 04 07:17:35 PM PDT 24 |
44524217 ps |
| T812 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1857780051 |
|
|
Jul 04 07:16:52 PM PDT 24 |
Jul 04 07:40:00 PM PDT 24 |
94078605940 ps |
| T813 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2224433002 |
|
|
Jul 04 07:15:32 PM PDT 24 |
Jul 04 08:30:20 PM PDT 24 |
38105105789 ps |
| T814 |
/workspace/coverage/default/48.sram_ctrl_regwen.1189786459 |
|
|
Jul 04 07:19:53 PM PDT 24 |
Jul 04 07:46:15 PM PDT 24 |
92764267410 ps |
| T815 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2361461020 |
|
|
Jul 04 07:18:23 PM PDT 24 |
Jul 04 07:19:21 PM PDT 24 |
105029926 ps |
| T816 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.4068970226 |
|
|
Jul 04 07:18:36 PM PDT 24 |
Jul 04 07:18:42 PM PDT 24 |
860256571 ps |
| T817 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1607778445 |
|
|
Jul 04 07:15:49 PM PDT 24 |
Jul 04 07:16:53 PM PDT 24 |
636531191 ps |
| T818 |
/workspace/coverage/default/17.sram_ctrl_executable.1092403133 |
|
|
Jul 04 07:15:59 PM PDT 24 |
Jul 04 07:30:42 PM PDT 24 |
62860994050 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2720904466 |
|
|
Jul 04 07:16:34 PM PDT 24 |
Jul 04 07:16:54 PM PDT 24 |
1247371780 ps |
| T820 |
/workspace/coverage/default/39.sram_ctrl_alert_test.2357481415 |
|
|
Jul 04 07:18:33 PM PDT 24 |
Jul 04 07:18:34 PM PDT 24 |
13169695 ps |
| T821 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2194017969 |
|
|
Jul 04 07:15:13 PM PDT 24 |
Jul 04 07:17:34 PM PDT 24 |
31062995689 ps |
| T822 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2239929110 |
|
|
Jul 04 07:15:50 PM PDT 24 |
Jul 04 07:20:33 PM PDT 24 |
6012285094 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.966125432 |
|
|
Jul 04 07:19:23 PM PDT 24 |
Jul 04 07:25:42 PM PDT 24 |
45594213397 ps |
| T824 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.334310864 |
|
|
Jul 04 07:15:54 PM PDT 24 |
Jul 04 07:20:28 PM PDT 24 |
5386433157 ps |
| T825 |
/workspace/coverage/default/7.sram_ctrl_smoke.1256437709 |
|
|
Jul 04 07:15:25 PM PDT 24 |
Jul 04 07:16:47 PM PDT 24 |
672615147 ps |
| T826 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.367160891 |
|
|
Jul 04 07:16:35 PM PDT 24 |
Jul 04 07:25:59 PM PDT 24 |
6663166396 ps |
| T827 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2387858064 |
|
|
Jul 04 07:17:19 PM PDT 24 |
Jul 04 07:22:07 PM PDT 24 |
4156694248 ps |
| T828 |
/workspace/coverage/default/45.sram_ctrl_smoke.4273218440 |
|
|
Jul 04 07:19:24 PM PDT 24 |
Jul 04 07:19:40 PM PDT 24 |
2729113487 ps |
| T829 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1093776945 |
|
|
Jul 04 07:15:08 PM PDT 24 |
Jul 04 07:24:25 PM PDT 24 |
2540707612 ps |
| T830 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2330135052 |
|
|
Jul 04 07:18:35 PM PDT 24 |
Jul 04 07:18:36 PM PDT 24 |
31849755 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3621016064 |
|
|
Jul 04 07:15:05 PM PDT 24 |
Jul 04 07:15:07 PM PDT 24 |
52577856 ps |
| T832 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.577718955 |
|
|
Jul 04 07:16:56 PM PDT 24 |
Jul 04 07:18:00 PM PDT 24 |
122049252 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_smoke.3367573170 |
|
|
Jul 04 07:17:04 PM PDT 24 |
Jul 04 07:17:22 PM PDT 24 |
1343644280 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3590572005 |
|
|
Jul 04 07:16:06 PM PDT 24 |
Jul 04 07:16:49 PM PDT 24 |
347407184 ps |
| T835 |
/workspace/coverage/default/9.sram_ctrl_bijection.2012174290 |
|
|
Jul 04 07:15:28 PM PDT 24 |
Jul 04 07:16:03 PM PDT 24 |
6066112163 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3847398623 |
|
|
Jul 04 07:17:19 PM PDT 24 |
Jul 04 07:17:20 PM PDT 24 |
55304789 ps |
| T837 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.175447948 |
|
|
Jul 04 07:15:36 PM PDT 24 |
Jul 04 07:15:44 PM PDT 24 |
865087617 ps |
| T838 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2450776417 |
|
|
Jul 04 07:15:46 PM PDT 24 |
Jul 04 07:15:50 PM PDT 24 |
634954268 ps |
| T839 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1653951611 |
|
|
Jul 04 07:15:32 PM PDT 24 |
Jul 04 07:15:33 PM PDT 24 |
49483513 ps |
| T840 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1621669238 |
|
|
Jul 04 07:17:39 PM PDT 24 |
Jul 04 07:22:50 PM PDT 24 |
4196934752 ps |
| T841 |
/workspace/coverage/default/40.sram_ctrl_smoke.2670556732 |
|
|
Jul 04 07:18:30 PM PDT 24 |
Jul 04 07:20:42 PM PDT 24 |
662751684 ps |
| T842 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.435171092 |
|
|
Jul 04 07:16:10 PM PDT 24 |
Jul 04 07:16:14 PM PDT 24 |
815092144 ps |
| T843 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2087266126 |
|
|
Jul 04 07:16:56 PM PDT 24 |
Jul 04 07:18:02 PM PDT 24 |
122132645 ps |
| T844 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3361512460 |
|
|
Jul 04 07:16:39 PM PDT 24 |
Jul 04 07:17:47 PM PDT 24 |
442066564 ps |
| T845 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3178154313 |
|
|
Jul 04 07:15:46 PM PDT 24 |
Jul 04 07:15:53 PM PDT 24 |
755002246 ps |
| T846 |
/workspace/coverage/default/21.sram_ctrl_regwen.2939120439 |
|
|
Jul 04 07:16:20 PM PDT 24 |
Jul 04 07:33:34 PM PDT 24 |
15760004152 ps |
| T847 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2114591839 |
|
|
Jul 04 07:15:50 PM PDT 24 |
Jul 04 07:17:24 PM PDT 24 |
259003135 ps |
| T848 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1546107376 |
|
|
Jul 04 07:15:31 PM PDT 24 |
Jul 04 07:15:47 PM PDT 24 |
948883885 ps |
| T849 |
/workspace/coverage/default/30.sram_ctrl_smoke.3517375352 |
|
|
Jul 04 07:17:18 PM PDT 24 |
Jul 04 07:19:59 PM PDT 24 |
1379051903 ps |
| T850 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.1346064622 |
|
|
Jul 04 07:16:42 PM PDT 24 |
Jul 04 07:17:13 PM PDT 24 |
93011495 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_partial_access.672719967 |
|
|
Jul 04 07:15:51 PM PDT 24 |
Jul 04 07:15:53 PM PDT 24 |
50548498 ps |
| T852 |
/workspace/coverage/default/20.sram_ctrl_regwen.2888130149 |
|
|
Jul 04 07:16:13 PM PDT 24 |
Jul 04 07:35:34 PM PDT 24 |
106268827513 ps |
| T853 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1949690989 |
|
|
Jul 04 07:18:59 PM PDT 24 |
Jul 04 07:19:06 PM PDT 24 |
475427403 ps |
| T854 |
/workspace/coverage/default/23.sram_ctrl_executable.2336650989 |
|
|
Jul 04 07:16:24 PM PDT 24 |
Jul 04 07:27:02 PM PDT 24 |
7028088339 ps |
| T855 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2106075723 |
|
|
Jul 04 07:17:20 PM PDT 24 |
Jul 04 07:17:27 PM PDT 24 |
996988020 ps |
| T856 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1511580440 |
|
|
Jul 04 07:17:59 PM PDT 24 |
Jul 04 07:21:32 PM PDT 24 |
2980135198 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_bijection.4115261393 |
|
|
Jul 04 07:16:08 PM PDT 24 |
Jul 04 07:16:54 PM PDT 24 |
709458298 ps |
| T858 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1955462671 |
|
|
Jul 04 07:15:06 PM PDT 24 |
Jul 04 09:17:00 PM PDT 24 |
565545185801 ps |
| T859 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3009552960 |
|
|
Jul 04 07:19:17 PM PDT 24 |
Jul 04 07:19:23 PM PDT 24 |
347629237 ps |
| T860 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3141970312 |
|
|
Jul 04 07:18:22 PM PDT 24 |
Jul 04 07:18:30 PM PDT 24 |
578598959 ps |
| T861 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3151968489 |
|
|
Jul 04 07:17:20 PM PDT 24 |
Jul 04 07:17:43 PM PDT 24 |
324423322 ps |
| T862 |
/workspace/coverage/default/31.sram_ctrl_bijection.2372903660 |
|
|
Jul 04 07:17:18 PM PDT 24 |
Jul 04 07:18:41 PM PDT 24 |
7499959094 ps |
| T863 |
/workspace/coverage/default/18.sram_ctrl_regwen.1368005726 |
|
|
Jul 04 07:16:05 PM PDT 24 |
Jul 04 07:31:24 PM PDT 24 |
46060510849 ps |
| T864 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1682693959 |
|
|
Jul 04 07:16:09 PM PDT 24 |
Jul 04 07:30:55 PM PDT 24 |
14097287411 ps |
| T865 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1568563850 |
|
|
Jul 04 07:18:29 PM PDT 24 |
Jul 04 07:18:35 PM PDT 24 |
288104067 ps |
| T866 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.343319018 |
|
|
Jul 04 07:17:24 PM PDT 24 |
Jul 04 07:17:31 PM PDT 24 |
355567820 ps |
| T867 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.263504591 |
|
|
Jul 04 07:16:52 PM PDT 24 |
Jul 04 07:16:59 PM PDT 24 |
691049700 ps |
| T868 |
/workspace/coverage/default/42.sram_ctrl_regwen.982645353 |
|
|
Jul 04 07:19:00 PM PDT 24 |
Jul 04 07:45:09 PM PDT 24 |
233274481572 ps |
| T869 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1400429470 |
|
|
Jul 04 07:16:05 PM PDT 24 |
Jul 04 07:16:11 PM PDT 24 |
668910155 ps |
| T870 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1656945259 |
|
|
Jul 04 07:15:25 PM PDT 24 |
Jul 04 07:30:02 PM PDT 24 |
6762977917 ps |
| T871 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2743257790 |
|
|
Jul 04 07:15:45 PM PDT 24 |
Jul 04 07:16:06 PM PDT 24 |
665857336 ps |
| T872 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.4047135346 |
|
|
Jul 04 07:15:39 PM PDT 24 |
Jul 04 07:37:19 PM PDT 24 |
4285205815 ps |
| T873 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1759733338 |
|
|
Jul 04 07:17:25 PM PDT 24 |
Jul 04 07:19:02 PM PDT 24 |
189665437 ps |
| T874 |
/workspace/coverage/default/46.sram_ctrl_bijection.3282880854 |
|
|
Jul 04 07:19:29 PM PDT 24 |
Jul 04 07:20:25 PM PDT 24 |
875286649 ps |
| T875 |
/workspace/coverage/default/2.sram_ctrl_alert_test.588784688 |
|
|
Jul 04 07:15:07 PM PDT 24 |
Jul 04 07:15:08 PM PDT 24 |
33541703 ps |
| T876 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2482312342 |
|
|
Jul 04 07:18:16 PM PDT 24 |
Jul 04 07:33:26 PM PDT 24 |
12093506186 ps |
| T877 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1419754687 |
|
|
Jul 04 07:17:44 PM PDT 24 |
Jul 04 07:27:24 PM PDT 24 |
4006628693 ps |
| T878 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2007044149 |
|
|
Jul 04 07:18:30 PM PDT 24 |
Jul 04 07:21:55 PM PDT 24 |
24783008973 ps |
| T879 |
/workspace/coverage/default/22.sram_ctrl_executable.3429207188 |
|
|
Jul 04 07:16:19 PM PDT 24 |
Jul 04 07:23:30 PM PDT 24 |
8428396294 ps |
| T880 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3696903941 |
|
|
Jul 04 07:16:06 PM PDT 24 |
Jul 04 07:16:08 PM PDT 24 |
148889734 ps |
| T881 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1281954906 |
|
|
Jul 04 07:18:53 PM PDT 24 |
Jul 04 07:21:04 PM PDT 24 |
131871697 ps |
| T882 |
/workspace/coverage/default/24.sram_ctrl_stress_all.2054005166 |
|
|
Jul 04 07:16:32 PM PDT 24 |
Jul 04 08:59:50 PM PDT 24 |
281969995784 ps |
| T883 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.404788773 |
|
|
Jul 04 07:17:17 PM PDT 24 |
Jul 04 07:30:44 PM PDT 24 |
77233818706 ps |
| T884 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1474068534 |
|
|
Jul 04 07:16:22 PM PDT 24 |
Jul 04 07:21:55 PM PDT 24 |
13532335535 ps |
| T885 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2353385956 |
|
|
Jul 04 07:15:01 PM PDT 24 |
Jul 04 07:15:47 PM PDT 24 |
477756056 ps |
| T95 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.454402389 |
|
|
Jul 04 07:15:50 PM PDT 24 |
Jul 04 07:15:55 PM PDT 24 |
113201820 ps |
| T886 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3327691300 |
|
|
Jul 04 07:17:17 PM PDT 24 |
Jul 04 08:28:09 PM PDT 24 |
45718741672 ps |
| T887 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2590035000 |
|
|
Jul 04 07:16:26 PM PDT 24 |
Jul 04 07:20:40 PM PDT 24 |
2603021907 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1686436269 |
|
|
Jul 04 07:18:01 PM PDT 24 |
Jul 04 07:18:29 PM PDT 24 |
19968788941 ps |
| T889 |
/workspace/coverage/default/33.sram_ctrl_partial_access.352809770 |
|
|
Jul 04 07:17:34 PM PDT 24 |
Jul 04 07:19:54 PM PDT 24 |
791842908 ps |
| T890 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.817041859 |
|
|
Jul 04 07:18:00 PM PDT 24 |
Jul 04 07:21:28 PM PDT 24 |
2208117770 ps |
| T891 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1243734262 |
|
|
Jul 04 07:16:55 PM PDT 24 |
Jul 04 07:22:09 PM PDT 24 |
4343298513 ps |
| T892 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1713197260 |
|
|
Jul 04 07:18:49 PM PDT 24 |
Jul 04 07:27:29 PM PDT 24 |
18641581043 ps |
| T893 |
/workspace/coverage/default/34.sram_ctrl_regwen.250654576 |
|
|
Jul 04 07:17:49 PM PDT 24 |
Jul 04 07:38:57 PM PDT 24 |
14523773028 ps |
| T894 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1025339324 |
|
|
Jul 04 07:16:20 PM PDT 24 |
Jul 04 07:16:24 PM PDT 24 |
588485966 ps |
| T895 |
/workspace/coverage/default/7.sram_ctrl_bijection.3573944186 |
|
|
Jul 04 07:15:26 PM PDT 24 |
Jul 04 07:16:36 PM PDT 24 |
4690737343 ps |
| T896 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.666443652 |
|
|
Jul 04 07:17:41 PM PDT 24 |
Jul 04 07:42:53 PM PDT 24 |
21972222263 ps |
| T897 |
/workspace/coverage/default/15.sram_ctrl_regwen.1910542822 |
|
|
Jul 04 07:15:50 PM PDT 24 |
Jul 04 07:36:33 PM PDT 24 |
79746157790 ps |
| T898 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.362212857 |
|
|
Jul 04 07:15:26 PM PDT 24 |
Jul 04 07:15:39 PM PDT 24 |
926344118 ps |
| T899 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1738329652 |
|
|
Jul 04 07:16:52 PM PDT 24 |
Jul 04 07:16:56 PM PDT 24 |
114514093 ps |
| T900 |
/workspace/coverage/default/32.sram_ctrl_partial_access.4122902868 |
|
|
Jul 04 07:17:29 PM PDT 24 |
Jul 04 07:17:49 PM PDT 24 |
1014721382 ps |
| T901 |
/workspace/coverage/default/37.sram_ctrl_partial_access.387306303 |
|
|
Jul 04 07:18:08 PM PDT 24 |
Jul 04 07:18:22 PM PDT 24 |
240381070 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2371236440 |
|
|
Jul 04 07:19:15 PM PDT 24 |
Jul 04 07:22:45 PM PDT 24 |
29809181271 ps |
| T903 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2773699271 |
|
|
Jul 04 07:18:16 PM PDT 24 |
Jul 04 07:20:03 PM PDT 24 |
2827465739 ps |
| T904 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.812447390 |
|
|
Jul 04 07:15:00 PM PDT 24 |
Jul 04 07:21:03 PM PDT 24 |
9277619253 ps |
| T905 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.163782851 |
|
|
Jul 04 07:15:36 PM PDT 24 |
Jul 04 07:42:51 PM PDT 24 |
14686642322 ps |
| T906 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1643427371 |
|
|
Jul 04 07:15:45 PM PDT 24 |
Jul 04 08:18:28 PM PDT 24 |
22946832846 ps |
| T907 |
/workspace/coverage/default/44.sram_ctrl_executable.3735032498 |
|
|
Jul 04 07:19:15 PM PDT 24 |
Jul 04 07:38:31 PM PDT 24 |
12566540531 ps |
| T908 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3698224036 |
|
|
Jul 04 07:16:19 PM PDT 24 |
Jul 04 07:18:11 PM PDT 24 |
146423675 ps |
| T909 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2808995312 |
|
|
Jul 04 07:18:39 PM PDT 24 |
Jul 04 07:24:17 PM PDT 24 |
2058876286 ps |
| T910 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2462613786 |
|
|
Jul 04 07:15:24 PM PDT 24 |
Jul 04 07:15:39 PM PDT 24 |
1773994583 ps |
| T911 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.287163118 |
|
|
Jul 04 07:16:15 PM PDT 24 |
Jul 04 07:34:40 PM PDT 24 |
36921575538 ps |
| T912 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3371879991 |
|
|
Jul 04 07:15:29 PM PDT 24 |
Jul 04 07:15:33 PM PDT 24 |
115309005 ps |
| T913 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3627781031 |
|
|
Jul 04 07:18:58 PM PDT 24 |
Jul 04 07:34:04 PM PDT 24 |
13610973930 ps |
| T914 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.724717291 |
|
|
Jul 04 07:18:31 PM PDT 24 |
Jul 04 07:18:32 PM PDT 24 |
102158339 ps |
| T915 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2083506834 |
|
|
Jul 04 07:18:54 PM PDT 24 |
Jul 04 07:18:59 PM PDT 24 |
62493721 ps |
| T916 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1438731056 |
|
|
Jul 04 07:17:32 PM PDT 24 |
Jul 04 07:17:35 PM PDT 24 |
916098460 ps |
| T917 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3918001447 |
|
|
Jul 04 07:15:53 PM PDT 24 |
Jul 04 07:20:14 PM PDT 24 |
3580236959 ps |
| T918 |
/workspace/coverage/default/20.sram_ctrl_bijection.1471830542 |
|
|
Jul 04 07:16:15 PM PDT 24 |
Jul 04 07:16:37 PM PDT 24 |
4390013656 ps |
| T919 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1974959976 |
|
|
Jul 04 07:19:54 PM PDT 24 |
Jul 04 07:19:55 PM PDT 24 |
85033510 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.3173130411 |
|
|
Jul 04 07:17:39 PM PDT 24 |
Jul 04 07:19:25 PM PDT 24 |
714912262 ps |
| T921 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1861613119 |
|
|
Jul 04 07:18:53 PM PDT 24 |
Jul 04 07:25:03 PM PDT 24 |
5021608049 ps |
| T922 |
/workspace/coverage/default/30.sram_ctrl_executable.320435770 |
|
|
Jul 04 07:17:18 PM PDT 24 |
Jul 04 07:36:30 PM PDT 24 |
35743460508 ps |
| T923 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3707207731 |
|
|
Jul 04 07:16:51 PM PDT 24 |
Jul 04 07:16:52 PM PDT 24 |
79088195 ps |
| T924 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1092373490 |
|
|
Jul 04 07:18:16 PM PDT 24 |
Jul 04 07:20:19 PM PDT 24 |
152667091 ps |
| T925 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2837006063 |
|
|
Jul 04 07:16:25 PM PDT 24 |
Jul 04 07:19:45 PM PDT 24 |
10033186040 ps |
| T926 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3406391015 |
|
|
Jul 04 07:19:31 PM PDT 24 |
Jul 04 07:23:43 PM PDT 24 |
6430182904 ps |
| T927 |
/workspace/coverage/default/0.sram_ctrl_executable.2345589315 |
|
|
Jul 04 07:15:00 PM PDT 24 |
Jul 04 07:25:17 PM PDT 24 |
9050662774 ps |
| T928 |
/workspace/coverage/default/39.sram_ctrl_bijection.3023630461 |
|
|
Jul 04 07:18:22 PM PDT 24 |
Jul 04 07:19:22 PM PDT 24 |
3948698603 ps |
| T929 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1825218410 |
|
|
Jul 04 07:16:05 PM PDT 24 |
Jul 04 08:27:31 PM PDT 24 |
157272545894 ps |
| T930 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3574649684 |
|
|
Jul 04 07:20:02 PM PDT 24 |
Jul 04 07:20:06 PM PDT 24 |
102351051 ps |
| T931 |
/workspace/coverage/default/41.sram_ctrl_executable.2813375800 |
|
|
Jul 04 07:18:43 PM PDT 24 |
Jul 04 07:36:45 PM PDT 24 |
12819829798 ps |
| T932 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2688301758 |
|
|
Jul 04 07:17:04 PM PDT 24 |
Jul 04 07:17:24 PM PDT 24 |
138387302 ps |
| T933 |
/workspace/coverage/default/21.sram_ctrl_executable.1801800325 |
|
|
Jul 04 07:16:19 PM PDT 24 |
Jul 04 07:28:56 PM PDT 24 |
27090097409 ps |
| T934 |
/workspace/coverage/default/32.sram_ctrl_bijection.2289212801 |
|
|
Jul 04 07:17:24 PM PDT 24 |
Jul 04 07:17:51 PM PDT 24 |
5355689684 ps |
| T935 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3919995273 |
|
|
Jul 04 07:18:00 PM PDT 24 |
Jul 04 08:30:42 PM PDT 24 |
131567761052 ps |
| T936 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2742770924 |
|
|
Jul 04 07:19:15 PM PDT 24 |
Jul 04 07:19:16 PM PDT 24 |
52477942 ps |
| T937 |
/workspace/coverage/default/26.sram_ctrl_partial_access.113357340 |
|
|
Jul 04 07:16:52 PM PDT 24 |
Jul 04 07:17:03 PM PDT 24 |
361457793 ps |
| T61 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1628044628 |
|
|
Jul 04 06:54:36 PM PDT 24 |
Jul 04 06:54:38 PM PDT 24 |
273931908 ps |
| T68 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1394741094 |
|
|
Jul 04 06:54:24 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
131855548 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2995859122 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:14 PM PDT 24 |
48970880 ps |
| T79 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1025673907 |
|
|
Jul 04 06:54:25 PM PDT 24 |
Jul 04 06:54:26 PM PDT 24 |
18194458 ps |
| T938 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3604631374 |
|
|
Jul 04 06:54:31 PM PDT 24 |
Jul 04 06:54:34 PM PDT 24 |
354521968 ps |
| T80 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2597277238 |
|
|
Jul 04 06:54:04 PM PDT 24 |
Jul 04 06:54:05 PM PDT 24 |
20797049 ps |
| T62 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1241855064 |
|
|
Jul 04 06:54:36 PM PDT 24 |
Jul 04 06:54:38 PM PDT 24 |
219377219 ps |
| T104 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1059781191 |
|
|
Jul 04 06:54:30 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
25064564 ps |
| T939 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3986490297 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:19 PM PDT 24 |
1383804483 ps |
| T940 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4261172210 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:24 PM PDT 24 |
119979088 ps |
| T941 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2457004228 |
|
|
Jul 04 06:54:24 PM PDT 24 |
Jul 04 06:54:27 PM PDT 24 |
197864601 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2551624523 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
169902175 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2595615468 |
|
|
Jul 04 06:54:36 PM PDT 24 |
Jul 04 06:54:39 PM PDT 24 |
101758994 ps |
| T81 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4241090413 |
|
|
Jul 04 06:54:32 PM PDT 24 |
Jul 04 06:54:33 PM PDT 24 |
253387302 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2283807759 |
|
|
Jul 04 06:54:20 PM PDT 24 |
Jul 04 06:54:22 PM PDT 24 |
224608525 ps |
| T122 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1907587649 |
|
|
Jul 04 06:54:29 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
105325243 ps |
| T105 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3605893915 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:27 PM PDT 24 |
49861763 ps |
| T120 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4279504110 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:15 PM PDT 24 |
105454455 ps |
| T83 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1774569285 |
|
|
Jul 04 06:54:24 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
65664978 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1072682839 |
|
|
Jul 04 06:54:14 PM PDT 24 |
Jul 04 06:54:16 PM PDT 24 |
35542519 ps |
| T106 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3556367470 |
|
|
Jul 04 06:54:33 PM PDT 24 |
Jul 04 06:54:35 PM PDT 24 |
251880903 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3828610175 |
|
|
Jul 04 06:54:25 PM PDT 24 |
Jul 04 06:54:26 PM PDT 24 |
39414173 ps |
| T107 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3140592613 |
|
|
Jul 04 06:54:31 PM PDT 24 |
Jul 04 06:54:32 PM PDT 24 |
17069155 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3426112660 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:23 PM PDT 24 |
163566241 ps |
| T945 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4210979481 |
|
|
Jul 04 06:54:32 PM PDT 24 |
Jul 04 06:54:34 PM PDT 24 |
207849346 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4260988191 |
|
|
Jul 04 06:54:32 PM PDT 24 |
Jul 04 06:54:33 PM PDT 24 |
51254465 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4178447653 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:28 PM PDT 24 |
402026597 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2177400880 |
|
|
Jul 04 06:54:15 PM PDT 24 |
Jul 04 06:54:16 PM PDT 24 |
46877338 ps |
| T86 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1081728125 |
|
|
Jul 04 06:54:24 PM PDT 24 |
Jul 04 06:54:27 PM PDT 24 |
220400441 ps |
| T948 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1645237511 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
24117308 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.812187447 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:14 PM PDT 24 |
12853854 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1846046936 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:26 PM PDT 24 |
1382905119 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3759256565 |
|
|
Jul 04 06:54:14 PM PDT 24 |
Jul 04 06:54:15 PM PDT 24 |
25775944 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3357447292 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:24 PM PDT 24 |
16209641 ps |
| T950 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1724241037 |
|
|
Jul 04 06:54:38 PM PDT 24 |
Jul 04 06:54:39 PM PDT 24 |
34874497 ps |
| T121 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.296805530 |
|
|
Jul 04 06:54:33 PM PDT 24 |
Jul 04 06:54:34 PM PDT 24 |
298878431 ps |
| T951 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.912063414 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:23 PM PDT 24 |
13504756 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1495808458 |
|
|
Jul 04 06:54:28 PM PDT 24 |
Jul 04 06:54:29 PM PDT 24 |
36352632 ps |
| T91 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.889621504 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
1578566826 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1311781172 |
|
|
Jul 04 06:54:24 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
14201621 ps |
| T92 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2926532817 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
1497776042 ps |
| T127 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1262354357 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:27 PM PDT 24 |
130584452 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.49687446 |
|
|
Jul 04 06:54:27 PM PDT 24 |
Jul 04 06:54:29 PM PDT 24 |
113613006 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1977782433 |
|
|
Jul 04 06:54:05 PM PDT 24 |
Jul 04 06:54:08 PM PDT 24 |
228274242 ps |
| T96 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4268389627 |
|
|
Jul 04 06:54:25 PM PDT 24 |
Jul 04 06:54:28 PM PDT 24 |
489376195 ps |
| T97 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3377807914 |
|
|
Jul 04 06:54:33 PM PDT 24 |
Jul 04 06:54:34 PM PDT 24 |
27604374 ps |
| T956 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.921588806 |
|
|
Jul 04 06:54:29 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
40690812 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1566220097 |
|
|
Jul 04 06:54:37 PM PDT 24 |
Jul 04 06:54:41 PM PDT 24 |
478294675 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2269940273 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:22 PM PDT 24 |
24915457 ps |
| T959 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1275444923 |
|
|
Jul 04 06:54:29 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
126765117 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1899500937 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:23 PM PDT 24 |
46039848 ps |
| T98 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2097138672 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
418169934 ps |
| T124 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.715346153 |
|
|
Jul 04 06:54:25 PM PDT 24 |
Jul 04 06:54:28 PM PDT 24 |
644570388 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1796269031 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:22 PM PDT 24 |
19845359 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2166225177 |
|
|
Jul 04 06:54:32 PM PDT 24 |
Jul 04 06:54:33 PM PDT 24 |
27993955 ps |
| T99 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.812812993 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
1492174927 ps |
| T963 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1466723941 |
|
|
Jul 04 06:54:14 PM PDT 24 |
Jul 04 06:54:15 PM PDT 24 |
34154321 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1080157127 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:16 PM PDT 24 |
2229992251 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1444156623 |
|
|
Jul 04 06:54:05 PM PDT 24 |
Jul 04 06:54:08 PM PDT 24 |
436240718 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1515061062 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:14 PM PDT 24 |
10740294 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2942134441 |
|
|
Jul 04 06:54:29 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
45882553 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.298298296 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:22 PM PDT 24 |
102322806 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2170624594 |
|
|
Jul 04 06:54:29 PM PDT 24 |
Jul 04 06:54:31 PM PDT 24 |
44549660 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3352791494 |
|
|
Jul 04 06:54:25 PM PDT 24 |
Jul 04 06:54:31 PM PDT 24 |
894638391 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1000652361 |
|
|
Jul 04 06:54:24 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
71775904 ps |
| T972 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3876905955 |
|
|
Jul 04 06:54:25 PM PDT 24 |
Jul 04 06:54:27 PM PDT 24 |
35483843 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.811643360 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:29 PM PDT 24 |
903606947 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2943466745 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:15 PM PDT 24 |
18397252 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.643777076 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:26 PM PDT 24 |
1596237897 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.552185391 |
|
|
Jul 04 06:54:29 PM PDT 24 |
Jul 04 06:54:30 PM PDT 24 |
41973477 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3108905299 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:23 PM PDT 24 |
59276393 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3239704954 |
|
|
Jul 04 06:54:20 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
146776082 ps |
| T979 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2311881520 |
|
|
Jul 04 06:54:37 PM PDT 24 |
Jul 04 06:54:37 PM PDT 24 |
23672508 ps |
| T100 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1858148124 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:24 PM PDT 24 |
285458016 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3731884432 |
|
|
Jul 04 06:54:37 PM PDT 24 |
Jul 04 06:54:38 PM PDT 24 |
15697773 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.160580483 |
|
|
Jul 04 06:54:27 PM PDT 24 |
Jul 04 06:54:29 PM PDT 24 |
336757199 ps |
| T130 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3054660730 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:24 PM PDT 24 |
283780974 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.78881976 |
|
|
Jul 04 06:54:12 PM PDT 24 |
Jul 04 06:54:14 PM PDT 24 |
79364058 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.636840304 |
|
|
Jul 04 06:54:06 PM PDT 24 |
Jul 04 06:54:07 PM PDT 24 |
149122943 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1790111701 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:24 PM PDT 24 |
77202889 ps |
| T984 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2131234112 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
35967172 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1404766780 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:15 PM PDT 24 |
77567234 ps |
| T986 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2524720498 |
|
|
Jul 04 06:54:05 PM PDT 24 |
Jul 04 06:54:06 PM PDT 24 |
29397582 ps |
| T102 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.922942837 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:15 PM PDT 24 |
56541505 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2209112418 |
|
|
Jul 04 06:54:33 PM PDT 24 |
Jul 04 06:54:36 PM PDT 24 |
36928042 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.465900252 |
|
|
Jul 04 06:54:07 PM PDT 24 |
Jul 04 06:54:08 PM PDT 24 |
31505549 ps |
| T989 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2089080518 |
|
|
Jul 04 06:54:26 PM PDT 24 |
Jul 04 06:54:27 PM PDT 24 |
48729648 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3620060004 |
|
|
Jul 04 06:54:12 PM PDT 24 |
Jul 04 06:54:14 PM PDT 24 |
32943665 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1710845914 |
|
|
Jul 04 06:54:06 PM PDT 24 |
Jul 04 06:54:08 PM PDT 24 |
79576680 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2680485829 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:17 PM PDT 24 |
2341727689 ps |
| T123 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.348934257 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:25 PM PDT 24 |
211353698 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3513648974 |
|
|
Jul 04 06:54:32 PM PDT 24 |
Jul 04 06:54:35 PM PDT 24 |
378076804 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1114862127 |
|
|
Jul 04 06:54:22 PM PDT 24 |
Jul 04 06:54:24 PM PDT 24 |
495195064 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.811339413 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:14 PM PDT 24 |
49631504 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.373342609 |
|
|
Jul 04 06:54:05 PM PDT 24 |
Jul 04 06:54:06 PM PDT 24 |
19786026 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.880055745 |
|
|
Jul 04 06:54:13 PM PDT 24 |
Jul 04 06:54:16 PM PDT 24 |
688335383 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.352155856 |
|
|
Jul 04 06:54:14 PM PDT 24 |
Jul 04 06:54:16 PM PDT 24 |
509877361 ps |
| T997 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2347954238 |
|
|
Jul 04 06:54:27 PM PDT 24 |
Jul 04 06:54:29 PM PDT 24 |
137441240 ps |
| T125 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1416386234 |
|
|
Jul 04 06:54:05 PM PDT 24 |
Jul 04 06:54:07 PM PDT 24 |
174232812 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1152054314 |
|
|
Jul 04 06:54:28 PM PDT 24 |
Jul 04 06:54:31 PM PDT 24 |
1537146512 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2833960999 |
|
|
Jul 04 06:54:06 PM PDT 24 |
Jul 04 06:54:10 PM PDT 24 |
216909429 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.646092785 |
|
|
Jul 04 06:54:23 PM PDT 24 |
Jul 04 06:54:26 PM PDT 24 |
235789856 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1808402814 |
|
|
Jul 04 06:54:35 PM PDT 24 |
Jul 04 06:54:41 PM PDT 24 |
373911713 ps |
| T1002 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3483327680 |
|
|
Jul 04 06:54:35 PM PDT 24 |
Jul 04 06:54:35 PM PDT 24 |
105146871 ps |
| T1003 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1217862372 |
|
|
Jul 04 06:54:21 PM PDT 24 |
Jul 04 06:54:22 PM PDT 24 |
188328358 ps |