Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13870669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59004818

1

T1

6691

T3

275843

T4

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36329865	1			T1	2441		T3	148761		T4	392
values[0x0]	16888779	1			T1	2284		T3	72362		T4	205
values[0x1]	19656843	1			T1	2304		T3	76798		T4	398

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6909065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65966422

1

T1

6844

T3

286901

T4

455

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	311897	1			T1	31		T3	347		T8	88
valid_sources[0x01]	270023	1			T1	18		T8	116		T11	13
valid_sources[0x02]	288488	1			T1	16		T3	345		T8	116
valid_sources[0x03]	269232	1			T1	38		T3	159		T8	106
valid_sources[0x04]	273856	1			T1	25		T3	141		T8	134
valid_sources[0x05]	395505	1			T1	35		T3	605		T8	158
valid_sources[0x06]	318372	1			T1	19		T3	161		T8	140
valid_sources[0x07]	254811	1			T1	19		T3	1445		T4	45
valid_sources[0x08]	290825	1			T1	25		T8	124		T11	8
valid_sources[0x09]	293224	1			T1	14		T3	213		T8	139
valid_sources[0x0a]	300088	1			T1	34		T3	900		T8	173
valid_sources[0x0b]	269047	1			T1	21		T3	988		T8	137
valid_sources[0x0c]	277103	1			T1	31		T3	244		T8	210
valid_sources[0x0d]	274357	1			T1	21		T3	1050		T8	180
valid_sources[0x0e]	262490	1			T1	19		T3	326		T8	177
valid_sources[0x0f]	282653	1			T1	22		T3	1407		T8	111
valid_sources[0x10]	277955	1			T1	22		T3	55		T8	115
valid_sources[0x11]	342336	1			T1	48		T3	251		T8	148
valid_sources[0x12]	250401	1			T1	26		T3	110		T4	111
valid_sources[0x13]	245965	1			T1	26		T3	339		T8	148
valid_sources[0x14]	266579	1			T1	34		T3	550		T8	233
valid_sources[0x15]	279984	1			T1	37		T3	371		T8	148
valid_sources[0x16]	348781	1			T1	25		T3	1009		T8	146
valid_sources[0x17]	313777	1			T1	23		T3	583		T8	142
valid_sources[0x18]	251916	1			T1	33		T3	520		T8	80
valid_sources[0x19]	272753	1			T1	31		T3	595		T8	200
valid_sources[0x1a]	251520	1			T1	36		T3	3593		T8	148
valid_sources[0x1b]	288094	1			T1	32		T3	561		T8	144
valid_sources[0x1c]	285215	1			T1	23		T3	201		T8	129
valid_sources[0x1d]	246587	1			T1	21		T3	265		T8	154
valid_sources[0x1e]	316253	1			T1	31		T3	656		T8	94
valid_sources[0x1f]	269974	1			T1	32		T3	385		T4	15
valid_sources[0x20]	289020	1			T1	32		T3	430		T8	103
valid_sources[0x21]	277819	1			T1	30		T3	1271		T8	174
valid_sources[0x22]	278739	1			T1	23		T3	142		T8	139
valid_sources[0x23]	273982	1			T1	31		T3	293		T8	139
valid_sources[0x24]	347242	1			T1	39		T3	632		T8	110
valid_sources[0x25]	258342	1			T1	24		T3	979		T8	187
valid_sources[0x26]	289074	1			T1	33		T3	317		T8	118
valid_sources[0x27]	278556	1			T1	47		T3	411		T8	97
valid_sources[0x28]	322677	1			T1	23		T3	391		T8	174
valid_sources[0x29]	317171	1			T1	24		T3	348		T8	194
valid_sources[0x2a]	260893	1			T1	47		T3	446		T8	73
valid_sources[0x2b]	260655	1			T1	32		T3	173		T8	185
valid_sources[0x2c]	271297	1			T1	21		T3	480		T8	165
valid_sources[0x2d]	340645	1			T1	49		T3	208		T8	119
valid_sources[0x2e]	289902	1			T1	35		T3	516		T8	128
valid_sources[0x2f]	244638	1			T1	23		T3	1006		T8	86
valid_sources[0x30]	253423	1			T1	34		T3	258		T8	111
valid_sources[0x31]	285029	1			T1	32		T3	283		T4	37
valid_sources[0x32]	263161	1			T1	29		T3	236		T4	6
valid_sources[0x33]	276977	1			T1	20		T3	529		T8	195
valid_sources[0x34]	258304	1			T1	39		T3	445		T8	126
valid_sources[0x35]	258070	1			T1	33		T3	2		T8	156
valid_sources[0x36]	285584	1			T1	20		T3	149		T8	131
valid_sources[0x37]	262496	1			T1	31		T3	676		T8	149
valid_sources[0x38]	282813	1			T1	29		T3	589		T8	146
valid_sources[0x39]	321644	1			T1	32		T3	83		T8	127
valid_sources[0x3a]	275497	1			T1	26		T3	570		T8	133
valid_sources[0x3b]	277647	1			T1	18		T3	785		T8	115
valid_sources[0x3c]	257205	1			T1	40		T3	194		T4	2
valid_sources[0x3d]	262254	1			T1	23		T3	95		T8	94
valid_sources[0x3e]	267465	1			T1	36		T3	244		T8	147
valid_sources[0x3f]	279088	1			T1	23		T3	1132		T8	116
valid_sources[0x40]	272730	1			T1	35		T3	187		T4	30
valid_sources[0x41]	333905	1			T1	34		T3	548		T8	145
valid_sources[0x42]	268388	1			T1	20		T3	321		T4	14
valid_sources[0x43]	259837	1			T1	39		T3	514		T4	14
valid_sources[0x44]	255538	1			T1	11		T3	503		T8	111
valid_sources[0x45]	256074	1			T1	22		T3	2932		T8	106
valid_sources[0x46]	291278	1			T1	19		T3	513		T8	141
valid_sources[0x47]	296188	1			T1	23		T3	129		T8	79
valid_sources[0x48]	311890	1			T1	27		T3	565		T8	75
valid_sources[0x49]	276062	1			T1	19		T3	237		T8	115
valid_sources[0x4a]	303820	1			T1	20		T3	573		T8	127
valid_sources[0x4b]	266368	1			T1	18		T3	977		T8	56
valid_sources[0x4c]	269054	1			T1	23		T3	511		T4	31
valid_sources[0x4d]	368077	1			T1	20		T3	80		T8	84
valid_sources[0x4e]	245153	1			T1	26		T3	85		T4	132
valid_sources[0x4f]	250906	1			T1	26		T3	233		T8	159
valid_sources[0x50]	257040	1			T1	25		T3	669		T8	192
valid_sources[0x51]	277939	1			T1	33		T3	678		T8	139
valid_sources[0x52]	261715	1			T1	28		T3	240		T8	118
valid_sources[0x53]	260046	1			T1	32		T3	1136		T8	128
valid_sources[0x54]	297766	1			T1	18		T3	428		T8	128
valid_sources[0x55]	272737	1			T1	30		T3	663		T8	130
valid_sources[0x56]	263683	1			T1	29		T3	605		T8	173
valid_sources[0x57]	344229	1			T1	32		T3	73393		T8	115
valid_sources[0x58]	284009	1			T1	31		T3	673		T4	23
valid_sources[0x59]	260161	1			T1	21		T3	288		T8	122
valid_sources[0x5a]	278492	1			T1	27		T3	117		T8	88
valid_sources[0x5b]	270584	1			T1	21		T3	1147		T8	152
valid_sources[0x5c]	273907	1			T1	30		T3	262		T8	77
valid_sources[0x5d]	280657	1			T1	45		T3	260		T8	164
valid_sources[0x5e]	255711	1			T1	26		T3	594		T8	120
valid_sources[0x5f]	284601	1			T1	27		T3	559		T8	199
valid_sources[0x60]	279934	1			T1	15		T3	1171		T8	97
valid_sources[0x61]	255604	1			T1	29		T3	672		T8	112
valid_sources[0x62]	255441	1			T1	29		T3	611		T8	183
valid_sources[0x63]	290681	1			T1	28		T3	270		T4	41
valid_sources[0x64]	282592	1			T1	24		T3	693		T8	110
valid_sources[0x65]	289702	1			T1	27		T3	203		T8	155
valid_sources[0x66]	337870	1			T1	34		T3	197		T8	167
valid_sources[0x67]	318766	1			T1	38		T3	271		T8	129
valid_sources[0x68]	312563	1			T1	17		T3	196		T8	162
valid_sources[0x69]	254760	1			T1	28		T3	611		T8	201
valid_sources[0x6a]	348609	1			T1	29		T3	16436		T4	8
valid_sources[0x6b]	311056	1			T1	24		T3	439		T8	125
valid_sources[0x6c]	279568	1			T1	23		T3	433		T4	4
valid_sources[0x6d]	322410	1			T1	36		T3	464		T8	114
valid_sources[0x6e]	275245	1			T1	32		T3	812		T8	75
valid_sources[0x6f]	257210	1			T1	22		T3	462		T8	135
valid_sources[0x70]	276519	1			T1	27		T3	630		T8	117
valid_sources[0x71]	262551	1			T1	19		T3	12569		T8	170
valid_sources[0x72]	266080	1			T1	25		T3	531		T4	12
valid_sources[0x73]	330493	1			T1	21		T3	157		T8	189
valid_sources[0x74]	316278	1			T1	20		T3	721		T4	51
valid_sources[0x75]	323651	1			T1	30		T3	859		T8	207
valid_sources[0x76]	291697	1			T1	33		T3	700		T8	173
valid_sources[0x77]	243058	1			T1	27		T3	647		T8	170
valid_sources[0x78]	280648	1			T1	23		T3	195		T8	100
valid_sources[0x79]	272669	1			T1	30		T3	500		T8	86
valid_sources[0x7a]	332504	1			T1	29		T3	84		T8	120
valid_sources[0x7b]	280564	1			T1	22		T3	317		T8	125
valid_sources[0x7c]	271482	1			T1	16		T3	780		T8	167
valid_sources[0x7d]	256648	1			T1	37		T3	79		T8	171
valid_sources[0x7e]	306126	1			T1	34		T3	247		T8	150
valid_sources[0x7f]	268855	1			T1	25		T3	1114		T4	38
valid_sources[0x80]	305567	1			T1	27		T3	569		T8	158

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29398918

1

T1

2266

T3

137739

T4

2

values[0x0]

all_enables

biggest_size

14808083

1

T1

2238

T3

69017

T4

23

values[0x1]

all_enables

biggest_size

14797817

1

T1

2187

T3

69087

T4

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140921

1

T1

1491

T2

3

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50837	1			T1	414		T3	55		T8	500
values[0x0]	60493	1			T1	572		T2	6		T3	73
values[0x1]	65131	1			T1	606		T2	8		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149539

1

T1

1537

T2

6

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	931	1			T1	10		T3	1		T8	21
valid_sources[0x01]	734	1			T1	11		T8	8		T21	20
valid_sources[0x02]	542	1			T3	2		T8	10		T21	15
valid_sources[0x03]	585	1			T1	12		T8	11		T21	15
valid_sources[0x04]	631	1			T8	7		T21	17		T46	2
valid_sources[0x05]	785	1			T1	15		T8	4		T21	27
valid_sources[0x06]	748	1			T1	17		T11	2		T21	12
valid_sources[0x07]	717	1			T1	18		T8	4		T11	1
valid_sources[0x08]	795	1			T1	1		T3	2		T8	4
valid_sources[0x09]	463	1			T1	1		T3	2		T21	26
valid_sources[0x0a]	983	1			T1	13		T8	8		T5	1
valid_sources[0x0b]	478	1			T1	3		T3	1		T8	11
valid_sources[0x0c]	591	1			T1	2		T8	2		T21	9
valid_sources[0x0d]	545	1			T1	8		T3	1		T8	12
valid_sources[0x0e]	803	1			T1	28		T2	1		T8	9
valid_sources[0x0f]	535	1			T1	2		T3	1		T8	9
valid_sources[0x10]	679	1			T1	8		T8	12		T21	15
valid_sources[0x11]	559	1			T1	7		T3	1		T8	7
valid_sources[0x12]	663	1			T1	3		T3	2		T8	31
valid_sources[0x13]	615	1			T1	2		T8	3		T21	15
valid_sources[0x14]	1083	1			T1	11		T8	2		T21	16
valid_sources[0x15]	615	1			T1	14		T3	2		T8	4
valid_sources[0x16]	557	1			T1	10		T3	2		T8	5
valid_sources[0x17]	619	1			T1	2		T8	7		T21	20
valid_sources[0x18]	650	1			T1	12		T8	6		T21	7
valid_sources[0x19]	564	1			T1	8		T21	12		T7	12
valid_sources[0x1a]	532	1			T1	5		T3	1		T8	9
valid_sources[0x1b]	758	1			T1	8		T8	10		T21	19
valid_sources[0x1c]	838	1			T1	15		T8	5		T21	19
valid_sources[0x1d]	1006	1			T3	1		T8	6		T21	17
valid_sources[0x1e]	674	1			T3	3		T8	4		T21	16
valid_sources[0x1f]	668	1			T1	18		T3	1		T8	14
valid_sources[0x20]	489	1			T1	10		T8	12		T21	15
valid_sources[0x21]	853	1			T1	7		T3	1		T8	2
valid_sources[0x22]	476	1			T1	4		T8	1		T21	20
valid_sources[0x23]	581	1			T1	7		T3	3		T8	2
valid_sources[0x24]	981	1			T3	5		T8	10		T21	18
valid_sources[0x25]	733	1			T1	8		T8	7		T21	8
valid_sources[0x26]	738	1			T1	4		T8	11		T21	16
valid_sources[0x27]	595	1			T3	2		T8	13		T21	14
valid_sources[0x28]	564	1			T1	8		T8	10		T21	15
valid_sources[0x29]	560	1			T1	9		T8	7		T5	1
valid_sources[0x2a]	579	1			T1	4		T8	9		T21	11
valid_sources[0x2b]	741	1			T1	3		T8	3		T21	11
valid_sources[0x2c]	574	1			T1	1		T3	2		T8	8
valid_sources[0x2d]	927	1			T8	3		T21	10		T45	3
valid_sources[0x2e]	699	1			T1	9		T21	12		T61	2
valid_sources[0x2f]	518	1			T3	1		T8	12		T21	18
valid_sources[0x30]	505	1			T1	37		T3	1		T8	10
valid_sources[0x31]	818	1			T1	5		T3	1		T8	5
valid_sources[0x32]	581	1			T1	2		T3	1		T8	13
valid_sources[0x33]	739	1			T1	24		T2	1		T3	1
valid_sources[0x34]	525	1			T3	1		T8	4		T21	21
valid_sources[0x35]	770	1			T8	12		T21	17		T7	5
valid_sources[0x36]	573	1			T8	3		T21	9		T55	3
valid_sources[0x37]	553	1			T1	12		T21	10		T72	1
valid_sources[0x38]	642	1			T8	14		T21	14		T7	2
valid_sources[0x39]	977	1			T1	12		T8	7		T21	15
valid_sources[0x3a]	546	1			T1	9		T3	1		T8	10
valid_sources[0x3b]	481	1			T3	1		T8	6		T21	14
valid_sources[0x3c]	848	1			T1	22		T8	4		T21	17
valid_sources[0x3d]	731	1			T1	2		T8	10		T21	13
valid_sources[0x3e]	647	1			T3	3		T8	3		T21	30
valid_sources[0x3f]	602	1			T1	3		T3	1		T8	4
valid_sources[0x40]	803	1			T1	4		T8	3		T21	21
valid_sources[0x41]	781	1			T1	8		T3	1		T8	9
valid_sources[0x42]	644	1			T3	1		T8	19		T21	14
valid_sources[0x43]	487	1			T1	2		T8	23		T21	15
valid_sources[0x44]	552	1			T1	3		T8	8		T21	20
valid_sources[0x45]	668	1			T1	4		T8	5		T21	16
valid_sources[0x46]	812	1			T8	4		T21	18		T7	3
valid_sources[0x47]	524	1			T8	8		T21	20		T18	1
valid_sources[0x48]	608	1			T8	6		T21	7		T6	1
valid_sources[0x49]	747	1			T1	4		T8	12		T21	22
valid_sources[0x4a]	939	1			T1	3		T3	1		T8	16
valid_sources[0x4b]	682	1			T1	5		T3	1		T8	8
valid_sources[0x4c]	1169	1			T1	7		T8	4		T21	17
valid_sources[0x4d]	710	1			T1	8		T3	1		T8	6
valid_sources[0x4e]	573	1			T1	2		T8	1		T21	14
valid_sources[0x4f]	849	1			T8	12		T21	14		T46	9
valid_sources[0x50]	752	1			T1	5		T8	2		T21	21
valid_sources[0x51]	810	1			T3	1		T8	23		T21	20
valid_sources[0x52]	913	1			T1	1		T8	16		T21	22
valid_sources[0x53]	609	1			T1	2		T8	16		T21	13
valid_sources[0x54]	508	1			T1	8		T8	14		T11	1
valid_sources[0x55]	997	1			T1	1		T3	1		T8	15
valid_sources[0x56]	875	1			T1	9		T8	5		T21	18
valid_sources[0x57]	1380	1			T1	1		T8	6		T21	25
valid_sources[0x58]	792	1			T1	2		T8	4		T21	18
valid_sources[0x59]	645	1			T1	1		T8	2		T21	14
valid_sources[0x5a]	596	1			T1	5		T8	7		T21	12
valid_sources[0x5b]	641	1			T3	1		T8	9		T21	20
valid_sources[0x5c]	828	1			T1	15		T3	2		T8	7
valid_sources[0x5d]	636	1			T1	13		T3	1		T8	13
valid_sources[0x5e]	546	1			T1	1		T8	9		T21	19
valid_sources[0x5f]	666	1			T1	3		T2	1		T3	1
valid_sources[0x60]	676	1			T1	3		T3	4		T8	5
valid_sources[0x61]	694	1			T1	9		T3	2		T8	8
valid_sources[0x62]	941	1			T1	10		T8	7		T21	22
valid_sources[0x63]	463	1			T1	4		T8	16		T21	12
valid_sources[0x64]	543	1			T3	3		T8	7		T21	10
valid_sources[0x65]	619	1			T1	7		T3	2		T8	6
valid_sources[0x66]	644	1			T1	13		T8	11		T21	21
valid_sources[0x67]	517	1			T3	1		T8	5		T21	20
valid_sources[0x68]	513	1			T1	1		T3	2		T8	7
valid_sources[0x69]	725	1			T1	16		T8	5		T21	18
valid_sources[0x6a]	898	1			T1	4		T8	5		T21	22
valid_sources[0x6b]	545	1			T1	5		T3	2		T8	3
valid_sources[0x6c]	484	1			T1	8		T3	2		T8	16
valid_sources[0x6d]	610	1			T1	4		T8	10		T21	14
valid_sources[0x6e]	584	1			T8	7		T21	23		T37	1
valid_sources[0x6f]	815	1			T1	15		T8	7		T21	19
valid_sources[0x70]	616	1			T1	1		T8	2		T21	11
valid_sources[0x71]	821	1			T1	6		T2	3		T3	2
valid_sources[0x72]	751	1			T1	1		T3	2		T8	9
valid_sources[0x73]	782	1			T1	2		T3	1		T8	6
valid_sources[0x74]	926	1			T1	3		T8	20		T5	1
valid_sources[0x75]	513	1			T1	2		T3	2		T8	10
valid_sources[0x76]	776	1			T1	20		T8	10		T21	9
valid_sources[0x77]	570	1			T1	2		T21	14		T7	1
valid_sources[0x78]	1271	1			T1	3		T8	8		T21	35
valid_sources[0x79]	491	1			T1	2		T8	4		T21	10
valid_sources[0x7a]	636	1			T1	4		T8	9		T21	17
valid_sources[0x7b]	730	1			T1	3		T8	4		T21	17
valid_sources[0x7c]	560	1			T1	5		T3	1		T8	5
valid_sources[0x7d]	640	1			T8	5		T21	26		T136	3
valid_sources[0x7e]	529	1			T1	3		T8	4		T21	13
valid_sources[0x7f]	568	1			T1	12		T3	2		T8	12
valid_sources[0x80]	524	1			T1	3		T8	1		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38620

1

T1

378

T3

24

T8

463

values[0x0]

all_enables

biggest_size

52014

1

T1

562

T2

3

T3

19

values[0x1]

all_enables

biggest_size

50287

1

T1

551

T3

7

T8

724