Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13564393

1

T1

3190

T3

18957

T4

953

full_word

54025278

1

T1

6364

T3

243728

T4

42

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67589411	1			T1	9554		T3	262685		T4	995
auto[TlIntgErrCmd]	77	1			T51	3		T52	6		T53	2
auto[TlIntgErrData]	86	1			T51	3		T52	7		T53	1
auto[TlIntgErrBoth]	97	1			T51	4		T52	7		T53	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30981570

1

T1

2309

T3

115544

T4

392

auto[1]

36608101

1

T1

7245

T3

147141

T4

603

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6480194	1			T1	687		T3	8071		T4	390
auto[TlIntgErrNone]	partial	auto[1]	7083960	1			T1	2503		T3	10886		T4	563
auto[TlIntgErrNone]	full_word	auto[0]	24501260	1			T1	1622		T3	107473		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	29523997	1			T1	4742		T3	136255		T4	40
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T51	1		T52	2		T53	1
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T51	1		T52	4		T53	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T121	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T51	1		T112	1		T113	2
auto[TlIntgErrData]	partial	auto[0]	38	1			T52	3		T117	3		T112	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T51	2		T52	4		T53	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T122	1		T118	2		T123	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T51	1		T124	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T51	1		T52	2		T53	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T51	3		T52	4		T53	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T118	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T52	1		T124	1		T125	1