Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	560824	1			T1	4		T3	163		T21	5
auto[1]	10405963	1			T3	1478		T4	353		T8	5171
auto[2]	471032	1			T3	104		T21	5		T36	33
auto[3]	10322164	1			T1	1		T3	1369		T4	545

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14195135	1			T1	3		T3	2256		T4	4
auto[1]	2056373	1			T1	1		T3	314		T4	38
auto[2]	2096588	1			T1	1		T3	483		T4	46
auto[3]	3411887	1			T3	61		T4	810		T8	93

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7980951

1

T1

5

T3

3109

T4

896

auto[1]

13779032

1

T3

5

T4

2

T8

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	190059	1			T1	2		T3	131		T21	3
auto[0]	auto[0]	auto[1]	19842	1			T1	1		T3	18		T7	52
auto[0]	auto[0]	auto[2]	19848	1			T1	1		T3	13		T21	2
auto[0]	auto[0]	auto[3]	7589	1			T3	1		T36	49		T7	3
auto[0]	auto[1]	auto[0]	3085380	1			T3	1156		T8	4245		T9	2556
auto[0]	auto[1]	auto[1]	317641	1			T3	192		T4	2		T8	422
auto[0]	auto[1]	auto[2]	313845	1			T3	107		T4	13		T8	458
auto[0]	auto[1]	auto[3]	73526	1			T3	20		T4	338		T8	45
auto[0]	auto[2]	auto[0]	153176	1			T18	1392		T126	1361		T130	1033
auto[0]	auto[2]	auto[1]	16133	1			T18	135		T126	141		T130	100
auto[0]	auto[2]	auto[2]	22207	1			T3	95		T21	5		T7	351
auto[0]	auto[2]	auto[3]	6779	1			T3	9		T36	33		T7	35
auto[0]	auto[3]	auto[0]	3050236	1			T1	1		T3	965		T4	4
auto[0]	auto[3]	auto[1]	308741	1			T3	103		T4	36		T8	409
auto[0]	auto[3]	auto[2]	321263	1			T3	268		T4	32		T8	409
auto[0]	auto[3]	auto[3]	74686	1			T3	31		T4	471		T8	48
auto[1]	auto[0]	auto[0]	10797	1			T22	1		T72	172		T18	3
auto[1]	auto[0]	auto[1]	48068	1			T72	695		T92	728		T108	1
auto[1]	auto[0]	auto[2]	48268	1			T72	743		T92	770		T131	1
auto[1]	auto[0]	auto[3]	216353	1			T72	3356		T92	3502		T132	1
auto[1]	auto[1]	auto[0]	3850640	1			T3	2		T8	1		T5	3
auto[1]	auto[1]	auto[1]	668093	1			T3	1		T39	3		T22	1
auto[1]	auto[1]	auto[2]	665220	1			T5	1		T39	2		T7	1
auto[1]	auto[1]	auto[3]	1431618	1			T72	9864		T59	1		T92	10610
auto[1]	auto[2]	auto[0]	7081	1			T18	2		T126	1		T130	3
auto[1]	auto[2]	auto[1]	31246	1			T133	1		T19	1		T105	1
auto[1]	auto[2]	auto[2]	42600	1			T7	1		T72	648		T92	680
auto[1]	auto[2]	auto[3]	191810	1			T72	2937		T92	3137		T27	1
auto[1]	auto[3]	auto[0]	3847766	1			T3	2		T8	4		T9	1
auto[1]	auto[3]	auto[1]	646609	1			T8	1		T9	1		T39	6
auto[1]	auto[3]	auto[2]	663337	1			T4	1		T8	1		T39	3
auto[1]	auto[3]	auto[3]	1409526	1			T4	1		T5	1		T36	1