Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	313708665	201937	0	0
ctrl_regwen_rd_A	313708665	3601	0	0
exec_rd_A	313708665	3386	0	0
exec_regwen_rd_A	313708665	3703	0	0
readback_rd_A	313708665	2495	0	0
readback_regwen_rd_A	313708665	2441	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313708665	201937	0	0
T1	68482	2554	0	0
T2	1181	0	0	0
T3	205862	0	0	0
T4	3936	0	0	0
T5	38548	0	0	0
T8	84745	2850	0	0
T9	12024	0	0	0
T10	2746	0	0	0
T11	33395	0	0	0
T12	151304	0	0	0
T21	0	6396	0	0
T42	0	2758	0	0
T45	0	10412	0	0
T46	0	2545	0	0
T48	0	4550	0	0
T49	0	1635	0	0
T56	0	1795	0	0
T57	0	1650	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313708665	3601	0	0
T40	125482	0	0	0
T42	49381	104	0	0
T49	90859	0	0	0
T50	9096	0	0	0
T56	0	95	0	0
T95	294617	0	0	0
T97	0	300	0	0
T98	0	231	0	0
T99	0	29	0	0
T100	0	60	0	0
T101	0	401	0	0
T102	0	452	0	0
T103	0	434	0	0
T104	0	143	0	0
T105	148613	0	0	0
T106	1696	0	0	0
T107	347824	0	0	0
T108	390418	0	0	0
T109	23327	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313708665	3386	0	0
T40	125482	0	0	0
T42	49381	88	0	0
T49	90859	0	0	0
T50	9096	0	0	0
T56	0	53	0	0
T95	294617	0	0	0
T97	0	343	0	0
T98	0	214	0	0
T99	0	92	0	0
T100	0	57	0	0
T101	0	370	0	0
T102	0	433	0	0
T103	0	318	0	0
T104	0	109	0	0
T105	148613	0	0	0
T106	1696	0	0	0
T107	347824	0	0	0
T108	390418	0	0	0
T109	23327	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313708665	3703	0	0
T40	125482	0	0	0
T42	49381	133	0	0
T49	90859	0	0	0
T50	9096	0	0	0
T56	0	111	0	0
T95	294617	0	0	0
T97	0	391	0	0
T98	0	234	0	0
T99	0	84	0	0
T100	0	30	0	0
T101	0	470	0	0
T102	0	494	0	0
T103	0	410	0	0
T104	0	168	0	0
T105	148613	0	0	0
T106	1696	0	0	0
T107	347824	0	0	0
T108	390418	0	0	0
T109	23327	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313708665	2495	0	0
T40	125482	0	0	0
T42	49381	66	0	0
T49	90859	0	0	0
T50	9096	0	0	0
T56	0	75	0	0
T95	294617	0	0	0
T97	0	356	0	0
T98	0	202	0	0
T99	0	69	0	0
T100	0	41	0	0
T101	0	403	0	0
T102	0	465	0	0
T103	0	423	0	0
T104	0	147	0	0
T105	148613	0	0	0
T106	1696	0	0	0
T107	347824	0	0	0
T108	390418	0	0	0
T109	23327	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313708665	2441	0	0
T40	125482	0	0	0
T42	49381	84	0	0
T49	90859	0	0	0
T50	9096	0	0	0
T56	0	55	0	0
T95	294617	0	0	0
T97	0	376	0	0
T98	0	209	0	0
T99	0	78	0	0
T100	0	43	0	0
T101	0	293	0	0
T102	0	356	0	0
T103	0	364	0	0
T104	0	188	0	0
T105	148613	0	0	0
T106	1696	0	0	0
T107	347824	0	0	0
T108	390418	0	0	0
T109	23327	0	0	0