SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1798 | 1798 | 0 | 0 |
OutputsKnown_A | 625215220 | 624979340 | 0 | 0 |
gen_flops.OutputDelay_A | 312607610 | 312476252 | 0 | 2697 |
gen_no_flops.OutputDelay_A | 312607610 | 312489670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1798 | 1798 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
T12 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625215220 | 624979340 | 0 | 0 |
T1 | 136964 | 136778 | 0 | 0 |
T2 | 2362 | 2252 | 0 | 0 |
T3 | 411724 | 411520 | 0 | 0 |
T4 | 7872 | 7706 | 0 | 0 |
T5 | 77096 | 76960 | 0 | 0 |
T8 | 169490 | 169308 | 0 | 0 |
T9 | 24048 | 23910 | 0 | 0 |
T10 | 5492 | 5342 | 0 | 0 |
T11 | 66790 | 66690 | 0 | 0 |
T12 | 302608 | 302460 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 312607610 | 312476252 | 0 | 2697 |
T1 | 68482 | 68371 | 0 | 3 |
T2 | 1181 | 1123 | 0 | 3 |
T3 | 205862 | 205748 | 0 | 3 |
T4 | 3936 | 3850 | 0 | 3 |
T5 | 38548 | 38477 | 0 | 3 |
T8 | 84745 | 84636 | 0 | 3 |
T9 | 12024 | 11952 | 0 | 3 |
T10 | 2746 | 2668 | 0 | 3 |
T11 | 33395 | 33342 | 0 | 3 |
T12 | 151304 | 151227 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 312607610 | 312489670 | 0 | 0 |
T1 | 68482 | 68389 | 0 | 0 |
T2 | 1181 | 1126 | 0 | 0 |
T3 | 205862 | 205760 | 0 | 0 |
T4 | 3936 | 3853 | 0 | 0 |
T5 | 38548 | 38480 | 0 | 0 |
T8 | 84745 | 84654 | 0 | 0 |
T9 | 12024 | 11955 | 0 | 0 |
T10 | 2746 | 2671 | 0 | 0 |
T11 | 33395 | 33345 | 0 | 0 |
T12 | 151304 | 151230 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 899 | 899 | 0 | 0 |
OutputsKnown_A | 312607610 | 312489670 | 0 | 0 |
gen_flops.OutputDelay_A | 312607610 | 312476252 | 0 | 2697 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 899 | 899 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 312607610 | 312489670 | 0 | 0 |
T1 | 68482 | 68389 | 0 | 0 |
T2 | 1181 | 1126 | 0 | 0 |
T3 | 205862 | 205760 | 0 | 0 |
T4 | 3936 | 3853 | 0 | 0 |
T5 | 38548 | 38480 | 0 | 0 |
T8 | 84745 | 84654 | 0 | 0 |
T9 | 12024 | 11955 | 0 | 0 |
T10 | 2746 | 2671 | 0 | 0 |
T11 | 33395 | 33345 | 0 | 0 |
T12 | 151304 | 151230 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 312607610 | 312476252 | 0 | 2697 |
T1 | 68482 | 68371 | 0 | 3 |
T2 | 1181 | 1123 | 0 | 3 |
T3 | 205862 | 205748 | 0 | 3 |
T4 | 3936 | 3850 | 0 | 3 |
T5 | 38548 | 38477 | 0 | 3 |
T8 | 84745 | 84636 | 0 | 3 |
T9 | 12024 | 11952 | 0 | 3 |
T10 | 2746 | 2668 | 0 | 3 |
T11 | 33395 | 33342 | 0 | 3 |
T12 | 151304 | 151227 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 899 | 899 | 0 | 0 |
OutputsKnown_A | 312607610 | 312489670 | 0 | 0 |
gen_no_flops.OutputDelay_A | 312607610 | 312489670 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 899 | 899 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 312607610 | 312489670 | 0 | 0 |
T1 | 68482 | 68389 | 0 | 0 |
T2 | 1181 | 1126 | 0 | 0 |
T3 | 205862 | 205760 | 0 | 0 |
T4 | 3936 | 3853 | 0 | 0 |
T5 | 38548 | 38480 | 0 | 0 |
T8 | 84745 | 84654 | 0 | 0 |
T9 | 12024 | 11955 | 0 | 0 |
T10 | 2746 | 2671 | 0 | 0 |
T11 | 33395 | 33345 | 0 | 0 |
T12 | 151304 | 151230 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 312607610 | 312489670 | 0 | 0 |
T1 | 68482 | 68389 | 0 | 0 |
T2 | 1181 | 1126 | 0 | 0 |
T3 | 205862 | 205760 | 0 | 0 |
T4 | 3936 | 3853 | 0 | 0 |
T5 | 38548 | 38480 | 0 | 0 |
T8 | 84745 | 84654 | 0 | 0 |
T9 | 12024 | 11955 | 0 | 0 |
T10 | 2746 | 2671 | 0 | 0 |
T11 | 33395 | 33345 | 0 | 0 |
T12 | 151304 | 151230 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |