Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 5 | 83.33 |
Logical | 6 | 5 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T3,T8 |
ODD |
- |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T3,T8 |
ODD |
- |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
551032968 |
9113 |
0 |
0 |
T1 |
271194 |
8 |
0 |
0 |
T2 |
1181 |
0 |
0 |
0 |
T3 |
600418 |
70 |
0 |
0 |
T4 |
16399 |
1 |
0 |
0 |
T5 |
2810 |
4 |
0 |
0 |
T8 |
264834 |
9 |
0 |
0 |
T9 |
48100 |
2 |
0 |
0 |
T10 |
1483 |
1 |
0 |
0 |
T11 |
29722 |
0 |
0 |
0 |
T12 |
518755 |
8 |
0 |
0 |
T21 |
0 |
17 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
312607610 |
9112 |
0 |
0 |
T1 |
68482 |
8 |
0 |
0 |
T2 |
1181 |
0 |
0 |
0 |
T3 |
205862 |
70 |
0 |
0 |
T4 |
3936 |
1 |
0 |
0 |
T5 |
38548 |
4 |
0 |
0 |
T8 |
84745 |
9 |
0 |
0 |
T9 |
12024 |
2 |
0 |
0 |
T10 |
2746 |
1 |
0 |
0 |
T11 |
33395 |
0 |
0 |
0 |
T12 |
151304 |
8 |
0 |
0 |
T21 |
0 |
17 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_sync_reqack_data.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_prim_sync_reqack_data.u_prim_sync_reqack
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
[UNSUPPORTED] ACK can't come without REQ |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_prim_sync_reqack_data.u_prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T3,T8 |
ODD |
- |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T3,T8 |
ODD |
- |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_sync_reqack_data.u_prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
551032968 |
9113 |
0 |
0 |
T1 |
271194 |
8 |
0 |
0 |
T2 |
1181 |
0 |
0 |
0 |
T3 |
600418 |
70 |
0 |
0 |
T4 |
16399 |
1 |
0 |
0 |
T5 |
2810 |
4 |
0 |
0 |
T8 |
264834 |
9 |
0 |
0 |
T9 |
48100 |
2 |
0 |
0 |
T10 |
1483 |
1 |
0 |
0 |
T11 |
29722 |
0 |
0 |
0 |
T12 |
518755 |
8 |
0 |
0 |
T21 |
0 |
17 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
312607610 |
9112 |
0 |
0 |
T1 |
68482 |
8 |
0 |
0 |
T2 |
1181 |
0 |
0 |
0 |
T3 |
205862 |
70 |
0 |
0 |
T4 |
3936 |
1 |
0 |
0 |
T5 |
38548 |
4 |
0 |
0 |
T8 |
84745 |
9 |
0 |
0 |
T9 |
12024 |
2 |
0 |
0 |
T10 |
2746 |
1 |
0 |
0 |
T11 |
33395 |
0 |
0 |
0 |
T12 |
151304 |
8 |
0 |
0 |
T21 |
0 |
17 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |