Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14375061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57244536

1

T1

59374

T2

175250

T4

6142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35702268	1			T1	32771		T2	96493		T4	2048
values[0x0]	16516357	1			T1	15779		T2	46269		T4	2053
values[0x1]	19400972	1			T1	16838		T2	50094		T4	2041

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7163293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64456304

1

T1

62436

T2

184030

T4

6142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	272069	1			T1	240		T2	763		T4	18
valid_sources[0x01]	289282	1			T1	205		T2	733		T4	38
valid_sources[0x02]	286454	1			T1	248		T2	754		T4	11
valid_sources[0x03]	255862	1			T1	232		T2	761		T4	34
valid_sources[0x04]	300032	1			T1	240		T2	801		T4	16
valid_sources[0x05]	274706	1			T1	227		T2	750		T4	25
valid_sources[0x06]	285527	1			T1	263		T2	738		T4	27
valid_sources[0x07]	323689	1			T1	323		T2	761		T4	14
valid_sources[0x08]	261417	1			T1	204		T2	773		T4	23
valid_sources[0x09]	273731	1			T1	273		T2	727		T4	14
valid_sources[0x0a]	275665	1			T1	320		T2	755		T4	22
valid_sources[0x0b]	331457	1			T1	230		T2	797		T4	20
valid_sources[0x0c]	289426	1			T1	268		T2	724		T4	15
valid_sources[0x0d]	251660	1			T1	206		T2	764		T4	47
valid_sources[0x0e]	257691	1			T1	177		T2	758		T4	14
valid_sources[0x0f]	262829	1			T1	201		T2	732		T4	38
valid_sources[0x10]	253973	1			T1	227		T2	773		T4	13
valid_sources[0x11]	249934	1			T1	256		T2	696		T4	27
valid_sources[0x12]	291175	1			T1	198		T2	759		T4	19
valid_sources[0x13]	268690	1			T1	264		T2	796		T4	54
valid_sources[0x14]	273554	1			T1	316		T2	750		T4	18
valid_sources[0x15]	252864	1			T1	313		T2	761		T4	11
valid_sources[0x16]	265149	1			T1	278		T2	764		T4	56
valid_sources[0x17]	264353	1			T1	293		T2	759		T4	43
valid_sources[0x18]	247013	1			T1	196		T2	740		T4	32
valid_sources[0x19]	282858	1			T1	253		T2	755		T4	23
valid_sources[0x1a]	250321	1			T1	254		T2	792		T4	9
valid_sources[0x1b]	295093	1			T1	213		T2	779		T4	13
valid_sources[0x1c]	279685	1			T1	239		T2	767		T4	15
valid_sources[0x1d]	320787	1			T1	303		T2	753		T4	47
valid_sources[0x1e]	260007	1			T1	346		T2	783		T4	23
valid_sources[0x1f]	255615	1			T1	240		T2	733		T4	29
valid_sources[0x20]	250673	1			T1	314		T2	762		T4	39
valid_sources[0x21]	350116	1			T1	300		T2	744		T4	26
valid_sources[0x22]	256460	1			T1	363		T2	778		T4	22
valid_sources[0x23]	279683	1			T1	272		T2	722		T4	28
valid_sources[0x24]	264482	1			T1	250		T2	774		T4	34
valid_sources[0x25]	280022	1			T1	274		T2	809		T4	48
valid_sources[0x26]	262958	1			T1	296		T2	723		T4	20
valid_sources[0x27]	250642	1			T1	272		T2	757		T4	12
valid_sources[0x28]	278327	1			T1	326		T2	759		T4	48
valid_sources[0x29]	246648	1			T1	236		T2	764		T4	27
valid_sources[0x2a]	299114	1			T1	260		T2	834		T4	36
valid_sources[0x2b]	294992	1			T1	284		T2	733		T4	28
valid_sources[0x2c]	253106	1			T1	273		T2	745		T4	27
valid_sources[0x2d]	274070	1			T1	226		T2	718		T4	36
valid_sources[0x2e]	286890	1			T1	231		T2	792		T4	31
valid_sources[0x2f]	263301	1			T1	300		T2	757		T4	36
valid_sources[0x30]	303793	1			T1	191		T2	757		T4	18
valid_sources[0x31]	253344	1			T1	251		T2	732		T4	14
valid_sources[0x32]	276952	1			T1	224		T2	765		T4	22
valid_sources[0x33]	320368	1			T1	270		T2	748		T4	20
valid_sources[0x34]	253961	1			T1	266		T2	777		T4	40
valid_sources[0x35]	260391	1			T1	257		T2	708		T4	45
valid_sources[0x36]	273115	1			T1	284		T2	743		T4	19
valid_sources[0x37]	336282	1			T1	285		T2	817		T4	16
valid_sources[0x38]	293457	1			T1	222		T2	762		T4	25
valid_sources[0x39]	461575	1			T1	215		T2	690		T4	35
valid_sources[0x3a]	250079	1			T1	280		T2	717		T4	37
valid_sources[0x3b]	310277	1			T1	308		T2	796		T4	42
valid_sources[0x3c]	286312	1			T1	252		T2	719		T4	15
valid_sources[0x3d]	255152	1			T1	183		T2	735		T4	26
valid_sources[0x3e]	259723	1			T1	245		T2	699		T4	23
valid_sources[0x3f]	260439	1			T1	189		T2	771		T4	19
valid_sources[0x40]	286248	1			T1	223		T2	787		T4	21
valid_sources[0x41]	250845	1			T1	229		T2	738		T4	11
valid_sources[0x42]	247323	1			T1	242		T2	812		T4	43
valid_sources[0x43]	281113	1			T1	276		T2	736		T4	25
valid_sources[0x44]	261729	1			T1	228		T2	715		T4	36
valid_sources[0x45]	282048	1			T1	199		T2	746		T4	17
valid_sources[0x46]	322749	1			T1	333		T2	784		T4	35
valid_sources[0x47]	346635	1			T1	270		T2	732		T4	16
valid_sources[0x48]	257427	1			T1	245		T2	726		T4	22
valid_sources[0x49]	300360	1			T1	312		T2	766		T4	16
valid_sources[0x4a]	288474	1			T1	305		T2	762		T4	26
valid_sources[0x4b]	266963	1			T1	275		T2	775		T4	39
valid_sources[0x4c]	264911	1			T1	276		T2	741		T4	23
valid_sources[0x4d]	260887	1			T1	275		T2	688		T4	3
valid_sources[0x4e]	281052	1			T1	226		T2	839		T4	32
valid_sources[0x4f]	287098	1			T1	258		T2	722		T4	44
valid_sources[0x50]	248580	1			T1	304		T2	751		T4	29
valid_sources[0x51]	247687	1			T1	262		T2	743		T4	25
valid_sources[0x52]	264506	1			T1	272		T2	813		T4	11
valid_sources[0x53]	256769	1			T1	240		T2	736		T4	12
valid_sources[0x54]	249725	1			T1	203		T2	773		T4	38
valid_sources[0x55]	259767	1			T1	199		T2	742		T4	31
valid_sources[0x56]	306803	1			T1	279		T2	758		T4	50
valid_sources[0x57]	302431	1			T1	237		T2	729		T4	21
valid_sources[0x58]	246694	1			T1	266		T2	734		T4	18
valid_sources[0x59]	257218	1			T1	218		T2	761		T4	12
valid_sources[0x5a]	307470	1			T1	252		T2	747		T4	23
valid_sources[0x5b]	310838	1			T1	229		T2	703		T4	31
valid_sources[0x5c]	333373	1			T1	256		T2	736		T4	17
valid_sources[0x5d]	319960	1			T1	337		T2	806		T4	19
valid_sources[0x5e]	294625	1			T1	231		T2	724		T4	37
valid_sources[0x5f]	262473	1			T1	282		T2	737		T4	24
valid_sources[0x60]	246763	1			T1	313		T2	733		T4	19
valid_sources[0x61]	278993	1			T1	190		T2	738		T4	39
valid_sources[0x62]	271540	1			T1	205		T2	794		T4	30
valid_sources[0x63]	274676	1			T1	282		T2	776		T4	24
valid_sources[0x64]	250445	1			T1	284		T2	699		T4	33
valid_sources[0x65]	271218	1			T1	292		T2	786		T4	21
valid_sources[0x66]	277764	1			T1	276		T2	799		T4	19
valid_sources[0x67]	260833	1			T1	278		T2	796		T4	32
valid_sources[0x68]	264247	1			T1	241		T2	728		T4	29
valid_sources[0x69]	300081	1			T1	213		T2	731		T4	18
valid_sources[0x6a]	276015	1			T1	206		T2	745		T4	13
valid_sources[0x6b]	287332	1			T1	294		T2	713		T4	22
valid_sources[0x6c]	285672	1			T1	273		T2	799		T4	12
valid_sources[0x6d]	292717	1			T1	229		T2	756		T4	20
valid_sources[0x6e]	326211	1			T1	284		T2	796		T4	13
valid_sources[0x6f]	289105	1			T1	276		T2	773		T4	22
valid_sources[0x70]	248705	1			T1	242		T2	742		T4	6
valid_sources[0x71]	246411	1			T1	294		T2	677		T4	24
valid_sources[0x72]	301593	1			T1	272		T2	784		T4	20
valid_sources[0x73]	246532	1			T1	162		T2	761		T4	31
valid_sources[0x74]	289859	1			T1	270		T2	717		T4	44
valid_sources[0x75]	270947	1			T1	333		T2	771		T4	27
valid_sources[0x76]	259509	1			T1	241		T2	751		T4	26
valid_sources[0x77]	298625	1			T1	204		T2	720		T4	28
valid_sources[0x78]	264466	1			T1	306		T2	851		T4	35
valid_sources[0x79]	269265	1			T1	277		T2	697		T4	11
valid_sources[0x7a]	261571	1			T1	215		T2	790		T4	4
valid_sources[0x7b]	247014	1			T1	326		T2	744		T4	44
valid_sources[0x7c]	259191	1			T1	206		T2	742		T4	14
valid_sources[0x7d]	282909	1			T1	238		T2	731		T4	14
valid_sources[0x7e]	265401	1			T1	276		T2	747		T4	16
valid_sources[0x7f]	291105	1			T1	230		T2	790		T4	32
valid_sources[0x80]	270467	1			T1	245		T2	759		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28520795

1

T1

29753

T2

87723

T4

2048

values[0x0]

all_enables

biggest_size

14358925

1

T1

14915

T2

43651

T4

2053

values[0x1]

all_enables

biggest_size

14364816

1

T1

14706

T2

43876

T4

2041

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34966	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132889

1

T1

5

T2

64

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48379	1			T2	67		T7	72		T8	79
values[0x0]	57168	1			T1	7		T2	52		T3	2
values[0x1]	62308	1			T1	9		T2	65		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141364

1

T1

8

T2

78

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	987	1			T21	11		T19	5		T127	1
valid_sources[0x01]	702	1			T127	2		T23	7		T48	4
valid_sources[0x02]	639	1			T11	1		T7	1		T60	3
valid_sources[0x03]	933	1			T18	2		T19	120		T128	2
valid_sources[0x04]	528	1			T15	1		T19	5		T127	4
valid_sources[0x05]	537	1			T8	2		T60	5		T127	1
valid_sources[0x06]	624	1			T5	1		T35	3		T29	1
valid_sources[0x07]	671	1			T40	3		T54	1		T8	1
valid_sources[0x08]	513	1			T129	2		T130	2		T23	15
valid_sources[0x09]	788	1			T8	2		T131	1		T22	1
valid_sources[0x0a]	534	1			T7	3		T8	1		T66	1
valid_sources[0x0b]	610	1			T11	1		T7	3		T132	1
valid_sources[0x0c]	610	1			T7	1		T96	1		T60	6
valid_sources[0x0d]	539	1			T8	1		T60	5		T22	1
valid_sources[0x0e]	631	1			T1	1		T29	1		T22	2
valid_sources[0x0f]	807	1			T52	1		T7	1		T8	2
valid_sources[0x10]	573	1			T5	1		T11	2		T8	1
valid_sources[0x11]	698	1			T11	1		T133	5		T19	59
valid_sources[0x12]	629	1			T18	1		T19	29		T23	10
valid_sources[0x13]	551	1			T11	1		T15	2		T19	60
valid_sources[0x14]	737	1			T8	2		T19	7		T134	1
valid_sources[0x15]	626	1			T37	25		T102	1		T15	2
valid_sources[0x16]	612	1			T7	1		T97	6		T19	33
valid_sources[0x17]	600	1			T8	7		T29	1		T18	2
valid_sources[0x18]	678	1			T18	1		T19	2		T134	1
valid_sources[0x19]	717	1			T60	1		T15	1		T19	66
valid_sources[0x1a]	966	1			T21	17		T22	238		T19	27
valid_sources[0x1b]	629	1			T2	9		T11	1		T8	1
valid_sources[0x1c]	866	1			T7	1		T19	31		T128	8
valid_sources[0x1d]	628	1			T96	1		T60	6		T14	1
valid_sources[0x1e]	548	1			T8	1		T19	37		T124	1
valid_sources[0x1f]	585	1			T5	1		T7	1		T135	1
valid_sources[0x20]	729	1			T8	3		T31	1		T19	12
valid_sources[0x21]	515	1			T18	1		T136	14		T23	18
valid_sources[0x22]	662	1			T7	1		T15	1		T19	49
valid_sources[0x23]	551	1			T7	1		T8	1		T15	1
valid_sources[0x24]	802	1			T8	4		T125	1		T19	7
valid_sources[0x25]	545	1			T8	2		T60	12		T19	1
valid_sources[0x26]	489	1			T7	2		T61	1		T29	1
valid_sources[0x27]	536	1			T7	1		T19	1		T88	1
valid_sources[0x28]	636	1			T2	20		T22	1		T19	44
valid_sources[0x29]	627	1			T8	1		T125	1		T15	1
valid_sources[0x2a]	517	1			T36	2		T7	3		T8	2
valid_sources[0x2b]	502	1			T7	4		T8	1		T18	1
valid_sources[0x2c]	474	1			T7	1		T8	3		T22	20
valid_sources[0x2d]	586	1			T7	3		T21	16		T29	1
valid_sources[0x2e]	496	1			T7	6		T60	10		T61	1
valid_sources[0x2f]	542	1			T36	1		T8	3		T137	2
valid_sources[0x30]	619	1			T7	1		T60	2		T23	13
valid_sources[0x31]	745	1			T14	2		T22	96		T19	56
valid_sources[0x32]	571	1			T10	1		T7	3		T61	1
valid_sources[0x33]	1172	1			T8	3		T22	33		T19	9
valid_sources[0x34]	483	1			T29	1		T18	1		T19	11
valid_sources[0x35]	580	1			T19	73		T134	1		T138	2
valid_sources[0x36]	808	1			T7	3		T8	4		T29	1
valid_sources[0x37]	765	1			T1	2		T15	1		T19	15
valid_sources[0x38]	657	1			T8	1		T19	64		T68	1
valid_sources[0x39]	757	1			T8	1		T60	2		T15	1
valid_sources[0x3a]	982	1			T7	1		T8	5		T102	1
valid_sources[0x3b]	837	1			T7	2		T15	1		T29	1
valid_sources[0x3c]	786	1			T7	3		T61	1		T126	1
valid_sources[0x3d]	621	1			T35	6		T7	1		T8	5
valid_sources[0x3e]	744	1			T2	2		T61	1		T19	19
valid_sources[0x3f]	539	1			T7	2		T22	31		T19	5
valid_sources[0x40]	964	1			T8	2		T22	7		T19	41
valid_sources[0x41]	590	1			T7	3		T8	2		T22	1
valid_sources[0x42]	690	1			T36	2		T96	1		T22	1
valid_sources[0x43]	478	1			T7	3		T15	1		T18	1
valid_sources[0x44]	655	1			T1	1		T7	1		T13	1
valid_sources[0x45]	572	1			T2	1		T7	1		T22	2
valid_sources[0x46]	553	1			T7	1		T8	5		T19	2
valid_sources[0x47]	594	1			T8	7		T19	11		T124	1
valid_sources[0x48]	582	1			T61	1		T19	1		T88	1
valid_sources[0x49]	487	1			T11	1		T7	1		T19	10
valid_sources[0x4a]	508	1			T1	1		T7	2		T22	1
valid_sources[0x4b]	606	1			T100	2		T29	1		T30	6
valid_sources[0x4c]	533	1			T7	3		T8	3		T19	1
valid_sources[0x4d]	780	1			T19	1		T23	10		T48	4
valid_sources[0x4e]	487	1			T22	3		T18	1		T134	1
valid_sources[0x4f]	545	1			T4	1		T11	1		T7	1
valid_sources[0x50]	556	1			T2	9		T19	4		T127	3
valid_sources[0x51]	932	1			T8	1		T100	2		T29	2
valid_sources[0x52]	762	1			T2	3		T5	1		T7	2
valid_sources[0x53]	1078	1			T2	2		T36	1		T22	1
valid_sources[0x54]	597	1			T12	1		T29	1		T139	2
valid_sources[0x55]	515	1			T1	1		T7	2		T61	1
valid_sources[0x56]	754	1			T29	1		T18	1		T19	25
valid_sources[0x57]	523	1			T7	3		T8	2		T123	2
valid_sources[0x58]	545	1			T7	4		T19	1		T134	2
valid_sources[0x59]	652	1			T5	1		T60	3		T15	1
valid_sources[0x5a]	532	1			T7	2		T8	7		T22	2
valid_sources[0x5b]	817	1			T8	1		T14	1		T19	3
valid_sources[0x5c]	621	1			T51	1		T21	4		T18	1
valid_sources[0x5d]	695	1			T7	1		T8	1		T15	1
valid_sources[0x5e]	537	1			T2	10		T5	1		T126	1
valid_sources[0x5f]	768	1			T7	2		T123	2		T67	69
valid_sources[0x60]	989	1			T11	2		T8	1		T22	1
valid_sources[0x61]	691	1			T8	1		T18	1		T140	2
valid_sources[0x62]	525	1			T8	1		T22	1		T19	1
valid_sources[0x63]	630	1			T7	2		T128	3		T130	1
valid_sources[0x64]	582	1			T7	4		T8	2		T60	7
valid_sources[0x65]	688	1			T60	1		T98	5		T29	1
valid_sources[0x66]	749	1			T11	1		T7	3		T15	1
valid_sources[0x67]	787	1			T1	1		T61	1		T22	4
valid_sources[0x68]	643	1			T7	4		T19	32		T88	2
valid_sources[0x69]	704	1			T5	1		T35	1		T7	2
valid_sources[0x6a]	597	1			T23	8		T48	7		T41	4
valid_sources[0x6b]	659	1			T35	1		T8	5		T29	1
valid_sources[0x6c]	546	1			T9	1		T11	1		T7	4
valid_sources[0x6d]	620	1			T8	2		T61	1		T14	1
valid_sources[0x6e]	497	1			T2	3		T5	2		T7	1
valid_sources[0x6f]	622	1			T60	4		T19	114		T127	2
valid_sources[0x70]	829	1			T1	1		T7	6		T8	1
valid_sources[0x71]	581	1			T7	1		T29	2		T68	1
valid_sources[0x72]	796	1			T7	1		T60	5		T19	10
valid_sources[0x73]	482	1			T2	11		T8	1		T29	1
valid_sources[0x74]	571	1			T2	18		T7	2		T60	7
valid_sources[0x75]	789	1			T8	1		T19	12		T128	4
valid_sources[0x76]	634	1			T7	1		T19	2		T23	16
valid_sources[0x77]	847	1			T19	5		T134	1		T128	1
valid_sources[0x78]	859	1			T4	1		T11	1		T7	3
valid_sources[0x79]	565	1			T19	36		T141	2		T128	2
valid_sources[0x7a]	610	1			T7	2		T8	4		T19	56
valid_sources[0x7b]	836	1			T29	1		T19	8		T127	1
valid_sources[0x7c]	664	1			T22	2		T18	1		T19	43
valid_sources[0x7d]	618	1			T7	3		T8	1		T19	100
valid_sources[0x7e]	778	1			T2	24		T8	1		T60	19
valid_sources[0x7f]	448	1			T7	1		T53	22		T8	5
valid_sources[0x80]	506	1			T11	1		T134	1		T130	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36467

1

T2

34

T7

40

T8

38

values[0x0]

all_enables

biggest_size

49050

1

T1

4

T2

22

T3

1

values[0x1]

all_enables

biggest_size

47372

1

T1

1

T2

8

T11

2