Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14063000

1

T1

4812

T2

14929

T6

25441

full_word

52209287

1

T1

47528

T2

149402

T4

6142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66272047	1			T1	52340		T2	164331		T4	6142
auto[TlIntgErrCmd]	88	1			T55	4		T56	8		T57	2
auto[TlIntgErrData]	77	1			T55	3		T56	3		T57	4
auto[TlIntgErrBoth]	75	1			T55	3		T56	9		T57	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30298939

1

T1

19723

T2

70031

T4

2048

auto[1]

35973348

1

T1

32617

T2

94300

T4

4094

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6725017	1			T1	1816		T2	6284		T6	12631
auto[TlIntgErrNone]	partial	auto[1]	7337759	1			T1	2996		T2	8645		T6	12810
auto[TlIntgErrNone]	full_word	auto[0]	23573834	1			T1	17907		T2	63747		T4	2048
auto[TlIntgErrNone]	full_word	auto[1]	28635437	1			T1	29621		T2	85655		T4	4094
auto[TlIntgErrCmd]	partial	auto[0]	25	1			T55	1		T56	1		T57	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T55	2		T56	6		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T114	1		T116	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T55	1		T56	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T55	1		T56	2		T57	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T55	2		T56	1		T57	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T118	1		T121	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T118	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	21	1			T55	1		T56	3		T57	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T55	2		T56	6		T57	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T118	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T119	1		T115	1		T116	1