Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	687440	1			T1	723		T5	2803		T9	380
auto[1]	10437890	1			T1	477		T2	13334		T6	116909
auto[2]	575730	1			T1	445		T5	1820		T9	190
auto[3]	10337223	1			T1	252		T2	13144		T6	117490

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14030451	1			T1	1440		T2	22186		T6	195580
auto[1]	2116761	1			T1	186		T2	2056		T6	18537
auto[2]	2136544	1			T1	248		T2	2054		T6	18506
auto[3]	3754527	1			T1	23		T2	182		T6	1776

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7952288

1

T1

1895

T2

26456

T5

7710

auto[1]

14085995

1

T1

2

T2

22

T6

234399

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	192431	1			T1	582		T5	2274		T9	319
auto[0]	auto[0]	auto[1]	20071	1			T1	65		T5	248		T9	25
auto[0]	auto[0]	auto[2]	20623	1			T1	72		T5	249		T9	33
auto[0]	auto[0]	auto[3]	8495	1			T1	4		T5	29		T9	3
auto[0]	auto[1]	auto[0]	3080515	1			T1	365		T2	11141		T5	1558
auto[0]	auto[1]	auto[1]	315762	1			T1	64		T2	989		T5	291
auto[0]	auto[1]	auto[2]	310033	1			T1	38		T2	1102		T5	166
auto[0]	auto[1]	auto[3]	62909	1			T1	9		T2	92		T5	29
auto[0]	auto[2]	auto[0]	162127	1			T1	341		T5	1386		T20	16
auto[0]	auto[2]	auto[1]	17096	1			T1	37		T5	161		T96	1
auto[0]	auto[2]	auto[2]	20036	1			T1	61		T5	246		T9	174
auto[0]	auto[2]	auto[3]	7120	1			T1	6		T5	27		T9	16
auto[0]	auto[3]	auto[0]	3047825	1			T1	152		T2	11025		T5	683
auto[0]	auto[3]	auto[1]	307117	1			T1	20		T2	1067		T5	72
auto[0]	auto[3]	auto[2]	316855	1			T1	75		T2	950		T5	254
auto[0]	auto[3]	auto[3]	63273	1			T1	4		T2	90		T5	37
auto[1]	auto[0]	auto[0]	15062	1			T5	3		T96	1184		T99	72
auto[1]	auto[0]	auto[1]	66755	1			T96	5262		T99	399		T30	4636
auto[1]	auto[0]	auto[2]	66337	1			T96	5214		T99	380		T30	4549
auto[1]	auto[0]	auto[3]	297666	1			T51	1		T96	23189		T125	1
auto[1]	auto[1]	auto[0]	3760764	1			T2	9		T6	97533		T5	1
auto[1]	auto[1]	auto[1]	690251	1			T6	8787		T11	1		T36	2
auto[1]	auto[1]	auto[2]	665032	1			T1	1		T2	1		T6	9724
auto[1]	auto[1]	auto[3]	1552624	1			T6	865		T96	23774		T97	859
auto[1]	auto[2]	auto[0]	11116	1			T96	1038		T30	948		T126	9
auto[1]	auto[2]	auto[1]	49577	1			T96	4829		T30	4115		T126	1
auto[1]	auto[2]	auto[2]	56101	1			T96	4318		T99	339		T30	3106
auto[1]	auto[2]	auto[3]	252557	1			T96	19765		T99	1560		T30	13810
auto[1]	auto[3]	auto[0]	3760611	1			T2	11		T6	98047		T9	3
auto[1]	auto[3]	auto[1]	650132	1			T6	9750		T9	1		T36	4
auto[1]	auto[3]	auto[2]	681527	1			T1	1		T2	1		T6	8782
auto[1]	auto[3]	auto[3]	1509883	1			T6	911		T9	1		T35	1