Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	295747218	199406	0	0
ctrl_regwen_rd_A	295747218	3314	0	0
exec_rd_A	295747218	2978	0	0
exec_regwen_rd_A	295747218	3116	0	0
readback_rd_A	295747218	1872	0	0
readback_regwen_rd_A	295747218	1702	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295747218	199406	0	0
T18	788731	0	0	0
T19	140451	7316	0	0
T22	81471	2054	0	0
T23	0	4069	0	0
T41	0	2894	0	0
T48	0	2297	0	0
T50	0	8420	0	0
T62	0	3888	0	0
T63	0	4670	0	0
T64	0	2815	0	0
T65	0	3259	0	0
T66	132476	0	0	0
T67	499766	0	0	0
T68	650	0	0	0
T69	22748	0	0	0
T70	13754	0	0	0
T71	116496	0	0	0
T72	2790	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295747218	3314	0	0
T18	788731	0	0	0
T19	140451	0	0	0
T22	81471	98	0	0
T41	0	147	0	0
T42	0	136	0	0
T65	0	124	0	0
T66	132476	0	0	0
T67	499766	0	0	0
T68	650	0	0	0
T69	22748	0	0	0
T70	13754	0	0	0
T71	116496	0	0	0
T72	2790	0	0	0
T104	0	103	0	0
T105	0	276	0	0
T106	0	335	0	0
T107	0	231	0	0
T108	0	145	0	0
T109	0	298	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295747218	2978	0	0
T18	788731	0	0	0
T19	140451	0	0	0
T22	81471	120	0	0
T41	0	141	0	0
T42	0	117	0	0
T65	0	101	0	0
T66	132476	0	0	0
T67	499766	0	0	0
T68	650	0	0	0
T69	22748	0	0	0
T70	13754	0	0	0
T71	116496	0	0	0
T72	2790	0	0	0
T104	0	72	0	0
T105	0	192	0	0
T106	0	277	0	0
T107	0	219	0	0
T108	0	124	0	0
T109	0	256	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295747218	3116	0	0
T18	788731	0	0	0
T19	140451	0	0	0
T22	81471	95	0	0
T41	0	184	0	0
T42	0	112	0	0
T65	0	108	0	0
T66	132476	0	0	0
T67	499766	0	0	0
T68	650	0	0	0
T69	22748	0	0	0
T70	13754	0	0	0
T71	116496	0	0	0
T72	2790	0	0	0
T104	0	77	0	0
T105	0	224	0	0
T106	0	325	0	0
T107	0	225	0	0
T108	0	152	0	0
T109	0	347	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295747218	1872	0	0
T18	788731	0	0	0
T19	140451	0	0	0
T22	81471	74	0	0
T41	0	109	0	0
T42	0	95	0	0
T65	0	92	0	0
T66	132476	0	0	0
T67	499766	0	0	0
T68	650	0	0	0
T69	22748	0	0	0
T70	13754	0	0	0
T71	116496	0	0	0
T72	2790	0	0	0
T104	0	94	0	0
T105	0	274	0	0
T106	0	321	0	0
T107	0	192	0	0
T108	0	130	0	0
T109	0	286	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295747218	1702	0	0
T18	788731	0	0	0
T19	140451	0	0	0
T22	81471	69	0	0
T41	0	149	0	0
T42	0	94	0	0
T65	0	112	0	0
T66	132476	0	0	0
T67	499766	0	0	0
T68	650	0	0	0
T69	22748	0	0	0
T70	13754	0	0	0
T71	116496	0	0	0
T72	2790	0	0	0
T104	0	35	0	0
T105	0	218	0	0
T106	0	359	0	0
T107	0	166	0	0
T108	0	137	0	0
T109	0	228	0	0