Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13942364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59532435

1

T1

1042

T2

3071

T3

30716

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36637823	1			T1	2941		T2	1024		T3	84814
values[0x0]	17018452	1			T1	964		T2	1021		T3	28390
values[0x1]	19818524	1			T1	1867		T2	1026		T3	55653

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6945955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66528844

1

T1

3435

T2

3071

T3

99899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	272212	1			T1	25		T3	666		T4	24
valid_sources[0x01]	287527	1			T1	17		T3	689		T4	25
valid_sources[0x02]	325114	1			T1	22		T3	651		T4	20
valid_sources[0x03]	286698	1			T1	25		T3	691		T4	26
valid_sources[0x04]	247822	1			T1	24		T3	695		T4	16
valid_sources[0x05]	314839	1			T1	20		T3	696		T4	25
valid_sources[0x06]	289670	1			T1	22		T3	708		T4	17
valid_sources[0x07]	249615	1			T1	25		T3	649		T4	18
valid_sources[0x08]	268076	1			T1	21		T3	619		T4	25
valid_sources[0x09]	287572	1			T1	19		T3	685		T4	22
valid_sources[0x0a]	275879	1			T1	14		T3	634		T4	31
valid_sources[0x0b]	271392	1			T1	27		T3	686		T4	19
valid_sources[0x0c]	332568	1			T1	20		T3	645		T4	28
valid_sources[0x0d]	262459	1			T1	30		T3	651		T4	25
valid_sources[0x0e]	307556	1			T1	23		T3	631		T4	25
valid_sources[0x0f]	276254	1			T1	26		T3	654		T4	21
valid_sources[0x10]	302437	1			T1	23		T3	711		T4	29
valid_sources[0x11]	311276	1			T1	26		T3	683		T4	20
valid_sources[0x12]	267851	1			T1	28		T3	699		T4	14
valid_sources[0x13]	302448	1			T1	26		T3	675		T4	20
valid_sources[0x14]	317753	1			T1	14		T3	632		T4	20
valid_sources[0x15]	301471	1			T1	20		T3	626		T4	24
valid_sources[0x16]	327343	1			T1	31		T3	686		T4	20
valid_sources[0x17]	324260	1			T1	15		T3	601		T4	21
valid_sources[0x18]	291759	1			T1	25		T3	694		T4	23
valid_sources[0x19]	295825	1			T1	16		T2	3071		T3	654
valid_sources[0x1a]	274323	1			T1	20		T3	694		T4	18
valid_sources[0x1b]	255131	1			T1	27		T3	741		T4	26
valid_sources[0x1c]	308482	1			T1	22		T3	671		T4	18
valid_sources[0x1d]	304517	1			T1	16		T3	612		T4	14
valid_sources[0x1e]	304241	1			T1	37		T3	655		T4	33
valid_sources[0x1f]	271025	1			T1	22		T3	664		T4	18
valid_sources[0x20]	256006	1			T1	14		T3	675		T4	25
valid_sources[0x21]	300392	1			T1	17		T3	654		T4	19
valid_sources[0x22]	330501	1			T1	20		T3	666		T4	25
valid_sources[0x23]	335369	1			T1	24		T3	642		T4	25
valid_sources[0x24]	264134	1			T1	22		T3	695		T4	35
valid_sources[0x25]	300561	1			T1	18		T3	642		T4	34
valid_sources[0x26]	252066	1			T1	29		T3	673		T4	24
valid_sources[0x27]	261565	1			T1	18		T3	639		T4	36
valid_sources[0x28]	259694	1			T1	21		T3	668		T4	15
valid_sources[0x29]	252848	1			T1	17		T3	649		T4	35
valid_sources[0x2a]	271971	1			T1	17		T3	619		T4	18
valid_sources[0x2b]	348367	1			T1	22		T3	624		T4	27
valid_sources[0x2c]	265185	1			T1	25		T3	632		T4	17
valid_sources[0x2d]	248392	1			T1	29		T3	681		T4	15
valid_sources[0x2e]	258762	1			T1	23		T3	655		T4	27
valid_sources[0x2f]	273281	1			T1	24		T3	645		T4	22
valid_sources[0x30]	266381	1			T1	21		T3	647		T4	23
valid_sources[0x31]	263655	1			T1	22		T3	703		T4	23
valid_sources[0x32]	294036	1			T1	22		T3	597		T4	27
valid_sources[0x33]	274905	1			T1	29		T3	646		T4	25
valid_sources[0x34]	301054	1			T1	29		T3	675		T4	16
valid_sources[0x35]	293108	1			T1	21		T3	672		T4	25
valid_sources[0x36]	297550	1			T1	18		T3	626		T4	34
valid_sources[0x37]	271155	1			T1	35		T3	677		T4	23
valid_sources[0x38]	281856	1			T1	18		T3	678		T4	35
valid_sources[0x39]	269701	1			T1	23		T3	669		T4	28
valid_sources[0x3a]	270876	1			T1	21		T3	705		T4	19
valid_sources[0x3b]	277173	1			T1	25		T3	659		T4	29
valid_sources[0x3c]	270428	1			T1	31		T3	648		T4	25
valid_sources[0x3d]	253488	1			T1	33		T3	650		T4	21
valid_sources[0x3e]	284289	1			T1	25		T3	587		T4	28
valid_sources[0x3f]	251080	1			T1	21		T3	655		T4	32
valid_sources[0x40]	271095	1			T1	16		T3	608		T4	18
valid_sources[0x41]	282725	1			T1	14		T3	633		T4	22
valid_sources[0x42]	281990	1			T1	22		T3	687		T4	23
valid_sources[0x43]	271837	1			T1	26		T3	725		T4	24
valid_sources[0x44]	272404	1			T1	27		T3	658		T4	28
valid_sources[0x45]	258496	1			T1	20		T3	689		T4	19
valid_sources[0x46]	353209	1			T1	31		T3	651		T4	28
valid_sources[0x47]	309513	1			T1	30		T3	664		T4	22
valid_sources[0x48]	269131	1			T1	24		T3	650		T4	22
valid_sources[0x49]	332204	1			T1	25		T3	698		T4	22
valid_sources[0x4a]	252299	1			T1	29		T3	661		T4	22
valid_sources[0x4b]	275880	1			T1	14		T3	708		T4	20
valid_sources[0x4c]	264408	1			T1	22		T3	593		T4	24
valid_sources[0x4d]	257678	1			T1	13		T3	696		T4	30
valid_sources[0x4e]	321286	1			T1	16		T3	684		T4	25
valid_sources[0x4f]	264592	1			T1	18		T3	646		T4	21
valid_sources[0x50]	337522	1			T1	31		T3	702		T4	31
valid_sources[0x51]	253457	1			T1	29		T3	691		T4	22
valid_sources[0x52]	310233	1			T1	23		T3	707		T4	26
valid_sources[0x53]	266064	1			T1	30		T3	635		T4	22
valid_sources[0x54]	312462	1			T1	16		T3	639		T4	33
valid_sources[0x55]	308339	1			T1	26		T3	680		T4	20
valid_sources[0x56]	299356	1			T1	15		T3	671		T4	13
valid_sources[0x57]	291425	1			T1	21		T3	632		T4	23
valid_sources[0x58]	300491	1			T1	18		T3	626		T4	22
valid_sources[0x59]	265981	1			T1	18		T3	624		T4	22
valid_sources[0x5a]	290805	1			T1	16		T3	673		T4	28
valid_sources[0x5b]	252228	1			T1	18		T3	629		T4	11
valid_sources[0x5c]	265896	1			T1	34		T3	675		T4	18
valid_sources[0x5d]	341774	1			T1	37		T3	677		T4	19
valid_sources[0x5e]	266570	1			T1	29		T3	622		T4	20
valid_sources[0x5f]	275249	1			T1	25		T3	624		T4	21
valid_sources[0x60]	280458	1			T1	18		T3	657		T4	28
valid_sources[0x61]	341444	1			T1	35		T3	643		T4	25
valid_sources[0x62]	303732	1			T1	29		T3	652		T4	36
valid_sources[0x63]	341617	1			T1	24		T3	626		T4	25
valid_sources[0x64]	302960	1			T1	20		T3	677		T4	31
valid_sources[0x65]	368727	1			T1	22		T3	663		T4	17
valid_sources[0x66]	282639	1			T1	24		T3	651		T4	31
valid_sources[0x67]	308141	1			T1	26		T3	649		T4	29
valid_sources[0x68]	277194	1			T1	22		T3	671		T4	19
valid_sources[0x69]	261928	1			T1	19		T3	689		T4	34
valid_sources[0x6a]	269804	1			T1	24		T3	662		T4	28
valid_sources[0x6b]	352319	1			T1	17		T3	690		T4	27
valid_sources[0x6c]	253756	1			T1	17		T3	675		T4	18
valid_sources[0x6d]	254238	1			T1	24		T3	603		T4	25
valid_sources[0x6e]	269159	1			T1	25		T3	628		T4	22
valid_sources[0x6f]	252791	1			T1	28		T3	644		T4	22
valid_sources[0x70]	277088	1			T1	19		T3	690		T4	24
valid_sources[0x71]	287016	1			T1	22		T3	683		T4	21
valid_sources[0x72]	253744	1			T1	22		T3	620		T4	20
valid_sources[0x73]	283309	1			T1	22		T3	684		T4	23
valid_sources[0x74]	256082	1			T1	24		T3	666		T4	25
valid_sources[0x75]	254545	1			T1	22		T3	651		T4	19
valid_sources[0x76]	284183	1			T1	20		T3	666		T4	26
valid_sources[0x77]	259225	1			T1	23		T3	626		T4	32
valid_sources[0x78]	262747	1			T1	16		T3	616		T4	19
valid_sources[0x79]	276360	1			T1	28		T3	627		T4	25
valid_sources[0x7a]	268757	1			T1	34		T3	676		T4	27
valid_sources[0x7b]	281647	1			T1	22		T3	666		T4	27
valid_sources[0x7c]	260381	1			T1	28		T3	697		T4	22
valid_sources[0x7d]	261158	1			T1	22		T3	698		T4	20
valid_sources[0x7e]	251188	1			T1	36		T3	668		T4	26
valid_sources[0x7f]	282892	1			T1	22		T3	621		T4	20
valid_sources[0x80]	248536	1			T1	24		T3	684		T4	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29666515

1

T1

535

T2

1024

T3

15476

values[0x0]

all_enables

biggest_size

14929103

1

T1

258

T2

1021

T3

7734

values[0x1]

all_enables

biggest_size

14936817

1

T1

249

T2

1026

T3

7506

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

127500

1

T2

2

T3

2

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47695	1			T12	24		T20	454		T21	25
values[0x0]	55697	1			T1	1		T2	3		T3	4
values[0x1]	60010	1			T2	4		T3	3		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27239	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136163

1

T2

2

T3

2

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	803	1			T20	10		T26	8		T129	3
valid_sources[0x01]	674	1			T20	2		T28	1		T139	1
valid_sources[0x02]	487	1			T20	3		T28	1		T8	2
valid_sources[0x03]	496	1			T20	4		T21	1		T8	2
valid_sources[0x04]	586	1			T20	8		T28	1		T26	7
valid_sources[0x05]	641	1			T43	41		T20	4		T63	1
valid_sources[0x06]	597	1			T20	3		T63	1		T28	1
valid_sources[0x07]	550	1			T20	22		T26	6		T53	3
valid_sources[0x08]	570	1			T20	13		T8	1		T22	2
valid_sources[0x09]	678	1			T20	1		T21	2		T74	3
valid_sources[0x0a]	834	1			T21	2		T8	1		T26	11
valid_sources[0x0b]	722	1			T20	5		T148	1		T28	1
valid_sources[0x0c]	739	1			T20	6		T7	2		T8	1
valid_sources[0x0d]	689	1			T20	10		T14	1		T63	1
valid_sources[0x0e]	838	1			T63	1		T26	10		T129	10
valid_sources[0x0f]	636	1			T20	16		T21	1		T7	10
valid_sources[0x10]	810	1			T20	4		T26	11		T45	1
valid_sources[0x11]	666	1			T20	1		T21	4		T7	3
valid_sources[0x12]	1084	1			T20	1		T7	1		T8	3
valid_sources[0x13]	692	1			T20	8		T26	6		T149	1
valid_sources[0x14]	868	1			T20	12		T28	1		T26	7
valid_sources[0x15]	578	1			T20	8		T21	2		T24	3
valid_sources[0x16]	800	1			T20	6		T8	1		T26	4
valid_sources[0x17]	837	1			T20	14		T28	1		T15	12
valid_sources[0x18]	762	1			T20	12		T150	1		T26	6
valid_sources[0x19]	670	1			T20	13		T21	2		T26	10
valid_sources[0x1a]	467	1			T20	6		T148	1		T28	1
valid_sources[0x1b]	473	1			T20	23		T24	1		T28	1
valid_sources[0x1c]	404	1			T20	2		T14	1		T24	2
valid_sources[0x1d]	714	1			T20	11		T60	5		T14	1
valid_sources[0x1e]	511	1			T20	12		T46	21		T26	10
valid_sources[0x1f]	876	1			T20	14		T63	2		T28	1
valid_sources[0x20]	619	1			T20	6		T7	5		T8	1
valid_sources[0x21]	521	1			T20	3		T21	1		T8	1
valid_sources[0x22]	811	1			T20	6		T26	8		T129	16
valid_sources[0x23]	910	1			T20	2		T8	1		T106	5
valid_sources[0x24]	921	1			T20	7		T44	1		T59	5
valid_sources[0x25]	460	1			T20	4		T44	1		T26	8
valid_sources[0x26]	772	1			T20	5		T26	12		T151	2
valid_sources[0x27]	1001	1			T20	5		T28	1		T26	4
valid_sources[0x28]	631	1			T20	14		T24	4		T8	1
valid_sources[0x29]	725	1			T20	1		T139	1		T26	5
valid_sources[0x2a]	518	1			T20	2		T47	6		T26	8
valid_sources[0x2b]	781	1			T20	12		T21	1		T8	1
valid_sources[0x2c]	649	1			T67	1		T47	9		T26	10
valid_sources[0x2d]	400	1			T20	4		T62	2		T7	8
valid_sources[0x2e]	459	1			T24	1		T7	1		T26	13
valid_sources[0x2f]	433	1			T20	7		T8	1		T26	13
valid_sources[0x30]	605	1			T20	8		T26	6		T152	1
valid_sources[0x31]	787	1			T20	16		T21	1		T24	1
valid_sources[0x32]	817	1			T20	7		T47	5		T109	2
valid_sources[0x33]	614	1			T20	15		T24	3		T26	3
valid_sources[0x34]	528	1			T20	7		T8	1		T105	4
valid_sources[0x35]	570	1			T20	5		T21	2		T28	1
valid_sources[0x36]	779	1			T20	12		T63	1		T28	1
valid_sources[0x37]	722	1			T150	1		T7	4		T74	15
valid_sources[0x38]	529	1			T20	8		T28	1		T26	8
valid_sources[0x39]	765	1			T20	19		T44	1		T26	7
valid_sources[0x3a]	580	1			T26	9		T149	1		T153	1
valid_sources[0x3b]	410	1			T20	1		T29	1		T28	1
valid_sources[0x3c]	493	1			T20	9		T26	10		T154	1
valid_sources[0x3d]	524	1			T20	3		T26	12		T45	1
valid_sources[0x3e]	545	1			T20	21		T150	1		T26	9
valid_sources[0x3f]	664	1			T20	10		T8	1		T26	8
valid_sources[0x40]	384	1			T20	1		T21	2		T63	1
valid_sources[0x41]	541	1			T20	18		T8	1		T26	7
valid_sources[0x42]	494	1			T20	10		T28	1		T8	2
valid_sources[0x43]	472	1			T9	4		T20	22		T26	4
valid_sources[0x44]	986	1			T27	3		T20	10		T150	1
valid_sources[0x45]	1230	1			T20	6		T21	2		T63	1
valid_sources[0x46]	488	1			T20	12		T28	2		T155	3
valid_sources[0x47]	1095	1			T20	2		T139	1		T26	5
valid_sources[0x48]	463	1			T20	11		T44	1		T26	9
valid_sources[0x49]	690	1			T20	5		T44	1		T24	13
valid_sources[0x4a]	480	1			T20	14		T24	3		T26	12
valid_sources[0x4b]	715	1			T20	5		T8	1		T155	1
valid_sources[0x4c]	678	1			T20	8		T21	1		T47	2
valid_sources[0x4d]	549	1			T25	2		T20	5		T24	1
valid_sources[0x4e]	868	1			T20	2		T24	67		T155	1
valid_sources[0x4f]	578	1			T8	2		T139	1		T26	4
valid_sources[0x50]	1329	1			T1	1		T20	4		T8	1
valid_sources[0x51]	473	1			T20	1		T44	1		T26	7
valid_sources[0x52]	534	1			T20	6		T67	4		T24	1
valid_sources[0x53]	492	1			T20	6		T21	3		T26	4
valid_sources[0x54]	526	1			T20	2		T21	2		T148	1
valid_sources[0x55]	758	1			T20	27		T24	1		T26	12
valid_sources[0x56]	483	1			T20	4		T24	1		T8	1
valid_sources[0x57]	466	1			T14	1		T24	1		T28	2
valid_sources[0x58]	539	1			T20	1		T21	4		T8	1
valid_sources[0x59]	858	1			T26	8		T156	1		T95	1
valid_sources[0x5a]	760	1			T63	1		T24	167		T8	1
valid_sources[0x5b]	552	1			T4	3		T20	11		T26	7
valid_sources[0x5c]	662	1			T20	20		T21	3		T26	4
valid_sources[0x5d]	552	1			T20	1		T14	1		T24	2
valid_sources[0x5e]	457	1			T20	6		T21	1		T24	6
valid_sources[0x5f]	578	1			T20	9		T157	1		T26	8
valid_sources[0x60]	514	1			T20	29		T44	1		T24	1
valid_sources[0x61]	619	1			T20	6		T26	12		T156	1
valid_sources[0x62]	511	1			T20	4		T14	1		T28	1
valid_sources[0x63]	753	1			T20	9		T21	2		T26	7
valid_sources[0x64]	563	1			T20	3		T7	6		T8	1
valid_sources[0x65]	495	1			T20	7		T47	21		T155	1
valid_sources[0x66]	477	1			T20	3		T26	3		T142	1
valid_sources[0x67]	760	1			T20	5		T28	1		T22	1
valid_sources[0x68]	831	1			T20	3		T22	4		T26	12
valid_sources[0x69]	618	1			T20	20		T28	1		T26	8
valid_sources[0x6a]	410	1			T20	6		T28	1		T8	3
valid_sources[0x6b]	497	1			T20	10		T24	1		T28	1
valid_sources[0x6c]	594	1			T2	1		T20	16		T26	9
valid_sources[0x6d]	974	1			T20	5		T21	1		T28	2
valid_sources[0x6e]	487	1			T20	3		T74	7		T26	4
valid_sources[0x6f]	587	1			T42	16		T20	9		T44	1
valid_sources[0x70]	1072	1			T20	10		T24	104		T26	8
valid_sources[0x71]	503	1			T8	1		T26	8		T151	1
valid_sources[0x72]	461	1			T20	3		T14	1		T54	1
valid_sources[0x73]	472	1			T20	25		T26	10		T129	12
valid_sources[0x74]	742	1			T20	10		T155	2		T26	11
valid_sources[0x75]	491	1			T20	20		T14	1		T26	7
valid_sources[0x76]	677	1			T20	5		T21	2		T8	1
valid_sources[0x77]	850	1			T4	3		T20	1		T26	9
valid_sources[0x78]	669	1			T26	3		T158	1		T38	10
valid_sources[0x79]	821	1			T27	1		T20	5		T24	1
valid_sources[0x7a]	460	1			T20	11		T28	1		T8	1
valid_sources[0x7b]	701	1			T20	7		T21	2		T22	1
valid_sources[0x7c]	539	1			T20	10		T63	1		T28	1
valid_sources[0x7d]	639	1			T20	1		T21	5		T26	9
valid_sources[0x7e]	507	1			T20	4		T28	1		T22	1
valid_sources[0x7f]	767	1			T20	7		T24	8		T26	8
valid_sources[0x80]	942	1			T20	2		T21	1		T26	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35023

1

T12

7

T20

421

T21

10

values[0x0]

all_enables

biggest_size

47252

1

T2

1

T3

2

T4

1

values[0x1]

all_enables

biggest_size

45225

1

T2

1

T4

1

T5

1