Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13623826

1

T1

4730

T3

138141

T12

18638

full_word

54500592

1

T1

1042

T2

3071

T3

30716

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68124088	1			T1	5772		T2	3071		T3	168857
auto[TlIntgErrCmd]	113	1			T64	3		T65	6		T66	5
auto[TlIntgErrData]	119	1			T64	4		T65	9		T66	10
auto[TlIntgErrBoth]	98	1			T64	3		T65	5		T66	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31221758

1

T1

2941

T2

1024

T3

84814

auto[1]

36902660

1

T1

2831

T2

2047

T3

84043

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6513231	1			T1	2406		T3	69338		T12	6978
auto[TlIntgErrNone]	partial	auto[1]	7110296	1			T1	2324		T3	68803		T12	11660
auto[TlIntgErrNone]	full_word	auto[0]	24708366	1			T1	535		T2	1024		T3	15476
auto[TlIntgErrNone]	full_word	auto[1]	29792195	1			T1	507		T2	2047		T3	15240
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T64	2		T65	3		T66	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T64	1		T65	2		T66	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T65	1		T66	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T130	1		T137	1		T138	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T64	2		T65	4		T66	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T64	1		T65	4		T66	4
auto[TlIntgErrData]	full_word	auto[0]	11	1			T64	1		T65	1		T130	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T66	2		T133	1		T134	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T64	1		T65	2		T66	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T64	1		T65	3		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T64	1		T66	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T133	1		T137	1		-	-