Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	777463	1			T1	3		T12	2833		T27	339
auto[1]	10622118	1			T1	3		T3	65181		T5	228
auto[2]	637264	1			T1	3		T12	2434		T27	193
auto[3]	10478539	1			T1	2		T3	64911		T5	241

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14241705	1			T3	4617		T5	469		T12	4973
auto[1]	2185485	1			T1	3		T3	20024		T12	666
auto[2]	2192626	1			T1	1		T3	19987		T12	550
auto[3]	3895568	1			T1	7		T3	85464		T12	65

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8253403

1

T1

11

T5

469

T12

6247

auto[1]

14261981

1

T3

130092

T12

7

T13

217482

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	278972	1			T12	2381		T27	274		T42	6593
auto[0]	auto[0]	auto[1]	28270	1			T1	1		T12	205		T27	29
auto[0]	auto[0]	auto[2]	28348	1			T12	226		T27	32		T42	666
auto[0]	auto[0]	auto[3]	7326	1			T1	2		T12	17		T27	4
auto[0]	auto[1]	auto[0]	3122207	1			T5	228		T12	335		T25	212
auto[0]	auto[1]	auto[1]	326388	1			T1	2		T12	232		T25	54
auto[0]	auto[1]	auto[2]	316741	1			T12	36		T25	61		T27	213
auto[0]	auto[1]	auto[3]	72010	1			T1	1		T12	22		T25	14
auto[0]	auto[2]	auto[0]	230695	1			T12	2073		T42	6065		T146	1982
auto[0]	auto[2]	auto[1]	23558	1			T12	213		T42	570		T146	213
auto[0]	auto[2]	auto[2]	26859	1			T1	1		T12	138		T27	176
auto[0]	auto[2]	auto[3]	5990	1			T1	2		T12	7		T27	17
auto[0]	auto[3]	auto[0]	3075244	1			T5	241		T12	178		T25	214
auto[0]	auto[3]	auto[1]	311821	1			T12	15		T25	51		T27	170
auto[0]	auto[3]	auto[2]	325614	1			T12	150		T25	51		T27	470
auto[0]	auto[3]	auto[3]	73360	1			T1	2		T12	19		T25	17
auto[1]	auto[0]	auto[0]	14656	1			T12	3		T42	10		T59	733
auto[1]	auto[0]	auto[1]	64654	1			T12	1		T42	1		T59	3237
auto[1]	auto[0]	auto[2]	64506	1			T42	3		T59	3326		T62	2370
auto[1]	auto[0]	auto[3]	290731	1			T59	14802		T62	10817		T105	4154
auto[1]	auto[1]	auto[0]	3757877	1			T3	2296		T13	89623		T25	1
auto[1]	auto[1]	auto[1]	703886	1			T3	9579		T13	9467		T27	1
auto[1]	auto[1]	auto[2]	687621	1			T3	10553		T13	8881		T43	5
auto[1]	auto[1]	auto[3]	1635388	1			T3	42753		T13	927		T44	1
auto[1]	auto[2]	auto[0]	11677	1			T12	3		T42	4		T59	709
auto[1]	auto[2]	auto[1]	52244	1			T42	2		T59	3084		T62	1400
auto[1]	auto[2]	auto[2]	52348	1			T59	2199		T62	2695		T105	830
auto[1]	auto[2]	auto[3]	233893	1			T59	10062		T62	11475		T105	3733
auto[1]	auto[3]	auto[0]	3750377	1			T3	2321		T13	89394		T43	56
auto[1]	auto[3]	auto[1]	674664	1			T3	10445		T13	9127		T43	3
auto[1]	auto[3]	auto[2]	690589	1			T3	9434		T13	9141		T27	1
auto[1]	auto[3]	auto[3]	1576870	1			T3	42711		T13	922		T59	10376