Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	316678644	190222	0	0
ctrl_regwen_rd_A	316678644	3473	0	0
exec_rd_A	316678644	3735	0	0
exec_regwen_rd_A	316678644	3711	0	0
readback_rd_A	316678644	1873	0	0
readback_regwen_rd_A	316678644	1869	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316678644	190222	0	0
T14	990	0	0	0
T20	76314	2443	0	0
T21	467899	0	0	0
T24	0	2494	0	0
T26	0	2515	0	0
T29	1906	0	0	0
T41	0	9772	0	0
T44	228227	0	0	0
T48	0	1446	0	0
T57	0	6368	0	0
T58	0	9383	0	0
T59	150191	0	0	0
T60	47286	0	0	0
T61	70040	0	0	0
T62	172429	0	0	0
T63	92380	0	0	0
T71	0	3415	0	0
T72	0	15767	0	0
T73	0	5209	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316678644	3473	0	0
T48	50221	152	0	0
T49	0	314	0	0
T50	0	170	0	0
T70	0	2	0	0
T71	0	242	0	0
T113	0	193	0	0
T114	0	428	0	0
T115	0	247	0	0
T116	0	429	0	0
T117	0	17	0	0
T118	11681	0	0	0
T119	120326	0	0	0
T120	289995	0	0	0
T121	1093	0	0	0
T122	1247	0	0	0
T123	826	0	0	0
T124	199627	0	0	0
T125	220599	0	0	0
T126	906393	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316678644	3735	0	0
T48	50221	85	0	0
T49	0	388	0	0
T50	0	237	0	0
T70	0	20	0	0
T71	0	293	0	0
T113	0	216	0	0
T114	0	344	0	0
T115	0	313	0	0
T116	0	495	0	0
T117	0	7	0	0
T118	11681	0	0	0
T119	120326	0	0	0
T120	289995	0	0	0
T121	1093	0	0	0
T122	1247	0	0	0
T123	826	0	0	0
T124	199627	0	0	0
T125	220599	0	0	0
T126	906393	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316678644	3711	0	0
T48	50221	146	0	0
T49	0	387	0	0
T50	0	180	0	0
T70	0	21	0	0
T71	0	341	0	0
T113	0	204	0	0
T114	0	393	0	0
T115	0	252	0	0
T116	0	449	0	0
T117	0	23	0	0
T118	11681	0	0	0
T119	120326	0	0	0
T120	289995	0	0	0
T121	1093	0	0	0
T122	1247	0	0	0
T123	826	0	0	0
T124	199627	0	0	0
T125	220599	0	0	0
T126	906393	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316678644	1873	0	0
T48	50221	140	0	0
T49	0	334	0	0
T50	0	159	0	0
T71	0	233	0	0
T113	0	215	0	0
T114	0	249	0	0
T115	0	172	0	0
T117	0	8	0	0
T118	11681	0	0	0
T119	120326	0	0	0
T120	289995	0	0	0
T121	1093	0	0	0
T122	1247	0	0	0
T123	826	0	0	0
T124	199627	0	0	0
T125	220599	0	0	0
T126	906393	0	0	0
T127	0	29	0	0
T128	0	37	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316678644	1869	0	0
T48	50221	90	0	0
T49	0	289	0	0
T50	0	179	0	0
T71	0	272	0	0
T113	0	229	0	0
T114	0	356	0	0
T115	0	219	0	0
T117	0	12	0	0
T118	11681	0	0	0
T119	120326	0	0	0
T120	289995	0	0	0
T121	1093	0	0	0
T122	1247	0	0	0
T123	826	0	0	0
T124	199627	0	0	0
T125	220599	0	0	0
T126	906393	0	0	0
T127	0	13	0	0
T128	0	6	0	0