| T798 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1406809517 |
|
|
Jul 07 05:41:29 PM PDT 24 |
Jul 07 05:42:28 PM PDT 24 |
151521566 ps |
| T50 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4057230754 |
|
|
Jul 07 05:41:49 PM PDT 24 |
Jul 07 05:43:16 PM PDT 24 |
4525278333 ps |
| T799 |
/workspace/coverage/default/40.sram_ctrl_executable.769655092 |
|
|
Jul 07 05:43:00 PM PDT 24 |
Jul 07 06:13:29 PM PDT 24 |
15032507251 ps |
| T800 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3604215001 |
|
|
Jul 07 05:43:40 PM PDT 24 |
Jul 07 05:43:48 PM PDT 24 |
4753110187 ps |
| T801 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2582151808 |
|
|
Jul 07 05:41:31 PM PDT 24 |
Jul 07 06:15:37 PM PDT 24 |
33211071355 ps |
| T802 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.2816153301 |
|
|
Jul 07 05:42:11 PM PDT 24 |
Jul 07 05:42:44 PM PDT 24 |
176608894 ps |
| T803 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2629799321 |
|
|
Jul 07 05:42:03 PM PDT 24 |
Jul 07 05:43:48 PM PDT 24 |
139532958 ps |
| T804 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1489466856 |
|
|
Jul 07 05:41:34 PM PDT 24 |
Jul 07 05:42:41 PM PDT 24 |
669306379 ps |
| T805 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3316635819 |
|
|
Jul 07 05:41:33 PM PDT 24 |
Jul 07 05:52:49 PM PDT 24 |
6652278461 ps |
| T806 |
/workspace/coverage/default/17.sram_ctrl_regwen.426279313 |
|
|
Jul 07 05:41:34 PM PDT 24 |
Jul 07 05:45:33 PM PDT 24 |
20352816141 ps |
| T807 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3605694414 |
|
|
Jul 07 05:42:17 PM PDT 24 |
Jul 07 05:42:18 PM PDT 24 |
642297187 ps |
| T808 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.4289380684 |
|
|
Jul 07 05:41:59 PM PDT 24 |
Jul 07 05:56:19 PM PDT 24 |
46455071752 ps |
| T809 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2278305618 |
|
|
Jul 07 05:41:25 PM PDT 24 |
Jul 07 05:41:32 PM PDT 24 |
227748833 ps |
| T810 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1774796541 |
|
|
Jul 07 05:43:24 PM PDT 24 |
Jul 07 05:43:29 PM PDT 24 |
150074840 ps |
| T811 |
/workspace/coverage/default/16.sram_ctrl_executable.2591838251 |
|
|
Jul 07 05:41:33 PM PDT 24 |
Jul 07 05:57:23 PM PDT 24 |
5962633408 ps |
| T812 |
/workspace/coverage/default/21.sram_ctrl_alert_test.228699211 |
|
|
Jul 07 05:41:37 PM PDT 24 |
Jul 07 05:41:38 PM PDT 24 |
44407595 ps |
| T813 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1492824870 |
|
|
Jul 07 05:43:38 PM PDT 24 |
Jul 07 06:02:52 PM PDT 24 |
4245682024 ps |
| T814 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4140132425 |
|
|
Jul 07 05:42:00 PM PDT 24 |
Jul 07 05:42:12 PM PDT 24 |
248728982 ps |
| T815 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.110366152 |
|
|
Jul 07 05:40:41 PM PDT 24 |
Jul 07 05:52:18 PM PDT 24 |
3481460263 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2862771589 |
|
|
Jul 07 05:40:35 PM PDT 24 |
Jul 07 05:59:09 PM PDT 24 |
18249927397 ps |
| T817 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3127848038 |
|
|
Jul 07 05:41:27 PM PDT 24 |
Jul 07 05:41:29 PM PDT 24 |
49462363 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_bijection.10463446 |
|
|
Jul 07 05:41:13 PM PDT 24 |
Jul 07 05:41:41 PM PDT 24 |
533164087 ps |
| T819 |
/workspace/coverage/default/1.sram_ctrl_alert_test.4226661206 |
|
|
Jul 07 05:40:39 PM PDT 24 |
Jul 07 05:40:43 PM PDT 24 |
15498914 ps |
| T820 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2981882081 |
|
|
Jul 07 05:41:23 PM PDT 24 |
Jul 07 05:41:31 PM PDT 24 |
1775717912 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.168814023 |
|
|
Jul 07 05:41:25 PM PDT 24 |
Jul 07 05:48:14 PM PDT 24 |
5466386920 ps |
| T822 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2197973233 |
|
|
Jul 07 05:43:59 PM PDT 24 |
Jul 07 05:44:06 PM PDT 24 |
893005892 ps |
| T823 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2434649132 |
|
|
Jul 07 05:42:41 PM PDT 24 |
Jul 07 05:43:16 PM PDT 24 |
95364197 ps |
| T824 |
/workspace/coverage/default/44.sram_ctrl_smoke.413834213 |
|
|
Jul 07 05:43:25 PM PDT 24 |
Jul 07 05:43:27 PM PDT 24 |
127323927 ps |
| T825 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2168009198 |
|
|
Jul 07 05:43:48 PM PDT 24 |
Jul 07 05:43:49 PM PDT 24 |
134706404 ps |
| T826 |
/workspace/coverage/default/47.sram_ctrl_bijection.3126083629 |
|
|
Jul 07 05:43:47 PM PDT 24 |
Jul 07 05:44:17 PM PDT 24 |
2151236599 ps |
| T827 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1958161553 |
|
|
Jul 07 05:41:06 PM PDT 24 |
Jul 07 06:31:20 PM PDT 24 |
207132635043 ps |
| T828 |
/workspace/coverage/default/26.sram_ctrl_executable.3696989849 |
|
|
Jul 07 05:41:59 PM PDT 24 |
Jul 07 06:01:05 PM PDT 24 |
11447635207 ps |
| T829 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.542772809 |
|
|
Jul 07 05:40:39 PM PDT 24 |
Jul 07 05:41:08 PM PDT 24 |
334674140 ps |
| T830 |
/workspace/coverage/default/43.sram_ctrl_executable.2509991177 |
|
|
Jul 07 05:43:21 PM PDT 24 |
Jul 07 06:10:15 PM PDT 24 |
26376908589 ps |
| T831 |
/workspace/coverage/default/5.sram_ctrl_regwen.808815584 |
|
|
Jul 07 05:41:11 PM PDT 24 |
Jul 07 06:03:34 PM PDT 24 |
42655854285 ps |
| T832 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.513247882 |
|
|
Jul 07 05:41:46 PM PDT 24 |
Jul 07 05:41:58 PM PDT 24 |
661510372 ps |
| T833 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1220171396 |
|
|
Jul 07 05:43:41 PM PDT 24 |
Jul 07 05:48:44 PM PDT 24 |
4019852726 ps |
| T834 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1430096876 |
|
|
Jul 07 05:41:04 PM PDT 24 |
Jul 07 05:41:10 PM PDT 24 |
259672360 ps |
| T835 |
/workspace/coverage/default/7.sram_ctrl_partial_access.4133095627 |
|
|
Jul 07 05:41:15 PM PDT 24 |
Jul 07 05:41:23 PM PDT 24 |
1478858068 ps |
| T836 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1331487263 |
|
|
Jul 07 05:41:29 PM PDT 24 |
Jul 07 06:10:56 PM PDT 24 |
131313404882 ps |
| T837 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3378307765 |
|
|
Jul 07 05:41:52 PM PDT 24 |
Jul 07 05:42:50 PM PDT 24 |
3017505619 ps |
| T838 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2762814010 |
|
|
Jul 07 05:41:51 PM PDT 24 |
Jul 07 05:41:55 PM PDT 24 |
196041166 ps |
| T839 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3429681995 |
|
|
Jul 07 05:41:30 PM PDT 24 |
Jul 07 05:41:34 PM PDT 24 |
235325527 ps |
| T840 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2022631239 |
|
|
Jul 07 05:42:29 PM PDT 24 |
Jul 07 05:42:35 PM PDT 24 |
460018411 ps |
| T841 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3154673644 |
|
|
Jul 07 05:41:57 PM PDT 24 |
Jul 07 05:41:57 PM PDT 24 |
70559697 ps |
| T842 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1000137029 |
|
|
Jul 07 05:43:34 PM PDT 24 |
Jul 07 05:50:08 PM PDT 24 |
6565111439 ps |
| T843 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3426194708 |
|
|
Jul 07 05:41:24 PM PDT 24 |
Jul 07 05:58:45 PM PDT 24 |
17088098922 ps |
| T844 |
/workspace/coverage/default/11.sram_ctrl_regwen.3253800493 |
|
|
Jul 07 05:41:19 PM PDT 24 |
Jul 07 06:01:28 PM PDT 24 |
52306651498 ps |
| T845 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3523742162 |
|
|
Jul 07 05:41:22 PM PDT 24 |
Jul 07 05:41:27 PM PDT 24 |
159232572 ps |
| T846 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.831472399 |
|
|
Jul 07 05:43:30 PM PDT 24 |
Jul 07 05:45:26 PM PDT 24 |
1074070154 ps |
| T847 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1773649573 |
|
|
Jul 07 05:42:24 PM PDT 24 |
Jul 07 05:56:39 PM PDT 24 |
2824788042 ps |
| T848 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.4215935746 |
|
|
Jul 07 05:41:09 PM PDT 24 |
Jul 07 05:41:11 PM PDT 24 |
36347962 ps |
| T849 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3952296544 |
|
|
Jul 07 05:41:33 PM PDT 24 |
Jul 07 05:43:30 PM PDT 24 |
5323730027 ps |
| T850 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1079339025 |
|
|
Jul 07 05:42:20 PM PDT 24 |
Jul 07 05:42:24 PM PDT 24 |
334451870 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_smoke.2950611799 |
|
|
Jul 07 05:40:38 PM PDT 24 |
Jul 07 05:43:01 PM PDT 24 |
2721018734 ps |
| T852 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1613765596 |
|
|
Jul 07 05:43:21 PM PDT 24 |
Jul 07 05:43:38 PM PDT 24 |
322127055 ps |
| T853 |
/workspace/coverage/default/17.sram_ctrl_smoke.1558641421 |
|
|
Jul 07 05:41:29 PM PDT 24 |
Jul 07 05:42:11 PM PDT 24 |
367992184 ps |
| T854 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2981208672 |
|
|
Jul 07 05:42:30 PM PDT 24 |
Jul 07 05:42:37 PM PDT 24 |
1179849093 ps |
| T855 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2999848905 |
|
|
Jul 07 05:42:52 PM PDT 24 |
Jul 07 05:43:00 PM PDT 24 |
911608867 ps |
| T856 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.4153072167 |
|
|
Jul 07 05:40:47 PM PDT 24 |
Jul 07 05:40:54 PM PDT 24 |
608335616 ps |
| T857 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.418890092 |
|
|
Jul 07 05:41:27 PM PDT 24 |
Jul 07 05:43:55 PM PDT 24 |
1576993844 ps |
| T858 |
/workspace/coverage/default/34.sram_ctrl_smoke.2277892876 |
|
|
Jul 07 05:42:24 PM PDT 24 |
Jul 07 05:42:42 PM PDT 24 |
2602924953 ps |
| T859 |
/workspace/coverage/default/7.sram_ctrl_smoke.3941103224 |
|
|
Jul 07 05:41:21 PM PDT 24 |
Jul 07 05:41:37 PM PDT 24 |
257385067 ps |
| T860 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.3135702791 |
|
|
Jul 07 05:42:00 PM PDT 24 |
Jul 07 05:42:12 PM PDT 24 |
460508164 ps |
| T861 |
/workspace/coverage/default/47.sram_ctrl_regwen.1994907602 |
|
|
Jul 07 05:43:47 PM PDT 24 |
Jul 07 06:20:13 PM PDT 24 |
20945354118 ps |
| T862 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2432208750 |
|
|
Jul 07 05:42:18 PM PDT 24 |
Jul 07 05:43:52 PM PDT 24 |
197379513 ps |
| T863 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.446925329 |
|
|
Jul 07 05:42:32 PM PDT 24 |
Jul 07 05:44:28 PM PDT 24 |
185439943 ps |
| T864 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.4204067661 |
|
|
Jul 07 05:42:13 PM PDT 24 |
Jul 07 05:54:15 PM PDT 24 |
15897347406 ps |
| T865 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3354422764 |
|
|
Jul 07 05:43:33 PM PDT 24 |
Jul 07 06:02:47 PM PDT 24 |
48434179301 ps |
| T866 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2385337952 |
|
|
Jul 07 05:40:54 PM PDT 24 |
Jul 07 05:41:01 PM PDT 24 |
64365529 ps |
| T867 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2833034629 |
|
|
Jul 07 05:41:13 PM PDT 24 |
Jul 07 05:42:02 PM PDT 24 |
239134474 ps |
| T868 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.584003571 |
|
|
Jul 07 05:42:33 PM PDT 24 |
Jul 07 05:45:44 PM PDT 24 |
5042795022 ps |
| T869 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1616297312 |
|
|
Jul 07 05:41:23 PM PDT 24 |
Jul 07 05:41:28 PM PDT 24 |
151313537 ps |
| T870 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3486415835 |
|
|
Jul 07 05:41:25 PM PDT 24 |
Jul 07 05:41:27 PM PDT 24 |
60003020 ps |
| T871 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2573518991 |
|
|
Jul 07 05:41:13 PM PDT 24 |
Jul 07 05:46:22 PM PDT 24 |
4143221995 ps |
| T872 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1682786777 |
|
|
Jul 07 05:41:51 PM PDT 24 |
Jul 07 05:41:57 PM PDT 24 |
110618982 ps |
| T873 |
/workspace/coverage/default/23.sram_ctrl_executable.4242672790 |
|
|
Jul 07 05:41:39 PM PDT 24 |
Jul 07 05:45:16 PM PDT 24 |
2853293337 ps |
| T874 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1811978230 |
|
|
Jul 07 05:41:35 PM PDT 24 |
Jul 07 05:41:46 PM PDT 24 |
845802260 ps |
| T875 |
/workspace/coverage/default/7.sram_ctrl_alert_test.4158573648 |
|
|
Jul 07 05:41:09 PM PDT 24 |
Jul 07 05:41:10 PM PDT 24 |
36045395 ps |
| T876 |
/workspace/coverage/default/38.sram_ctrl_executable.3975175412 |
|
|
Jul 07 05:42:52 PM PDT 24 |
Jul 07 06:01:01 PM PDT 24 |
14062364785 ps |
| T877 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2234929253 |
|
|
Jul 07 05:43:00 PM PDT 24 |
Jul 07 05:43:04 PM PDT 24 |
381081744 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1099349267 |
|
|
Jul 07 05:41:49 PM PDT 24 |
Jul 07 05:44:05 PM PDT 24 |
536779984 ps |
| T879 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1017347195 |
|
|
Jul 07 05:40:40 PM PDT 24 |
Jul 07 05:49:23 PM PDT 24 |
6948575592 ps |
| T880 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.179837089 |
|
|
Jul 07 05:41:20 PM PDT 24 |
Jul 07 05:45:54 PM PDT 24 |
2684136199 ps |
| T881 |
/workspace/coverage/default/6.sram_ctrl_regwen.3757158716 |
|
|
Jul 07 05:41:07 PM PDT 24 |
Jul 07 05:42:19 PM PDT 24 |
5251956969 ps |
| T882 |
/workspace/coverage/default/9.sram_ctrl_smoke.2362258941 |
|
|
Jul 07 05:41:15 PM PDT 24 |
Jul 07 05:41:39 PM PDT 24 |
2359487083 ps |
| T883 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.339386368 |
|
|
Jul 07 05:41:30 PM PDT 24 |
Jul 07 05:41:39 PM PDT 24 |
137233521 ps |
| T884 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3636848821 |
|
|
Jul 07 05:41:34 PM PDT 24 |
Jul 07 05:41:38 PM PDT 24 |
91319555 ps |
| T885 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3789616349 |
|
|
Jul 07 05:41:12 PM PDT 24 |
Jul 07 05:41:14 PM PDT 24 |
216226527 ps |
| T886 |
/workspace/coverage/default/11.sram_ctrl_bijection.4250754733 |
|
|
Jul 07 05:41:18 PM PDT 24 |
Jul 07 05:41:47 PM PDT 24 |
1815448603 ps |
| T887 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1169080881 |
|
|
Jul 07 05:42:19 PM PDT 24 |
Jul 07 05:46:53 PM PDT 24 |
7438251060 ps |
| T888 |
/workspace/coverage/default/49.sram_ctrl_executable.1580959863 |
|
|
Jul 07 05:44:01 PM PDT 24 |
Jul 07 05:58:19 PM PDT 24 |
31973999805 ps |
| T889 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.578328679 |
|
|
Jul 07 05:41:29 PM PDT 24 |
Jul 07 05:41:58 PM PDT 24 |
341270693 ps |
| T890 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.55401666 |
|
|
Jul 07 05:41:18 PM PDT 24 |
Jul 07 05:41:19 PM PDT 24 |
29217229 ps |
| T891 |
/workspace/coverage/default/18.sram_ctrl_alert_test.4170448436 |
|
|
Jul 07 05:41:37 PM PDT 24 |
Jul 07 05:41:38 PM PDT 24 |
20357280 ps |
| T31 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3677213058 |
|
|
Jul 07 05:41:14 PM PDT 24 |
Jul 07 05:41:23 PM PDT 24 |
538525013 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_executable.2142586878 |
|
|
Jul 07 05:41:28 PM PDT 24 |
Jul 07 06:04:24 PM PDT 24 |
14020629681 ps |
| T893 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.4236563673 |
|
|
Jul 07 05:41:21 PM PDT 24 |
Jul 07 05:41:23 PM PDT 24 |
633743763 ps |
| T894 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3447340726 |
|
|
Jul 07 05:42:27 PM PDT 24 |
Jul 07 05:47:18 PM PDT 24 |
9720424615 ps |
| T895 |
/workspace/coverage/default/23.sram_ctrl_regwen.3644476205 |
|
|
Jul 07 05:41:40 PM PDT 24 |
Jul 07 06:01:01 PM PDT 24 |
20579586653 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_smoke.2982017453 |
|
|
Jul 07 05:41:17 PM PDT 24 |
Jul 07 05:43:46 PM PDT 24 |
585538317 ps |
| T897 |
/workspace/coverage/default/39.sram_ctrl_stress_all.4132259713 |
|
|
Jul 07 05:42:59 PM PDT 24 |
Jul 07 06:24:16 PM PDT 24 |
10363071967 ps |
| T898 |
/workspace/coverage/default/24.sram_ctrl_bijection.388483669 |
|
|
Jul 07 05:41:37 PM PDT 24 |
Jul 07 05:42:32 PM PDT 24 |
819041612 ps |
| T899 |
/workspace/coverage/default/16.sram_ctrl_bijection.4217909164 |
|
|
Jul 07 05:41:41 PM PDT 24 |
Jul 07 05:42:41 PM PDT 24 |
3729114870 ps |
| T900 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2278938880 |
|
|
Jul 07 05:41:14 PM PDT 24 |
Jul 07 05:41:23 PM PDT 24 |
728378019 ps |
| T901 |
/workspace/coverage/default/36.sram_ctrl_bijection.184495080 |
|
|
Jul 07 05:42:34 PM PDT 24 |
Jul 07 05:43:40 PM PDT 24 |
1969217281 ps |
| T902 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3647867927 |
|
|
Jul 07 05:41:09 PM PDT 24 |
Jul 07 05:41:44 PM PDT 24 |
168834923 ps |
| T903 |
/workspace/coverage/default/7.sram_ctrl_regwen.473431022 |
|
|
Jul 07 05:41:23 PM PDT 24 |
Jul 07 05:48:38 PM PDT 24 |
8240074839 ps |
| T904 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2385649554 |
|
|
Jul 07 05:43:41 PM PDT 24 |
Jul 07 05:46:56 PM PDT 24 |
11976820142 ps |
| T905 |
/workspace/coverage/default/31.sram_ctrl_partial_access.598113366 |
|
|
Jul 07 05:42:22 PM PDT 24 |
Jul 07 05:42:39 PM PDT 24 |
193250192 ps |
| T906 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1366919190 |
|
|
Jul 07 05:41:32 PM PDT 24 |
Jul 07 05:41:45 PM PDT 24 |
81524382 ps |
| T907 |
/workspace/coverage/default/2.sram_ctrl_partial_access.737168850 |
|
|
Jul 07 05:40:43 PM PDT 24 |
Jul 07 05:40:54 PM PDT 24 |
448876101 ps |
| T908 |
/workspace/coverage/default/3.sram_ctrl_bijection.2905915830 |
|
|
Jul 07 05:40:56 PM PDT 24 |
Jul 07 05:42:19 PM PDT 24 |
21696308621 ps |
| T909 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.1943937301 |
|
|
Jul 07 05:41:29 PM PDT 24 |
Jul 07 05:41:35 PM PDT 24 |
3523008888 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.8552447 |
|
|
Jul 07 05:41:51 PM PDT 24 |
Jul 07 05:41:57 PM PDT 24 |
645589607 ps |
| T911 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.802442657 |
|
|
Jul 07 05:42:24 PM PDT 24 |
Jul 07 05:42:29 PM PDT 24 |
72809285 ps |
| T912 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.4159958872 |
|
|
Jul 07 05:41:22 PM PDT 24 |
Jul 07 06:01:56 PM PDT 24 |
9919738897 ps |
| T913 |
/workspace/coverage/default/13.sram_ctrl_alert_test.4282489549 |
|
|
Jul 07 05:41:19 PM PDT 24 |
Jul 07 05:41:20 PM PDT 24 |
24030849 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_stress_all.502810630 |
|
|
Jul 07 05:43:57 PM PDT 24 |
Jul 07 06:59:29 PM PDT 24 |
90346096980 ps |
| T915 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3199062220 |
|
|
Jul 07 05:41:29 PM PDT 24 |
Jul 07 05:41:53 PM PDT 24 |
105040386 ps |
| T916 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.199178890 |
|
|
Jul 07 05:43:19 PM PDT 24 |
Jul 07 05:43:20 PM PDT 24 |
69641065 ps |
| T917 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2241291277 |
|
|
Jul 07 05:41:41 PM PDT 24 |
Jul 07 06:02:30 PM PDT 24 |
5640199163 ps |
| T918 |
/workspace/coverage/default/42.sram_ctrl_partial_access.862940295 |
|
|
Jul 07 05:43:13 PM PDT 24 |
Jul 07 05:45:39 PM PDT 24 |
678906207 ps |
| T919 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3855868640 |
|
|
Jul 07 05:41:21 PM PDT 24 |
Jul 07 05:41:22 PM PDT 24 |
40676858 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2191363897 |
|
|
Jul 07 05:42:21 PM PDT 24 |
Jul 07 05:47:05 PM PDT 24 |
15609271404 ps |
| T921 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1982944344 |
|
|
Jul 07 05:42:05 PM PDT 24 |
Jul 07 05:42:12 PM PDT 24 |
178858065 ps |
| T922 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.666338943 |
|
|
Jul 07 05:41:36 PM PDT 24 |
Jul 07 05:41:46 PM PDT 24 |
183295575 ps |
| T923 |
/workspace/coverage/default/16.sram_ctrl_smoke.3419275224 |
|
|
Jul 07 05:41:48 PM PDT 24 |
Jul 07 05:41:51 PM PDT 24 |
1184803520 ps |
| T924 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.576594118 |
|
|
Jul 07 05:42:02 PM PDT 24 |
Jul 07 06:06:54 PM PDT 24 |
16639778508 ps |
| T925 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2645298681 |
|
|
Jul 07 05:41:43 PM PDT 24 |
Jul 07 05:47:03 PM PDT 24 |
12251695563 ps |
| T926 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.591045624 |
|
|
Jul 07 05:42:34 PM PDT 24 |
Jul 07 05:44:45 PM PDT 24 |
319248678 ps |
| T927 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.174785929 |
|
|
Jul 07 05:42:10 PM PDT 24 |
Jul 07 05:42:22 PM PDT 24 |
1700050850 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2573716641 |
|
|
Jul 07 05:42:08 PM PDT 24 |
Jul 07 05:55:55 PM PDT 24 |
35695949336 ps |
| T32 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1942496839 |
|
|
Jul 07 05:40:40 PM PDT 24 |
Jul 07 05:40:48 PM PDT 24 |
703361271 ps |
| T929 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4056585389 |
|
|
Jul 07 05:41:06 PM PDT 24 |
Jul 07 05:41:10 PM PDT 24 |
642724876 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1218437711 |
|
|
Jul 07 05:38:01 PM PDT 24 |
Jul 07 05:38:03 PM PDT 24 |
96364067 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3189865892 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
51889604 ps |
| T64 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1760811160 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:18 PM PDT 24 |
86191631 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.141588470 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:10 PM PDT 24 |
12645210 ps |
| T930 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2853142122 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:12 PM PDT 24 |
38011698 ps |
| T112 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1794553939 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
21589355 ps |
| T102 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3726718248 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
3797722384 ps |
| T931 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.509601446 |
|
|
Jul 07 05:38:19 PM PDT 24 |
Jul 07 05:38:21 PM PDT 24 |
25392243 ps |
| T932 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2881030507 |
|
|
Jul 07 05:38:01 PM PDT 24 |
Jul 07 05:38:06 PM PDT 24 |
107334298 ps |
| T103 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.811922580 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
23362157 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1727157429 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
2436284255 ps |
| T75 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2754518439 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:18 PM PDT 24 |
799849903 ps |
| T117 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2996078344 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:13 PM PDT 24 |
60837680 ps |
| T127 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2758085945 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
148949456 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3510835734 |
|
|
Jul 07 05:38:03 PM PDT 24 |
Jul 07 05:38:05 PM PDT 24 |
223796889 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2427571848 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
738637242 ps |
| T933 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3639831038 |
|
|
Jul 07 05:38:17 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
114566422 ps |
| T934 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2972501506 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
38249955 ps |
| T77 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2724467422 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
27409599 ps |
| T78 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.892598275 |
|
|
Jul 07 05:38:21 PM PDT 24 |
Jul 07 05:38:23 PM PDT 24 |
16953587 ps |
| T66 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4287577309 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:20 PM PDT 24 |
200883836 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3531671096 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
126784404 ps |
| T79 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1581346306 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:09 PM PDT 24 |
30694175 ps |
| T80 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3131723007 |
|
|
Jul 07 05:38:01 PM PDT 24 |
Jul 07 05:38:03 PM PDT 24 |
222152186 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.609158188 |
|
|
Jul 07 05:38:13 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
21060139 ps |
| T82 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.764643201 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:13 PM PDT 24 |
22054022 ps |
| T130 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3785395577 |
|
|
Jul 07 05:38:28 PM PDT 24 |
Jul 07 05:38:31 PM PDT 24 |
221010016 ps |
| T128 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.542189137 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
77272721 ps |
| T131 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2462604854 |
|
|
Jul 07 05:38:07 PM PDT 24 |
Jul 07 05:38:10 PM PDT 24 |
1560602385 ps |
| T936 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1174345512 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:20 PM PDT 24 |
161296897 ps |
| T937 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.147184605 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:08 PM PDT 24 |
67312488 ps |
| T938 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4119798663 |
|
|
Jul 07 05:38:03 PM PDT 24 |
Jul 07 05:38:04 PM PDT 24 |
16719914 ps |
| T939 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1552212854 |
|
|
Jul 07 05:38:14 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
36608181 ps |
| T940 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2052287597 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
14619854 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1345852611 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
25416383 ps |
| T132 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.283221772 |
|
|
Jul 07 05:38:04 PM PDT 24 |
Jul 07 05:38:07 PM PDT 24 |
883059146 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3223882238 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:09 PM PDT 24 |
95976332 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2386602643 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:18 PM PDT 24 |
93555954 ps |
| T943 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.464208953 |
|
|
Jul 07 05:38:01 PM PDT 24 |
Jul 07 05:38:03 PM PDT 24 |
14126868 ps |
| T944 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2684610977 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:11 PM PDT 24 |
31533877 ps |
| T133 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3240499305 |
|
|
Jul 07 05:38:19 PM PDT 24 |
Jul 07 05:38:22 PM PDT 24 |
606833047 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1574682999 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:07 PM PDT 24 |
14414802 ps |
| T946 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3415321934 |
|
|
Jul 07 05:38:27 PM PDT 24 |
Jul 07 05:38:32 PM PDT 24 |
158102745 ps |
| T947 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2653755048 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
81158092 ps |
| T84 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2428921535 |
|
|
Jul 07 05:38:07 PM PDT 24 |
Jul 07 05:38:08 PM PDT 24 |
32369008 ps |
| T85 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3599493931 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
32255791 ps |
| T134 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2589855239 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
663712682 ps |
| T948 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.888701727 |
|
|
Jul 07 05:38:14 PM PDT 24 |
Jul 07 05:38:16 PM PDT 24 |
101236169 ps |
| T104 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1812788976 |
|
|
Jul 07 05:38:17 PM PDT 24 |
Jul 07 05:38:21 PM PDT 24 |
1534017368 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2112612561 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:21 PM PDT 24 |
6567624820 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1870036741 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:12 PM PDT 24 |
14547046 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.952783754 |
|
|
Jul 07 05:38:27 PM PDT 24 |
Jul 07 05:38:29 PM PDT 24 |
57065324 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4168926728 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:11 PM PDT 24 |
25064148 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1962359892 |
|
|
Jul 07 05:38:13 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
42162947 ps |
| T953 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2853855436 |
|
|
Jul 07 05:38:18 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
116807056 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.730345153 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
138767581 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3386632889 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
1322969258 ps |
| T88 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3281412058 |
|
|
Jul 07 05:38:27 PM PDT 24 |
Jul 07 05:38:30 PM PDT 24 |
326135565 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.135850742 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:18 PM PDT 24 |
1585642068 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.316455717 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:18 PM PDT 24 |
23850010 ps |
| T956 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2558918801 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
529542231 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.124196559 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:13 PM PDT 24 |
76688820 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.691466655 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:08 PM PDT 24 |
17715369 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2758832117 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:12 PM PDT 24 |
34878169 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.215560318 |
|
|
Jul 07 05:38:01 PM PDT 24 |
Jul 07 05:38:05 PM PDT 24 |
329511276 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1191607378 |
|
|
Jul 07 05:38:28 PM PDT 24 |
Jul 07 05:38:29 PM PDT 24 |
39281716 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3654773783 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
25330690 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3834466648 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
19547749 ps |
| T90 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.590657277 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:10 PM PDT 24 |
853539275 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1799026689 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:13 PM PDT 24 |
365435647 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.944876379 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
61012643 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2095391021 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
44868300 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2192396881 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
134167585 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2731920025 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:11 PM PDT 24 |
110110844 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4171302832 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:07 PM PDT 24 |
88760129 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1352378814 |
|
|
Jul 07 05:38:28 PM PDT 24 |
Jul 07 05:38:30 PM PDT 24 |
894590673 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3183903054 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
2146501642 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4185079004 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:13 PM PDT 24 |
37516991 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1058656017 |
|
|
Jul 07 05:38:25 PM PDT 24 |
Jul 07 05:38:28 PM PDT 24 |
204381420 ps |
| T136 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1651659105 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
651385695 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2152617817 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:20 PM PDT 24 |
309692442 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2598856257 |
|
|
Jul 07 05:38:13 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
84404195 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.187196433 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
206619695 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2125136933 |
|
|
Jul 07 05:38:09 PM PDT 24 |
Jul 07 05:38:12 PM PDT 24 |
162222273 ps |
| T137 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.652860331 |
|
|
Jul 07 05:38:16 PM PDT 24 |
Jul 07 05:38:19 PM PDT 24 |
170584673 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.600439635 |
|
|
Jul 07 05:38:28 PM PDT 24 |
Jul 07 05:38:29 PM PDT 24 |
117692986 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2172462835 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
111984150 ps |
| T100 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2019020792 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
1300033041 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.288217752 |
|
|
Jul 07 05:38:08 PM PDT 24 |
Jul 07 05:38:11 PM PDT 24 |
160814225 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1956186329 |
|
|
Jul 07 05:38:04 PM PDT 24 |
Jul 07 05:38:08 PM PDT 24 |
1702172763 ps |
| T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3242957061 |
|
|
Jul 07 05:38:13 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
13748963 ps |
| T99 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1836264006 |
|
|
Jul 07 05:38:13 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
59090531 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2507066652 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:12 PM PDT 24 |
13721730 ps |
| T982 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.909305546 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
26381377 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3370103293 |
|
|
Jul 07 05:38:12 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
13583309 ps |
| T984 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2865582044 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:15 PM PDT 24 |
191778107 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3435912615 |
|
|
Jul 07 05:38:01 PM PDT 24 |
Jul 07 05:38:04 PM PDT 24 |
67756877 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3374740601 |
|
|
Jul 07 05:38:21 PM PDT 24 |
Jul 07 05:38:22 PM PDT 24 |
31240228 ps |
| T987 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1922453660 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:20 PM PDT 24 |
41486099 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.129573155 |
|
|
Jul 07 05:38:20 PM PDT 24 |
Jul 07 05:38:23 PM PDT 24 |
66058077 ps |
| T101 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2961988938 |
|
|
Jul 07 05:38:18 PM PDT 24 |
Jul 07 05:38:20 PM PDT 24 |
530380842 ps |
| T989 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3677049081 |
|
|
Jul 07 05:38:15 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
26207714 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4093734168 |
|
|
Jul 07 05:38:02 PM PDT 24 |
Jul 07 05:38:06 PM PDT 24 |
836373051 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.745576145 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:08 PM PDT 24 |
14500129 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3829536794 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
16446660 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.591834667 |
|
|
Jul 07 05:38:03 PM PDT 24 |
Jul 07 05:38:04 PM PDT 24 |
49840065 ps |
| T135 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2911116402 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
229145165 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.507043322 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:18 PM PDT 24 |
812784235 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1620915007 |
|
|
Jul 07 05:38:10 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
63224553 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2481174161 |
|
|
Jul 07 05:38:18 PM PDT 24 |
Jul 07 05:38:23 PM PDT 24 |
135176208 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1272721335 |
|
|
Jul 07 05:38:17 PM PDT 24 |
Jul 07 05:38:20 PM PDT 24 |
520344768 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4106560457 |
|
|
Jul 07 05:38:22 PM PDT 24 |
Jul 07 05:38:24 PM PDT 24 |
33621157 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2810279483 |
|
|
Jul 07 05:38:14 PM PDT 24 |
Jul 07 05:38:17 PM PDT 24 |
370076308 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.846315989 |
|
|
Jul 07 05:38:11 PM PDT 24 |
Jul 07 05:38:14 PM PDT 24 |
60644282 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1106925610 |
|
|
Jul 07 05:38:06 PM PDT 24 |
Jul 07 05:38:07 PM PDT 24 |
99188343 ps |