Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 145648660 1 T1 7372 T3 810206 T5 69632
instr_valid_dis 111127665 1 T1 7372 T3 810206 T5 69632
instr_en 22414347 1 T18 320 T21 3992 T7 132562



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 11960642 1 T11 107776 T18 5594 T21 26584
sram_ifetch_valid_disable 110524984 1 T1 7372 T3 810206 T5 69632
sram_ifetch_enable 23163034 1 T11 64230 T21 46154 T7 275516



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 145648660 1 T1 7372 T3 810206 T5 69632
hw_debug_en_valid_off 111510815 1 T1 7372 T3 810206 T5 69632
hw_debug_en_on 23079498 1 T11 253010 T18 14890 T21 64626



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 110524984 1 T1 7372 T3 810206 T5 69632
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 97305376 1 T1 7372 T3 810206 T5 69632
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 8340595 1 T21 3992 T7 457240 T55 44
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 4442477 1 T11 28410 T18 5274 T21 152
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 1352073 1 T11 28410 T18 5274 T19 21132
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 2091658 1 T7 53844 T62 68974 T135 17538
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 5634253 1 T11 75424 T18 320 T7 526910
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 2219023 1 T11 75424 T19 38372 T20 6586
hw_debug_en_on sram_ifetch_invalid_disable instr_en 2482688 1 T18 320 T7 526910 T55 32840
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 8239240 1 T11 140596 T18 14570 T21 64626
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 3247782 1 T11 140596 T18 14570 T21 64572
hw_debug_en_on sram_ifetch_valid_disable instr_en 3250208 1 T7 149582 T55 44 T19 14020


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 8702342 1 T7 275516 T55 42486 T22 15216
lc_exec_en 9206005 1 T11 36990 T7 52086 T55 42486
valid_exec_dis 107317943 1 T1 7372 T3 810206 T5 69632
invalid_exec_dis 35123676 1 T11 172006 T18 5594 T21 72738

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