Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43822261	1			T1	318		T3	368352		T5	34816
triple_byte_access	2474033	1			T1	6		T3	7375		T4	23
halfword_access	3714662	1			T1	6		T3	10982		T4	18
byte_access	4957662	1			T1	13		T3	14668		T4	29
zero_access	1247896	1			T1	2		T3	3726		T4	11

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28052345

1

T1

166

T3

202762

T5

17408

auto[1]

28164169

1

T1

179

T3

202341

T5

17408

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21861528	1			T1	154		T3	184329		T5	17408
auto[0]	triple_byte_access	1233757	1			T1	3		T3	3665		T4	10
auto[0]	halfword_access	1851771	1			T1	3		T3	5524		T4	8
auto[0]	byte_access	2478516	1			T1	6		T3	7356		T4	20
auto[0]	zero_access	626773	1			T3	1888		T4	5		T9	155
auto[1]	word_access	21960733	1			T1	164		T3	184023		T5	17408
auto[1]	triple_byte_access	1240276	1			T1	3		T3	3710		T4	13
auto[1]	halfword_access	1862891	1			T1	3		T3	5458		T4	10
auto[1]	byte_access	2479146	1			T1	7		T3	7312		T4	9
auto[1]	zero_access	621123	1			T1	2		T3	1838		T4	6