Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14074293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58532663

1

T1

3939

T2

54

T4

162683

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36206788	1			T1	2415		T2	364		T4	89837
values[0x0]	16796067	1			T1	1134		T2	202		T4	43068
values[0x1]	19604101	1			T1	1240		T2	420		T4	46127

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7012807	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65594149

1

T1

4355

T2

448

T4

170826

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	280451	1			T1	23		T4	714		T9	26
valid_sources[0x01]	263138	1			T1	10		T4	663		T5	3
valid_sources[0x02]	251949	1			T1	25		T4	754		T5	6
valid_sources[0x03]	261128	1			T1	13		T4	752		T5	2
valid_sources[0x04]	280547	1			T1	6		T2	1		T4	677
valid_sources[0x05]	285905	1			T1	21		T2	1		T4	717
valid_sources[0x06]	263764	1			T1	27		T2	3		T4	713
valid_sources[0x07]	288185	1			T1	10		T2	4		T4	639
valid_sources[0x08]	256884	1			T1	9		T2	1		T4	635
valid_sources[0x09]	278391	1			T1	10		T4	668		T5	5
valid_sources[0x0a]	295776	1			T1	16		T2	10		T4	639
valid_sources[0x0b]	288919	1			T1	16		T2	11		T4	676
valid_sources[0x0c]	343454	1			T1	13		T2	1		T4	754
valid_sources[0x0d]	293015	1			T1	25		T4	762		T5	4
valid_sources[0x0e]	278488	1			T1	18		T2	10		T4	716
valid_sources[0x0f]	256378	1			T1	15		T2	5		T4	745
valid_sources[0x10]	258844	1			T1	31		T4	677		T5	1
valid_sources[0x11]	276669	1			T1	16		T2	3		T4	702
valid_sources[0x12]	320323	1			T1	16		T4	773		T5	4
valid_sources[0x13]	272874	1			T1	26		T2	6		T4	710
valid_sources[0x14]	278457	1			T1	21		T4	679		T9	32
valid_sources[0x15]	295871	1			T1	19		T2	7		T4	732
valid_sources[0x16]	256135	1			T1	42		T2	2		T4	716
valid_sources[0x17]	374621	1			T1	13		T4	738		T5	7
valid_sources[0x18]	287904	1			T1	21		T4	673		T9	32
valid_sources[0x19]	256516	1			T1	16		T4	652		T5	2
valid_sources[0x1a]	280945	1			T1	19		T4	680		T5	4
valid_sources[0x1b]	268042	1			T1	21		T2	3		T4	676
valid_sources[0x1c]	266984	1			T1	23		T2	7		T4	751
valid_sources[0x1d]	296752	1			T1	14		T2	2		T4	679
valid_sources[0x1e]	257124	1			T1	23		T2	5		T4	701
valid_sources[0x1f]	263107	1			T1	26		T2	5		T4	717
valid_sources[0x20]	273457	1			T1	18		T2	2		T4	699
valid_sources[0x21]	272376	1			T1	14		T2	2		T4	731
valid_sources[0x22]	292028	1			T1	11		T2	1		T4	764
valid_sources[0x23]	269752	1			T1	16		T2	4		T4	662
valid_sources[0x24]	260917	1			T1	13		T2	12		T4	690
valid_sources[0x25]	259738	1			T1	29		T2	2		T4	637
valid_sources[0x26]	261812	1			T1	20		T2	11		T4	705
valid_sources[0x27]	281613	1			T1	21		T4	703		T5	6
valid_sources[0x28]	313688	1			T1	20		T2	2		T4	750
valid_sources[0x29]	272171	1			T1	19		T4	656		T9	44
valid_sources[0x2a]	297374	1			T1	18		T2	6		T4	701
valid_sources[0x2b]	331514	1			T1	11		T2	4		T4	725
valid_sources[0x2c]	271347	1			T1	30		T2	2		T4	721
valid_sources[0x2d]	281564	1			T1	18		T2	7		T4	752
valid_sources[0x2e]	281739	1			T1	23		T2	1		T4	681
valid_sources[0x2f]	299711	1			T1	17		T4	699		T5	10
valid_sources[0x30]	291785	1			T1	21		T2	7		T4	688
valid_sources[0x31]	256585	1			T1	19		T4	704		T5	1
valid_sources[0x32]	258450	1			T1	22		T2	1		T4	749
valid_sources[0x33]	269403	1			T1	24		T4	734		T5	3
valid_sources[0x34]	286446	1			T1	11		T2	7		T4	641
valid_sources[0x35]	258534	1			T1	25		T2	6		T4	725
valid_sources[0x36]	325790	1			T1	34		T4	634		T5	3
valid_sources[0x37]	255358	1			T1	7		T4	650		T9	31
valid_sources[0x38]	262699	1			T1	16		T2	21		T4	662
valid_sources[0x39]	284449	1			T1	15		T2	13		T4	687
valid_sources[0x3a]	288223	1			T1	25		T2	6		T4	737
valid_sources[0x3b]	321218	1			T1	40		T2	4		T4	671
valid_sources[0x3c]	255900	1			T1	30		T4	744		T5	6
valid_sources[0x3d]	269558	1			T1	17		T2	8		T4	678
valid_sources[0x3e]	262702	1			T1	16		T2	11		T4	725
valid_sources[0x3f]	291807	1			T1	30		T4	667		T9	41
valid_sources[0x40]	303608	1			T1	7		T2	2		T4	754
valid_sources[0x41]	271358	1			T1	16		T2	1		T4	754
valid_sources[0x42]	296708	1			T1	14		T4	699		T5	2
valid_sources[0x43]	307188	1			T1	12		T2	7		T4	727
valid_sources[0x44]	260441	1			T1	16		T2	4		T4	732
valid_sources[0x45]	255434	1			T1	19		T4	727		T5	5
valid_sources[0x46]	301810	1			T1	21		T2	17		T4	699
valid_sources[0x47]	255296	1			T1	14		T2	1		T4	699
valid_sources[0x48]	267602	1			T1	14		T2	5		T4	694
valid_sources[0x49]	277010	1			T1	12		T4	707		T9	34
valid_sources[0x4a]	288797	1			T1	24		T2	8		T4	677
valid_sources[0x4b]	277362	1			T1	16		T2	3		T4	682
valid_sources[0x4c]	263664	1			T1	32		T2	7		T4	669
valid_sources[0x4d]	273052	1			T1	23		T2	16		T4	711
valid_sources[0x4e]	252943	1			T1	27		T2	9		T4	693
valid_sources[0x4f]	250529	1			T1	11		T2	10		T4	708
valid_sources[0x50]	295425	1			T1	13		T2	11		T4	710
valid_sources[0x51]	276543	1			T1	27		T2	7		T4	691
valid_sources[0x52]	289562	1			T1	23		T4	733		T5	2
valid_sources[0x53]	303358	1			T1	19		T2	23		T4	703
valid_sources[0x54]	294029	1			T1	26		T2	11		T4	661
valid_sources[0x55]	284275	1			T1	22		T2	5		T4	698
valid_sources[0x56]	297386	1			T1	22		T4	738		T5	4
valid_sources[0x57]	291321	1			T1	19		T4	677		T5	3
valid_sources[0x58]	290130	1			T1	12		T4	696		T5	1
valid_sources[0x59]	267204	1			T1	24		T2	10		T4	725
valid_sources[0x5a]	254549	1			T1	8		T2	2		T4	693
valid_sources[0x5b]	326345	1			T1	14		T2	15		T4	722
valid_sources[0x5c]	332443	1			T1	31		T2	3		T4	674
valid_sources[0x5d]	258760	1			T1	18		T2	5		T4	688
valid_sources[0x5e]	299210	1			T1	18		T2	14		T4	656
valid_sources[0x5f]	264417	1			T1	10		T4	753		T9	29
valid_sources[0x60]	341434	1			T1	32		T4	788		T5	4
valid_sources[0x61]	257236	1			T1	12		T2	6		T4	699
valid_sources[0x62]	294887	1			T1	22		T2	3		T4	677
valid_sources[0x63]	293308	1			T1	30		T4	647		T5	1
valid_sources[0x64]	309548	1			T1	5		T2	8		T4	662
valid_sources[0x65]	307951	1			T1	21		T2	1		T4	649
valid_sources[0x66]	275115	1			T1	20		T2	3		T4	692
valid_sources[0x67]	325439	1			T1	20		T2	2		T4	725
valid_sources[0x68]	306949	1			T1	11		T2	15		T4	679
valid_sources[0x69]	305381	1			T1	26		T4	754		T5	1
valid_sources[0x6a]	265806	1			T1	16		T2	1		T4	673
valid_sources[0x6b]	259465	1			T1	20		T4	702		T5	1
valid_sources[0x6c]	272721	1			T1	17		T4	701		T5	2
valid_sources[0x6d]	323032	1			T1	11		T2	6		T4	725
valid_sources[0x6e]	290902	1			T1	10		T2	18		T4	659
valid_sources[0x6f]	261338	1			T1	16		T2	17		T4	682
valid_sources[0x70]	282245	1			T1	24		T4	729		T5	6
valid_sources[0x71]	272633	1			T1	20		T2	7		T4	647
valid_sources[0x72]	289152	1			T1	22		T2	8		T4	679
valid_sources[0x73]	305711	1			T1	9		T4	678		T5	5
valid_sources[0x74]	293942	1			T1	20		T4	745		T5	3
valid_sources[0x75]	277942	1			T1	16		T2	2		T4	601
valid_sources[0x76]	270602	1			T1	11		T2	5		T4	742
valid_sources[0x77]	251227	1			T1	21		T4	721		T9	33
valid_sources[0x78]	341530	1			T1	24		T2	2		T4	742
valid_sources[0x79]	251894	1			T1	32		T4	673		T5	4
valid_sources[0x7a]	263550	1			T1	16		T2	1		T4	679
valid_sources[0x7b]	288200	1			T1	7		T2	3		T4	683
valid_sources[0x7c]	266982	1			T1	26		T2	20		T4	666
valid_sources[0x7d]	297618	1			T1	19		T2	7		T4	725
valid_sources[0x7e]	268874	1			T1	17		T2	9		T4	793
valid_sources[0x7f]	262982	1			T1	33		T4	722		T5	7
valid_sources[0x80]	303461	1			T1	21		T2	1		T4	698

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29169480

1

T1

2010

T2

2

T4

81693

values[0x0]

all_enables

biggest_size

14684690

1

T1

994

T2

23

T4

40607

values[0x1]

all_enables

biggest_size

14678493

1

T1

935

T2

29

T4

40383

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

128572

1

T1

1

T4

1

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47786	1			T25	357		T6	31		T26	688
values[0x0]	56408	1			T1	1		T3	1		T4	2
values[0x1]	59974	1			T1	1		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

137018

1

T1

1

T2

1

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	520	1			T25	10		T26	11		T150	2
valid_sources[0x01]	806	1			T25	4		T51	1		T20	1
valid_sources[0x02]	709	1			T25	4		T27	3		T26	8
valid_sources[0x03]	637	1			T25	3		T26	10		T21	1
valid_sources[0x04]	652	1			T25	3		T26	9		T93	1
valid_sources[0x05]	768	1			T25	4		T65	1		T49	15
valid_sources[0x06]	522	1			T25	3		T26	8		T21	1
valid_sources[0x07]	665	1			T25	4		T44	1		T26	25
valid_sources[0x08]	850	1			T25	9		T26	7		T111	1
valid_sources[0x09]	1071	1			T25	6		T26	4		T21	1
valid_sources[0x0a]	467	1			T25	4		T20	1		T26	14
valid_sources[0x0b]	697	1			T25	6		T26	8		T16	1
valid_sources[0x0c]	597	1			T25	4		T51	1		T26	6
valid_sources[0x0d]	749	1			T25	2		T44	1		T26	9
valid_sources[0x0e]	575	1			T25	2		T27	1		T26	11
valid_sources[0x0f]	986	1			T25	8		T26	9		T111	1
valid_sources[0x10]	441	1			T25	3		T26	2		T21	1
valid_sources[0x11]	587	1			T25	6		T26	16		T151	1
valid_sources[0x12]	445	1			T25	4		T26	16		T151	1
valid_sources[0x13]	677	1			T25	6		T26	12		T94	1
valid_sources[0x14]	470	1			T25	3		T26	18		T8	2
valid_sources[0x15]	837	1			T25	3		T26	5		T16	2
valid_sources[0x16]	558	1			T25	4		T49	4		T26	11
valid_sources[0x17]	775	1			T25	4		T26	6		T21	1
valid_sources[0x18]	510	1			T25	6		T44	2		T26	15
valid_sources[0x19]	660	1			T12	2		T25	1		T26	16
valid_sources[0x1a]	674	1			T10	1		T25	5		T26	12
valid_sources[0x1b]	975	1			T25	6		T26	6		T21	1
valid_sources[0x1c]	622	1			T25	6		T44	1		T26	25
valid_sources[0x1d]	563	1			T25	5		T33	1		T26	3
valid_sources[0x1e]	630	1			T25	6		T26	8		T21	2
valid_sources[0x1f]	471	1			T3	5		T25	7		T26	8
valid_sources[0x20]	514	1			T25	4		T26	9		T30	7
valid_sources[0x21]	1261	1			T25	6		T26	12		T24	1
valid_sources[0x22]	772	1			T25	3		T26	2		T149	1
valid_sources[0x23]	424	1			T25	1		T26	3		T50	1
valid_sources[0x24]	597	1			T25	8		T26	8		T16	1
valid_sources[0x25]	651	1			T26	7		T112	5		T24	1
valid_sources[0x26]	854	1			T25	4		T26	2		T21	1
valid_sources[0x27]	552	1			T25	3		T26	11		T24	1
valid_sources[0x28]	622	1			T25	5		T65	1		T26	9
valid_sources[0x29]	826	1			T25	9		T26	4		T16	1
valid_sources[0x2a]	614	1			T25	5		T26	11		T21	2
valid_sources[0x2b]	579	1			T25	6		T26	35		T21	1
valid_sources[0x2c]	476	1			T25	5		T26	2		T152	1
valid_sources[0x2d]	539	1			T25	2		T26	8		T151	1
valid_sources[0x2e]	689	1			T25	2		T26	29		T58	15
valid_sources[0x2f]	456	1			T25	1		T26	11		T21	1
valid_sources[0x30]	731	1			T25	3		T26	8		T153	1
valid_sources[0x31]	688	1			T25	4		T26	7		T114	1
valid_sources[0x32]	484	1			T25	3		T28	1		T26	8
valid_sources[0x33]	806	1			T25	5		T64	4		T65	1
valid_sources[0x34]	775	1			T25	2		T20	1		T26	10
valid_sources[0x35]	543	1			T25	6		T26	21		T21	1
valid_sources[0x36]	606	1			T25	9		T26	4		T30	11
valid_sources[0x37]	736	1			T25	7		T26	7		T147	1
valid_sources[0x38]	560	1			T25	3		T26	10		T22	1
valid_sources[0x39]	750	1			T25	5		T26	7		T50	1
valid_sources[0x3a]	656	1			T25	8		T26	11		T154	2
valid_sources[0x3b]	818	1			T25	8		T26	6		T24	1
valid_sources[0x3c]	492	1			T25	4		T151	4		T50	2
valid_sources[0x3d]	555	1			T4	2		T25	2		T26	5
valid_sources[0x3e]	865	1			T25	5		T26	16		T24	2
valid_sources[0x3f]	473	1			T25	3		T71	3		T26	7
valid_sources[0x40]	744	1			T25	3		T49	1		T26	10
valid_sources[0x41]	781	1			T25	3		T26	9		T8	8
valid_sources[0x42]	626	1			T25	3		T26	17		T21	1
valid_sources[0x43]	685	1			T25	5		T26	23		T8	3
valid_sources[0x44]	612	1			T25	6		T26	12		T24	2
valid_sources[0x45]	516	1			T25	4		T26	10		T30	10
valid_sources[0x46]	603	1			T4	1		T25	5		T26	9
valid_sources[0x47]	460	1			T25	6		T44	1		T29	1
valid_sources[0x48]	1009	1			T25	2		T26	20		T155	1
valid_sources[0x49]	505	1			T25	9		T29	1		T49	2
valid_sources[0x4a]	590	1			T25	4		T26	9		T30	5
valid_sources[0x4b]	740	1			T25	4		T26	10		T156	1
valid_sources[0x4c]	497	1			T25	7		T26	8		T22	1
valid_sources[0x4d]	791	1			T25	4		T20	1		T26	17
valid_sources[0x4e]	947	1			T5	1		T25	1		T26	17
valid_sources[0x4f]	597	1			T25	2		T44	1		T19	2
valid_sources[0x50]	831	1			T25	12		T27	1		T26	1
valid_sources[0x51]	773	1			T25	8		T157	1		T26	20
valid_sources[0x52]	861	1			T25	2		T26	5		T8	4
valid_sources[0x53]	618	1			T25	4		T26	20		T21	1
valid_sources[0x54]	695	1			T25	1		T26	10		T8	2
valid_sources[0x55]	607	1			T25	4		T26	18		T30	21
valid_sources[0x56]	653	1			T25	11		T26	23		T16	1
valid_sources[0x57]	477	1			T25	5		T48	23		T26	1
valid_sources[0x58]	549	1			T25	6		T27	1		T26	11
valid_sources[0x59]	501	1			T10	1		T25	6		T44	3
valid_sources[0x5a]	827	1			T10	1		T25	6		T26	3
valid_sources[0x5b]	609	1			T25	14		T26	14		T54	1
valid_sources[0x5c]	742	1			T5	1		T25	3		T20	1
valid_sources[0x5d]	608	1			T25	4		T28	1		T26	14
valid_sources[0x5e]	724	1			T25	6		T26	4		T158	1
valid_sources[0x5f]	617	1			T25	7		T26	9		T37	2
valid_sources[0x60]	659	1			T25	6		T26	15		T94	1
valid_sources[0x61]	569	1			T25	6		T26	7		T30	8
valid_sources[0x62]	557	1			T25	7		T26	5		T21	1
valid_sources[0x63]	676	1			T25	6		T46	1		T26	8
valid_sources[0x64]	608	1			T25	3		T26	13		T159	19
valid_sources[0x65]	582	1			T25	8		T26	3		T113	2
valid_sources[0x66]	457	1			T10	1		T25	3		T47	3
valid_sources[0x67]	485	1			T25	5		T26	9		T24	2
valid_sources[0x68]	475	1			T25	6		T26	9		T50	3
valid_sources[0x69]	696	1			T25	13		T26	15		T158	1
valid_sources[0x6a]	627	1			T25	3		T26	8		T30	8
valid_sources[0x6b]	683	1			T25	7		T26	14		T24	3
valid_sources[0x6c]	770	1			T25	7		T26	5		T21	2
valid_sources[0x6d]	490	1			T25	5		T26	9		T21	1
valid_sources[0x6e]	550	1			T25	3		T26	16		T22	5
valid_sources[0x6f]	530	1			T25	2		T26	4		T21	1
valid_sources[0x70]	687	1			T25	8		T26	13		T30	7
valid_sources[0x71]	491	1			T25	2		T26	8		T160	2
valid_sources[0x72]	575	1			T25	5		T26	9		T50	1
valid_sources[0x73]	559	1			T25	12		T26	26		T21	1
valid_sources[0x74]	613	1			T25	8		T26	7		T30	4
valid_sources[0x75]	469	1			T25	9		T26	16		T149	3
valid_sources[0x76]	476	1			T25	2		T26	3		T21	1
valid_sources[0x77]	499	1			T25	2		T26	19		T21	1
valid_sources[0x78]	578	1			T25	4		T26	24		T21	2
valid_sources[0x79]	581	1			T25	5		T26	13		T161	1
valid_sources[0x7a]	466	1			T25	3		T26	13		T24	1
valid_sources[0x7b]	465	1			T25	5		T26	11		T162	1
valid_sources[0x7c]	498	1			T25	8		T26	12		T8	1
valid_sources[0x7d]	533	1			T25	9		T26	15		T154	1
valid_sources[0x7e]	702	1			T25	5		T26	14		T30	5
valid_sources[0x7f]	453	1			T25	7		T157	1		T27	2
valid_sources[0x80]	877	1			T25	5		T26	16		T151	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35174

1

T25

302

T6

12

T26

619

values[0x0]

all_enables

biggest_size

47825

1

T10

2

T13

1

T25

420

values[0x1]

all_enables

biggest_size

45573

1

T1

1

T4

1

T13

1