Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13748532

1

T1

850

T2

932

T4

16349

full_word

53491258

1

T1

3939

T2

54

T4

162683

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67239500	1			T1	4789		T2	986		T4	179032
auto[TlIntgErrCmd]	99	1			T61	10		T62	3		T63	3
auto[TlIntgErrData]	99	1			T61	1		T62	5		T63	5
auto[TlIntgErrBoth]	92	1			T61	9		T62	2		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30791423

1

T1

2415

T2

364

T4

89837

auto[1]

36448367

1

T1

2374

T2

622

T4

89195

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6578451	1			T1	405		T2	362		T4	8144
auto[TlIntgErrNone]	partial	auto[1]	7169822	1			T1	445		T2	570		T4	8205
auto[TlIntgErrNone]	full_word	auto[0]	24212828	1			T1	2010		T2	2		T4	81693
auto[TlIntgErrNone]	full_word	auto[1]	29278399	1			T1	1929		T2	52		T4	80990
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T61	3		T62	3		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T61	6		T63	1		T134	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T138	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T61	1		T134	2		T138	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T61	1		T62	1		T63	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T62	3		T63	3		T134	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T62	1		T138	1		T139	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T63	1		T139	1		T142	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T61	3		T63	1		T134	3
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T61	5		T62	1		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T61	1		T62	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T134	1		T138	1		T136	1