Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	775432	1			T44	5965		T28	47		T29	5
auto[1]	9902959	1			T1	2414		T4	74721		T5	432
auto[2]	648889	1			T44	3901		T28	39		T29	5
auto[3]	9782490	1			T1	2373		T4	74175		T5	375

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13766786	1			T1	3195		T4	124073		T5	807
auto[1]	2000804	1			T1	743		T4	11843		T10	21522
auto[2]	2023439	1			T1	666		T4	11840		T10	21420
auto[3]	3318741	1			T1	183		T4	1140		T10	2010

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8231106

1

T1

4784

T5

806

T11

9252

auto[1]

12878664

1

T1

3

T4

148896

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	361241	1			T44	4891		T29	4		T45	1698
auto[0]	auto[0]	auto[1]	38316	1			T44	497		T28	1		T45	174
auto[0]	auto[0]	auto[2]	38532	1			T44	517		T29	1		T45	167
auto[0]	auto[0]	auto[3]	13490	1			T44	56		T28	46		T45	19
auto[0]	auto[1]	auto[0]	3034336	1			T1	1627		T5	432		T11	3866
auto[0]	auto[1]	auto[1]	322237	1			T1	382		T11	326		T13	31
auto[0]	auto[1]	auto[2]	302783	1			T1	303		T11	398		T12	1
auto[0]	auto[1]	auto[3]	62824	1			T1	100		T11	35		T13	7
auto[0]	auto[2]	auto[0]	314033	1			T44	2969		T29	5		T45	1554
auto[0]	auto[2]	auto[1]	33206	1			T44	316		T45	160		T147	285
auto[0]	auto[2]	auto[2]	32642	1			T44	546		T28	2		T45	150
auto[0]	auto[2]	auto[3]	10566	1			T44	69		T28	36		T45	16
auto[0]	auto[3]	auto[0]	2988949	1			T1	1566		T5	374		T11	3934
auto[0]	auto[3]	auto[1]	297919	1			T1	361		T11	349		T12	2
auto[0]	auto[3]	auto[2]	318511	1			T1	362		T11	312		T12	2
auto[0]	auto[3]	auto[3]	61521	1			T1	83		T11	32		T13	7
auto[1]	auto[0]	auto[0]	11231	1			T44	4		T45	1		T147	4
auto[1]	auto[0]	auto[1]	48092	1			T148	3		T149	4		T21	3
auto[1]	auto[0]	auto[2]	48132	1			T148	2		T21	1		T8	1
auto[1]	auto[0]	auto[3]	216398	1			T41	2967		T132	1		T127	7021
auto[1]	auto[1]	auto[0]	3527208	1			T1	1		T4	62350		T10	113955
auto[1]	auto[1]	auto[1]	630466	1			T4	5564		T10	10268		T13	1
auto[1]	auto[1]	auto[2]	620785	1			T1	1		T4	6238		T10	11344
auto[1]	auto[1]	auto[3]	1402320	1			T4	569		T10	1014		T44	1
auto[1]	auto[2]	auto[0]	6757	1			T44	1		T45	3		T147	1
auto[1]	auto[2]	auto[1]	29380	1			T45	1		T148	1		T149	2
auto[1]	auto[2]	auto[2]	40474	1			T148	2		T21	1		T8	3
auto[1]	auto[2]	auto[3]	181831	1			T28	1		T41	2498		T127	7694
auto[1]	auto[3]	auto[0]	3523031	1			T1	1		T4	61723		T5	1
auto[1]	auto[3]	auto[1]	601188	1			T4	6279		T10	11254		T47	4
auto[1]	auto[3]	auto[2]	621580	1			T4	5602		T10	10076		T11	1
auto[1]	auto[3]	auto[3]	1369791	1			T4	571		T10	996		T71	870