Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	324898448	194855	0	0
ctrl_regwen_rd_A	324898448	2788	0	0
exec_rd_A	324898448	2753	0	0
exec_regwen_rd_A	324898448	2630	0	0
readback_rd_A	324898448	1485	0	0
readback_regwen_rd_A	324898448	1339	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324898448	194855	0	0
T19	51622	0	0	0
T25	51985	2595	0	0
T26	0	4864	0	0
T28	15582	0	0	0
T29	19537	0	0	0
T30	0	4158	0	0
T32	2371	0	0	0
T44	135389	0	0	0
T46	24192	0	0	0
T47	177829	0	0	0
T58	0	5090	0	0
T70	12045	0	0	0
T71	298812	0	0	0
T72	0	4218	0	0
T73	0	3096	0	0
T74	0	2819	0	0
T75	0	6225	0	0
T76	0	5223	0	0
T77	0	9269	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324898448	2788	0	0
T53	0	553	0	0
T58	203008	394	0	0
T59	6610	0	0	0
T66	0	29	0	0
T116	0	102	0	0
T117	0	103	0	0
T118	0	233	0	0
T119	0	66	0	0
T120	0	172	0	0
T121	0	19	0	0
T122	0	48	0	0
T123	283654	0	0	0
T124	123639	0	0	0
T125	721315	0	0	0
T126	996	0	0	0
T127	113890	0	0	0
T128	8969	0	0	0
T129	1455	0	0	0
T130	13184	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324898448	2753	0	0
T53	0	524	0	0
T58	203008	376	0	0
T59	6610	0	0	0
T66	0	43	0	0
T116	0	65	0	0
T117	0	114	0	0
T118	0	168	0	0
T119	0	74	0	0
T120	0	229	0	0
T121	0	10	0	0
T122	0	52	0	0
T123	283654	0	0	0
T124	123639	0	0	0
T125	721315	0	0	0
T126	996	0	0	0
T127	113890	0	0	0
T128	8969	0	0	0
T129	1455	0	0	0
T130	13184	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324898448	2630	0	0
T53	0	474	0	0
T58	203008	427	0	0
T59	6610	0	0	0
T66	0	21	0	0
T116	0	84	0	0
T117	0	166	0	0
T118	0	204	0	0
T119	0	46	0	0
T120	0	126	0	0
T121	0	45	0	0
T122	0	29	0	0
T123	283654	0	0	0
T124	123639	0	0	0
T125	721315	0	0	0
T126	996	0	0	0
T127	113890	0	0	0
T128	8969	0	0	0
T129	1455	0	0	0
T130	13184	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324898448	1485	0	0
T53	0	428	0	0
T58	203008	361	0	0
T59	6610	0	0	0
T116	0	79	0	0
T117	0	62	0	0
T118	0	200	0	0
T119	0	37	0	0
T120	0	208	0	0
T121	0	29	0	0
T122	0	50	0	0
T123	283654	0	0	0
T124	123639	0	0	0
T125	721315	0	0	0
T126	996	0	0	0
T127	113890	0	0	0
T128	8969	0	0	0
T129	1455	0	0	0
T130	13184	0	0	0
T131	0	4	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324898448	1339	0	0
T53	0	420	0	0
T58	203008	257	0	0
T59	6610	0	0	0
T116	0	88	0	0
T117	0	110	0	0
T118	0	139	0	0
T119	0	39	0	0
T120	0	153	0	0
T121	0	19	0	0
T122	0	85	0	0
T123	283654	0	0	0
T124	123639	0	0	0
T125	721315	0	0	0
T126	996	0	0	0
T127	113890	0	0	0
T128	8969	0	0	0
T129	1455	0	0	0
T130	13184	0	0	0
T131	0	5	0	0