SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1784 | 1784 | 0 | 0 |
OutputsKnown_A | 647445960 | 647213570 | 0 | 0 |
gen_flops.OutputDelay_A | 323722980 | 323593342 | 0 | 2676 |
gen_no_flops.OutputDelay_A | 323722980 | 323606785 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1784 | 1784 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
T12 | 2 | 2 | 0 | 0 |
T13 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 647445960 | 647213570 | 0 | 0 |
T1 | 17226 | 17110 | 0 | 0 |
T2 | 18424 | 18274 | 0 | 0 |
T3 | 2170 | 2000 | 0 | 0 |
T4 | 429406 | 429288 | 0 | 0 |
T5 | 7474 | 7354 | 0 | 0 |
T9 | 41346 | 41194 | 0 | 0 |
T10 | 792028 | 791906 | 0 | 0 |
T11 | 26268 | 26154 | 0 | 0 |
T12 | 31150 | 30988 | 0 | 0 |
T13 | 6984 | 6836 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323722980 | 323593342 | 0 | 2676 |
T1 | 8613 | 8552 | 0 | 3 |
T2 | 9212 | 9134 | 0 | 3 |
T3 | 1085 | 997 | 0 | 3 |
T4 | 214703 | 214641 | 0 | 3 |
T5 | 3737 | 3674 | 0 | 3 |
T9 | 20673 | 20594 | 0 | 3 |
T10 | 396014 | 395950 | 0 | 3 |
T11 | 13134 | 13074 | 0 | 3 |
T12 | 15575 | 15491 | 0 | 3 |
T13 | 3492 | 3415 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323722980 | 323606785 | 0 | 0 |
T1 | 8613 | 8555 | 0 | 0 |
T2 | 9212 | 9137 | 0 | 0 |
T3 | 1085 | 1000 | 0 | 0 |
T4 | 214703 | 214644 | 0 | 0 |
T5 | 3737 | 3677 | 0 | 0 |
T9 | 20673 | 20597 | 0 | 0 |
T10 | 396014 | 395953 | 0 | 0 |
T11 | 13134 | 13077 | 0 | 0 |
T12 | 15575 | 15494 | 0 | 0 |
T13 | 3492 | 3418 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 892 | 892 | 0 | 0 |
OutputsKnown_A | 323722980 | 323606785 | 0 | 0 |
gen_flops.OutputDelay_A | 323722980 | 323593342 | 0 | 2676 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 892 | 892 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323722980 | 323606785 | 0 | 0 |
T1 | 8613 | 8555 | 0 | 0 |
T2 | 9212 | 9137 | 0 | 0 |
T3 | 1085 | 1000 | 0 | 0 |
T4 | 214703 | 214644 | 0 | 0 |
T5 | 3737 | 3677 | 0 | 0 |
T9 | 20673 | 20597 | 0 | 0 |
T10 | 396014 | 395953 | 0 | 0 |
T11 | 13134 | 13077 | 0 | 0 |
T12 | 15575 | 15494 | 0 | 0 |
T13 | 3492 | 3418 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323722980 | 323593342 | 0 | 2676 |
T1 | 8613 | 8552 | 0 | 3 |
T2 | 9212 | 9134 | 0 | 3 |
T3 | 1085 | 997 | 0 | 3 |
T4 | 214703 | 214641 | 0 | 3 |
T5 | 3737 | 3674 | 0 | 3 |
T9 | 20673 | 20594 | 0 | 3 |
T10 | 396014 | 395950 | 0 | 3 |
T11 | 13134 | 13074 | 0 | 3 |
T12 | 15575 | 15491 | 0 | 3 |
T13 | 3492 | 3415 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 892 | 892 | 0 | 0 |
OutputsKnown_A | 323722980 | 323606785 | 0 | 0 |
gen_no_flops.OutputDelay_A | 323722980 | 323606785 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 892 | 892 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323722980 | 323606785 | 0 | 0 |
T1 | 8613 | 8555 | 0 | 0 |
T2 | 9212 | 9137 | 0 | 0 |
T3 | 1085 | 1000 | 0 | 0 |
T4 | 214703 | 214644 | 0 | 0 |
T5 | 3737 | 3677 | 0 | 0 |
T9 | 20673 | 20597 | 0 | 0 |
T10 | 396014 | 395953 | 0 | 0 |
T11 | 13134 | 13077 | 0 | 0 |
T12 | 15575 | 15494 | 0 | 0 |
T13 | 3492 | 3418 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323722980 | 323606785 | 0 | 0 |
T1 | 8613 | 8555 | 0 | 0 |
T2 | 9212 | 9137 | 0 | 0 |
T3 | 1085 | 1000 | 0 | 0 |
T4 | 214703 | 214644 | 0 | 0 |
T5 | 3737 | 3677 | 0 | 0 |
T9 | 20673 | 20597 | 0 | 0 |
T10 | 396014 | 395953 | 0 | 0 |
T11 | 13134 | 13077 | 0 | 0 |
T12 | 15575 | 15494 | 0 | 0 |
T13 | 3492 | 3418 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |