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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T802 /workspace/coverage/default/23.sram_ctrl_max_throughput.3536736535 Jul 11 05:14:55 PM PDT 24 Jul 11 05:16:30 PM PDT 24 474969679 ps
T803 /workspace/coverage/default/4.sram_ctrl_mem_walk.2746915333 Jul 11 05:12:15 PM PDT 24 Jul 11 05:12:20 PM PDT 24 448398929 ps
T804 /workspace/coverage/default/43.sram_ctrl_mem_walk.3093539216 Jul 11 05:17:29 PM PDT 24 Jul 11 05:17:41 PM PDT 24 461526368 ps
T805 /workspace/coverage/default/3.sram_ctrl_lc_escalation.2620815441 Jul 11 04:59:12 PM PDT 24 Jul 11 04:59:15 PM PDT 24 182180470 ps
T806 /workspace/coverage/default/38.sram_ctrl_executable.1548314520 Jul 11 05:17:39 PM PDT 24 Jul 11 05:18:10 PM PDT 24 1766480767 ps
T807 /workspace/coverage/default/15.sram_ctrl_executable.1360438281 Jul 11 05:14:02 PM PDT 24 Jul 11 05:18:11 PM PDT 24 23501534619 ps
T808 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2281713800 Jul 11 05:17:47 PM PDT 24 Jul 11 05:20:19 PM PDT 24 713823499 ps
T809 /workspace/coverage/default/45.sram_ctrl_mem_walk.3815718658 Jul 11 05:17:46 PM PDT 24 Jul 11 05:17:54 PM PDT 24 347738881 ps
T810 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2395652327 Jul 11 04:58:56 PM PDT 24 Jul 11 05:04:43 PM PDT 24 11374529356 ps
T811 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3545115570 Jul 11 05:13:51 PM PDT 24 Jul 11 05:13:55 PM PDT 24 405904241 ps
T812 /workspace/coverage/default/46.sram_ctrl_mem_walk.882470648 Jul 11 05:18:01 PM PDT 24 Jul 11 05:18:13 PM PDT 24 918401216 ps
T813 /workspace/coverage/default/46.sram_ctrl_partial_access.3422252807 Jul 11 05:18:02 PM PDT 24 Jul 11 05:19:42 PM PDT 24 746232873 ps
T814 /workspace/coverage/default/36.sram_ctrl_partial_access.551792597 Jul 11 05:17:17 PM PDT 24 Jul 11 05:17:46 PM PDT 24 1048738838 ps
T815 /workspace/coverage/default/23.sram_ctrl_smoke.3608750648 Jul 11 05:15:04 PM PDT 24 Jul 11 05:17:37 PM PDT 24 508935154 ps
T816 /workspace/coverage/default/3.sram_ctrl_max_throughput.577281311 Jul 11 04:59:10 PM PDT 24 Jul 11 04:59:16 PM PDT 24 132628562 ps
T817 /workspace/coverage/default/42.sram_ctrl_executable.3991207917 Jul 11 05:17:42 PM PDT 24 Jul 11 05:23:06 PM PDT 24 29810437596 ps
T818 /workspace/coverage/default/32.sram_ctrl_mem_walk.3780728546 Jul 11 05:16:46 PM PDT 24 Jul 11 05:16:58 PM PDT 24 354503867 ps
T819 /workspace/coverage/default/22.sram_ctrl_smoke.2282355499 Jul 11 05:15:04 PM PDT 24 Jul 11 05:15:13 PM PDT 24 654813968 ps
T820 /workspace/coverage/default/5.sram_ctrl_partial_access.3928224449 Jul 11 05:12:27 PM PDT 24 Jul 11 05:12:48 PM PDT 24 4132451577 ps
T821 /workspace/coverage/default/10.sram_ctrl_partial_access.2952560545 Jul 11 05:13:28 PM PDT 24 Jul 11 05:13:57 PM PDT 24 1425794703 ps
T822 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.874048909 Jul 11 05:16:55 PM PDT 24 Jul 11 05:22:03 PM PDT 24 6188886800 ps
T823 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1068449282 Jul 11 05:17:20 PM PDT 24 Jul 11 05:19:02 PM PDT 24 2142628043 ps
T824 /workspace/coverage/default/9.sram_ctrl_mem_walk.3677870350 Jul 11 05:13:11 PM PDT 24 Jul 11 05:13:18 PM PDT 24 240074429 ps
T825 /workspace/coverage/default/46.sram_ctrl_max_throughput.3461214535 Jul 11 05:18:02 PM PDT 24 Jul 11 05:18:18 PM PDT 24 75655175 ps
T826 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3471350775 Jul 11 05:13:45 PM PDT 24 Jul 11 05:14:50 PM PDT 24 294805030 ps
T827 /workspace/coverage/default/20.sram_ctrl_alert_test.2400529435 Jul 11 05:14:50 PM PDT 24 Jul 11 05:14:52 PM PDT 24 14788920 ps
T828 /workspace/coverage/default/28.sram_ctrl_mem_walk.1965592462 Jul 11 05:16:02 PM PDT 24 Jul 11 05:16:10 PM PDT 24 935942978 ps
T829 /workspace/coverage/default/28.sram_ctrl_max_throughput.1378759319 Jul 11 05:15:50 PM PDT 24 Jul 11 05:17:15 PM PDT 24 121810860 ps
T830 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3961079020 Jul 11 05:17:12 PM PDT 24 Jul 11 05:24:41 PM PDT 24 78605111893 ps
T831 /workspace/coverage/default/37.sram_ctrl_multiple_keys.36219077 Jul 11 05:17:29 PM PDT 24 Jul 11 05:30:47 PM PDT 24 3109601062 ps
T832 /workspace/coverage/default/34.sram_ctrl_max_throughput.1198645301 Jul 11 05:16:53 PM PDT 24 Jul 11 05:17:49 PM PDT 24 188365757 ps
T833 /workspace/coverage/default/24.sram_ctrl_partial_access.378928066 Jul 11 05:14:55 PM PDT 24 Jul 11 05:17:57 PM PDT 24 1715789164 ps
T834 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2083457322 Jul 11 05:15:06 PM PDT 24 Jul 11 05:17:12 PM PDT 24 4297633707 ps
T835 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.37157064 Jul 11 05:14:56 PM PDT 24 Jul 11 05:15:22 PM PDT 24 94346330 ps
T836 /workspace/coverage/default/37.sram_ctrl_bijection.2756812008 Jul 11 05:17:30 PM PDT 24 Jul 11 05:18:45 PM PDT 24 1058049798 ps
T837 /workspace/coverage/default/2.sram_ctrl_max_throughput.1771411247 Jul 11 04:59:07 PM PDT 24 Jul 11 05:00:53 PM PDT 24 608891094 ps
T838 /workspace/coverage/default/28.sram_ctrl_multiple_keys.1068645328 Jul 11 05:15:52 PM PDT 24 Jul 11 05:25:38 PM PDT 24 8840548583 ps
T839 /workspace/coverage/default/17.sram_ctrl_multiple_keys.2157349591 Jul 11 05:14:17 PM PDT 24 Jul 11 05:27:45 PM PDT 24 38970135556 ps
T840 /workspace/coverage/default/24.sram_ctrl_alert_test.756588643 Jul 11 05:15:04 PM PDT 24 Jul 11 05:15:07 PM PDT 24 12387537 ps
T841 /workspace/coverage/default/33.sram_ctrl_alert_test.3080636752 Jul 11 05:16:45 PM PDT 24 Jul 11 05:16:47 PM PDT 24 24175545 ps
T842 /workspace/coverage/default/48.sram_ctrl_smoke.3833128372 Jul 11 05:17:54 PM PDT 24 Jul 11 05:19:09 PM PDT 24 1136501243 ps
T843 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1221907648 Jul 11 05:13:18 PM PDT 24 Jul 11 05:13:22 PM PDT 24 427258729 ps
T844 /workspace/coverage/default/21.sram_ctrl_executable.2017317905 Jul 11 05:14:50 PM PDT 24 Jul 11 05:15:57 PM PDT 24 2804188762 ps
T845 /workspace/coverage/default/22.sram_ctrl_max_throughput.3467442684 Jul 11 05:15:05 PM PDT 24 Jul 11 05:15:52 PM PDT 24 95355828 ps
T846 /workspace/coverage/default/37.sram_ctrl_executable.4218720082 Jul 11 05:16:57 PM PDT 24 Jul 11 05:29:18 PM PDT 24 71063184513 ps
T847 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3331286287 Jul 11 05:15:05 PM PDT 24 Jul 11 05:20:37 PM PDT 24 19458146455 ps
T848 /workspace/coverage/default/1.sram_ctrl_smoke.2208661728 Jul 11 04:58:42 PM PDT 24 Jul 11 05:00:09 PM PDT 24 642616884 ps
T849 /workspace/coverage/default/19.sram_ctrl_smoke.244190376 Jul 11 05:14:27 PM PDT 24 Jul 11 05:16:23 PM PDT 24 666611859 ps
T850 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1454974573 Jul 11 05:14:38 PM PDT 24 Jul 11 05:15:44 PM PDT 24 121740193 ps
T851 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2811527951 Jul 11 05:16:28 PM PDT 24 Jul 11 05:21:36 PM PDT 24 4314895632 ps
T852 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2780220015 Jul 11 05:17:46 PM PDT 24 Jul 11 05:24:09 PM PDT 24 53468797764 ps
T853 /workspace/coverage/default/40.sram_ctrl_ram_cfg.716633850 Jul 11 05:17:51 PM PDT 24 Jul 11 05:17:54 PM PDT 24 282938071 ps
T854 /workspace/coverage/default/32.sram_ctrl_bijection.2725959237 Jul 11 05:17:08 PM PDT 24 Jul 11 05:18:24 PM PDT 24 1116289961 ps
T855 /workspace/coverage/default/48.sram_ctrl_partial_access.1070811403 Jul 11 05:17:54 PM PDT 24 Jul 11 05:18:48 PM PDT 24 421888594 ps
T856 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3590498344 Jul 11 05:13:40 PM PDT 24 Jul 11 05:13:50 PM PDT 24 726209623 ps
T857 /workspace/coverage/default/35.sram_ctrl_partial_access.1086893228 Jul 11 05:16:59 PM PDT 24 Jul 11 05:17:25 PM PDT 24 593417119 ps
T858 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2854881278 Jul 11 05:12:13 PM PDT 24 Jul 11 05:12:31 PM PDT 24 144356163 ps
T119 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1034258623 Jul 11 05:14:34 PM PDT 24 Jul 11 05:14:43 PM PDT 24 233768548 ps
T859 /workspace/coverage/default/19.sram_ctrl_mem_walk.69571083 Jul 11 05:14:39 PM PDT 24 Jul 11 05:14:44 PM PDT 24 191743889 ps
T860 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.949616429 Jul 11 05:15:12 PM PDT 24 Jul 11 05:20:12 PM PDT 24 3080586935 ps
T861 /workspace/coverage/default/3.sram_ctrl_bijection.2002566803 Jul 11 04:58:55 PM PDT 24 Jul 11 04:59:18 PM PDT 24 4199255574 ps
T862 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2496357006 Jul 11 05:14:19 PM PDT 24 Jul 11 05:20:57 PM PDT 24 1271427654 ps
T863 /workspace/coverage/default/6.sram_ctrl_bijection.1904622083 Jul 11 05:12:30 PM PDT 24 Jul 11 05:13:00 PM PDT 24 2870667714 ps
T864 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.4047062477 Jul 11 05:18:36 PM PDT 24 Jul 11 05:29:20 PM PDT 24 11493178523 ps
T865 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.496517626 Jul 11 04:58:56 PM PDT 24 Jul 11 05:00:46 PM PDT 24 159946320 ps
T866 /workspace/coverage/default/30.sram_ctrl_executable.3476882222 Jul 11 05:16:36 PM PDT 24 Jul 11 05:23:48 PM PDT 24 33776095153 ps
T867 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1724401961 Jul 11 05:14:21 PM PDT 24 Jul 11 05:14:46 PM PDT 24 338804838 ps
T868 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.758512369 Jul 11 05:16:24 PM PDT 24 Jul 11 05:16:41 PM PDT 24 152481436 ps
T869 /workspace/coverage/default/20.sram_ctrl_max_throughput.2834928876 Jul 11 05:14:44 PM PDT 24 Jul 11 05:17:03 PM PDT 24 137653410 ps
T870 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1778464134 Jul 11 05:14:06 PM PDT 24 Jul 11 05:20:22 PM PDT 24 14195637957 ps
T871 /workspace/coverage/default/45.sram_ctrl_executable.3794013995 Jul 11 05:17:47 PM PDT 24 Jul 11 05:34:51 PM PDT 24 56082479574 ps
T872 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2326091925 Jul 11 05:17:20 PM PDT 24 Jul 11 05:21:45 PM PDT 24 2772829310 ps
T873 /workspace/coverage/default/11.sram_ctrl_alert_test.4070165857 Jul 11 05:13:32 PM PDT 24 Jul 11 05:13:34 PM PDT 24 15735451 ps
T874 /workspace/coverage/default/38.sram_ctrl_smoke.2829942056 Jul 11 05:17:03 PM PDT 24 Jul 11 05:17:58 PM PDT 24 123633470 ps
T875 /workspace/coverage/default/37.sram_ctrl_ram_cfg.4160235148 Jul 11 05:17:18 PM PDT 24 Jul 11 05:17:19 PM PDT 24 48795011 ps
T876 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1428643138 Jul 11 05:17:52 PM PDT 24 Jul 11 05:18:02 PM PDT 24 191768043 ps
T877 /workspace/coverage/default/14.sram_ctrl_alert_test.2316745539 Jul 11 05:14:01 PM PDT 24 Jul 11 05:14:03 PM PDT 24 21614622 ps
T878 /workspace/coverage/default/8.sram_ctrl_partial_access.1804983874 Jul 11 05:13:13 PM PDT 24 Jul 11 05:13:53 PM PDT 24 164084041 ps
T879 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3541829981 Jul 11 05:14:54 PM PDT 24 Jul 11 05:15:00 PM PDT 24 585034559 ps
T880 /workspace/coverage/default/1.sram_ctrl_stress_all.2237658986 Jul 11 04:58:55 PM PDT 24 Jul 11 05:09:52 PM PDT 24 9004800477 ps
T881 /workspace/coverage/default/12.sram_ctrl_mem_walk.3619543277 Jul 11 05:13:53 PM PDT 24 Jul 11 05:14:07 PM PDT 24 3841751379 ps
T882 /workspace/coverage/default/32.sram_ctrl_max_throughput.1301793776 Jul 11 05:16:46 PM PDT 24 Jul 11 05:19:02 PM PDT 24 298586642 ps
T883 /workspace/coverage/default/49.sram_ctrl_smoke.3849364490 Jul 11 05:18:12 PM PDT 24 Jul 11 05:18:58 PM PDT 24 1695285072 ps
T884 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.137707646 Jul 11 05:13:53 PM PDT 24 Jul 11 05:19:02 PM PDT 24 12496058551 ps
T885 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1537020247 Jul 11 05:12:55 PM PDT 24 Jul 11 05:14:25 PM PDT 24 2124865812 ps
T886 /workspace/coverage/default/31.sram_ctrl_stress_all.612019017 Jul 11 05:16:35 PM PDT 24 Jul 11 06:03:12 PM PDT 24 22566550646 ps
T887 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2497449316 Jul 11 05:17:52 PM PDT 24 Jul 11 05:20:33 PM PDT 24 2124826344 ps
T888 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1415859831 Jul 11 05:15:14 PM PDT 24 Jul 11 05:15:16 PM PDT 24 57588687 ps
T889 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2365438508 Jul 11 05:14:23 PM PDT 24 Jul 11 05:15:06 PM PDT 24 1659240992 ps
T890 /workspace/coverage/default/24.sram_ctrl_lc_escalation.3107778525 Jul 11 05:14:53 PM PDT 24 Jul 11 05:14:56 PM PDT 24 168034300 ps
T891 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.209406812 Jul 11 05:16:40 PM PDT 24 Jul 11 05:23:45 PM PDT 24 21441513289 ps
T892 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.210279128 Jul 11 05:17:45 PM PDT 24 Jul 11 05:21:59 PM PDT 24 12389633686 ps
T893 /workspace/coverage/default/40.sram_ctrl_alert_test.514412160 Jul 11 05:17:48 PM PDT 24 Jul 11 05:17:51 PM PDT 24 23485092 ps
T894 /workspace/coverage/default/29.sram_ctrl_executable.1191746927 Jul 11 05:16:05 PM PDT 24 Jul 11 05:27:35 PM PDT 24 54837547282 ps
T895 /workspace/coverage/default/26.sram_ctrl_alert_test.1673377618 Jul 11 05:15:21 PM PDT 24 Jul 11 05:15:22 PM PDT 24 12969257 ps
T896 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1088620793 Jul 11 05:14:50 PM PDT 24 Jul 11 05:19:12 PM PDT 24 3666173066 ps
T897 /workspace/coverage/default/0.sram_ctrl_bijection.1116177637 Jul 11 04:58:48 PM PDT 24 Jul 11 04:59:26 PM PDT 24 2023268198 ps
T898 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2160040224 Jul 11 05:13:09 PM PDT 24 Jul 11 05:13:12 PM PDT 24 40681555 ps
T52 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1730629733 Jul 11 05:17:26 PM PDT 24 Jul 11 05:17:48 PM PDT 24 7525981206 ps
T899 /workspace/coverage/default/17.sram_ctrl_regwen.2529324535 Jul 11 05:15:36 PM PDT 24 Jul 11 05:24:11 PM PDT 24 5779132422 ps
T53 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1062126244 Jul 11 05:17:32 PM PDT 24 Jul 11 05:19:16 PM PDT 24 20508412905 ps
T900 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3351683850 Jul 11 05:16:34 PM PDT 24 Jul 11 05:17:57 PM PDT 24 134874215 ps
T901 /workspace/coverage/default/48.sram_ctrl_mem_walk.1581207771 Jul 11 05:18:12 PM PDT 24 Jul 11 05:18:20 PM PDT 24 332957221 ps
T902 /workspace/coverage/default/9.sram_ctrl_bijection.2785981338 Jul 11 05:13:13 PM PDT 24 Jul 11 05:13:50 PM PDT 24 522179697 ps
T903 /workspace/coverage/default/20.sram_ctrl_ram_cfg.2406242017 Jul 11 05:14:40 PM PDT 24 Jul 11 05:14:42 PM PDT 24 56758397 ps
T904 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1122124257 Jul 11 05:17:38 PM PDT 24 Jul 11 05:20:11 PM PDT 24 5986753764 ps
T905 /workspace/coverage/default/1.sram_ctrl_lc_escalation.2263599679 Jul 11 04:58:58 PM PDT 24 Jul 11 04:59:08 PM PDT 24 9801319791 ps
T906 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.392538695 Jul 11 05:16:28 PM PDT 24 Jul 11 05:21:15 PM PDT 24 5802142001 ps
T907 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.509758451 Jul 11 05:17:39 PM PDT 24 Jul 11 05:22:15 PM PDT 24 11444135690 ps
T908 /workspace/coverage/default/13.sram_ctrl_multiple_keys.4153049872 Jul 11 05:13:40 PM PDT 24 Jul 11 05:28:56 PM PDT 24 6602742747 ps
T909 /workspace/coverage/default/15.sram_ctrl_regwen.166705688 Jul 11 05:14:08 PM PDT 24 Jul 11 05:32:48 PM PDT 24 6119282188 ps
T910 /workspace/coverage/default/31.sram_ctrl_lc_escalation.2192916225 Jul 11 05:16:25 PM PDT 24 Jul 11 05:16:33 PM PDT 24 869771240 ps
T911 /workspace/coverage/default/19.sram_ctrl_executable.274207071 Jul 11 05:14:29 PM PDT 24 Jul 11 05:31:46 PM PDT 24 53648759666 ps
T912 /workspace/coverage/default/22.sram_ctrl_stress_all.2747027371 Jul 11 05:14:58 PM PDT 24 Jul 11 05:52:39 PM PDT 24 37807077421 ps
T913 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2959175598 Jul 11 05:16:47 PM PDT 24 Jul 11 05:16:51 PM PDT 24 226471086 ps
T914 /workspace/coverage/default/44.sram_ctrl_executable.3441538590 Jul 11 05:17:33 PM PDT 24 Jul 11 05:25:36 PM PDT 24 14592290223 ps
T915 /workspace/coverage/default/33.sram_ctrl_executable.2554108219 Jul 11 05:16:46 PM PDT 24 Jul 11 05:29:46 PM PDT 24 10003269229 ps
T916 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2166050071 Jul 11 05:16:45 PM PDT 24 Jul 11 05:16:47 PM PDT 24 41537122 ps
T917 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1850495506 Jul 11 05:16:28 PM PDT 24 Jul 11 05:16:29 PM PDT 24 28776497 ps
T918 /workspace/coverage/default/48.sram_ctrl_stress_all.2677114042 Jul 11 05:18:12 PM PDT 24 Jul 11 05:56:19 PM PDT 24 46478964850 ps
T120 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3277663441 Jul 11 05:16:02 PM PDT 24 Jul 11 05:16:26 PM PDT 24 899582384 ps
T919 /workspace/coverage/default/44.sram_ctrl_mem_walk.1672524625 Jul 11 05:17:46 PM PDT 24 Jul 11 05:17:58 PM PDT 24 472732854 ps
T920 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1122222029 Jul 11 05:17:20 PM PDT 24 Jul 11 05:19:21 PM PDT 24 309239596 ps
T921 /workspace/coverage/default/29.sram_ctrl_regwen.3506501987 Jul 11 05:16:05 PM PDT 24 Jul 11 05:34:52 PM PDT 24 12952623520 ps
T922 /workspace/coverage/default/22.sram_ctrl_partial_access.266602759 Jul 11 05:14:58 PM PDT 24 Jul 11 05:17:09 PM PDT 24 1092997258 ps
T923 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3067929596 Jul 11 04:59:00 PM PDT 24 Jul 11 05:01:38 PM PDT 24 6484279548 ps
T924 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1614204860 Jul 11 05:15:07 PM PDT 24 Jul 11 05:18:41 PM PDT 24 8369756632 ps
T925 /workspace/coverage/default/8.sram_ctrl_alert_test.3454095018 Jul 11 05:13:20 PM PDT 24 Jul 11 05:13:22 PM PDT 24 11867849 ps
T926 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.381166217 Jul 11 05:17:54 PM PDT 24 Jul 11 05:18:41 PM PDT 24 114640980 ps
T927 /workspace/coverage/default/43.sram_ctrl_lc_escalation.4287118101 Jul 11 05:17:47 PM PDT 24 Jul 11 05:17:55 PM PDT 24 2026665593 ps
T928 /workspace/coverage/default/44.sram_ctrl_smoke.2998542068 Jul 11 05:17:34 PM PDT 24 Jul 11 05:19:52 PM PDT 24 1268215910 ps
T929 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1790024016 Jul 11 05:13:35 PM PDT 24 Jul 11 05:13:41 PM PDT 24 69659889 ps
T930 /workspace/coverage/default/13.sram_ctrl_stress_all.3654455438 Jul 11 05:13:45 PM PDT 24 Jul 11 06:21:10 PM PDT 24 46011603285 ps
T931 /workspace/coverage/default/34.sram_ctrl_partial_access.588694399 Jul 11 05:16:46 PM PDT 24 Jul 11 05:18:25 PM PDT 24 1006670511 ps
T932 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1952413423 Jul 11 05:13:21 PM PDT 24 Jul 11 05:17:30 PM PDT 24 6021216112 ps
T933 /workspace/coverage/default/9.sram_ctrl_max_throughput.4112419603 Jul 11 05:13:35 PM PDT 24 Jul 11 05:15:06 PM PDT 24 444541288 ps
T934 /workspace/coverage/default/25.sram_ctrl_ram_cfg.2606458337 Jul 11 05:15:08 PM PDT 24 Jul 11 05:15:10 PM PDT 24 43279428 ps
T935 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2777194250 Jul 11 05:16:32 PM PDT 24 Jul 11 05:16:35 PM PDT 24 546237166 ps
T936 /workspace/coverage/default/42.sram_ctrl_ram_cfg.4241898329 Jul 11 05:17:44 PM PDT 24 Jul 11 05:17:46 PM PDT 24 38733346 ps
T937 /workspace/coverage/default/1.sram_ctrl_ram_cfg.759650457 Jul 11 04:58:45 PM PDT 24 Jul 11 04:58:48 PM PDT 24 74799062 ps
T938 /workspace/coverage/default/14.sram_ctrl_stress_all.3038850879 Jul 11 05:13:59 PM PDT 24 Jul 11 05:51:53 PM PDT 24 8976753690 ps
T939 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.270901368 Jul 11 04:58:52 PM PDT 24 Jul 11 05:00:48 PM PDT 24 1976061035 ps
T66 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1353489304 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:27 PM PDT 24 274148407 ps
T940 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2967948665 Jul 11 04:58:29 PM PDT 24 Jul 11 04:58:43 PM PDT 24 92134362 ps
T941 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3150877537 Jul 11 04:58:32 PM PDT 24 Jul 11 04:58:44 PM PDT 24 78223615 ps
T121 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3054474919 Jul 11 04:58:24 PM PDT 24 Jul 11 04:58:37 PM PDT 24 78633349 ps
T122 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3061514559 Jul 11 04:58:18 PM PDT 24 Jul 11 04:58:35 PM PDT 24 127004959 ps
T67 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2891865374 Jul 11 04:58:14 PM PDT 24 Jul 11 04:58:27 PM PDT 24 31259699 ps
T68 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1229195591 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:22 PM PDT 24 536051750 ps
T942 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1869595841 Jul 11 04:57:59 PM PDT 24 Jul 11 04:58:07 PM PDT 24 24588027 ps
T943 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.384272770 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:26 PM PDT 24 26968811 ps
T79 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.981884949 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:24 PM PDT 24 969302284 ps
T115 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.131932917 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:17 PM PDT 24 210878494 ps
T944 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2882695429 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:25 PM PDT 24 38024993 ps
T109 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4173581033 Jul 11 04:58:24 PM PDT 24 Jul 11 04:58:36 PM PDT 24 21776023 ps
T80 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.803354277 Jul 11 04:58:28 PM PDT 24 Jul 11 04:58:41 PM PDT 24 380249335 ps
T131 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2726826768 Jul 11 04:58:32 PM PDT 24 Jul 11 04:58:41 PM PDT 24 289037022 ps
T61 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.103452299 Jul 11 04:58:30 PM PDT 24 Jul 11 04:58:41 PM PDT 24 219302721 ps
T81 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1671437955 Jul 11 04:58:17 PM PDT 24 Jul 11 04:58:31 PM PDT 24 80157321 ps
T82 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2105229651 Jul 11 04:58:26 PM PDT 24 Jul 11 04:58:37 PM PDT 24 11760496 ps
T62 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1955235373 Jul 11 04:58:23 PM PDT 24 Jul 11 04:58:36 PM PDT 24 196937313 ps
T110 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1138983897 Jul 11 04:58:17 PM PDT 24 Jul 11 04:58:30 PM PDT 24 23526381 ps
T63 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1734209387 Jul 11 04:58:27 PM PDT 24 Jul 11 04:58:38 PM PDT 24 316635960 ps
T945 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3811343497 Jul 11 04:58:26 PM PDT 24 Jul 11 04:58:37 PM PDT 24 19845556 ps
T83 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.226940285 Jul 11 04:58:14 PM PDT 24 Jul 11 04:58:27 PM PDT 24 115939267 ps
T84 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2876828949 Jul 11 04:58:22 PM PDT 24 Jul 11 04:58:36 PM PDT 24 1074753250 ps
T134 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.570103975 Jul 11 04:58:36 PM PDT 24 Jul 11 04:58:44 PM PDT 24 815989706 ps
T85 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2235251708 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:24 PM PDT 24 24736508 ps
T86 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1645360837 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:21 PM PDT 24 27932841 ps
T946 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2787614878 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:28 PM PDT 24 208278145 ps
T947 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.496521347 Jul 11 04:58:17 PM PDT 24 Jul 11 04:58:31 PM PDT 24 69300369 ps
T948 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1694447796 Jul 11 04:58:22 PM PDT 24 Jul 11 04:58:35 PM PDT 24 27931185 ps
T949 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2417887756 Jul 11 04:58:28 PM PDT 24 Jul 11 04:58:40 PM PDT 24 499877101 ps
T950 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3638740300 Jul 11 04:58:19 PM PDT 24 Jul 11 04:58:32 PM PDT 24 27046070 ps
T951 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.78026988 Jul 11 04:58:04 PM PDT 24 Jul 11 04:58:13 PM PDT 24 15002800 ps
T952 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4140360172 Jul 11 04:58:15 PM PDT 24 Jul 11 04:58:32 PM PDT 24 83161642 ps
T953 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.210800037 Jul 11 04:58:26 PM PDT 24 Jul 11 04:58:39 PM PDT 24 166733551 ps
T137 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2574810154 Jul 11 04:58:24 PM PDT 24 Jul 11 04:58:37 PM PDT 24 429500491 ps
T954 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3819582180 Jul 11 04:58:29 PM PDT 24 Jul 11 04:58:39 PM PDT 24 27006446 ps
T955 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2077726124 Jul 11 04:58:28 PM PDT 24 Jul 11 04:58:38 PM PDT 24 33990260 ps
T98 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1742140666 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:25 PM PDT 24 26182870 ps
T956 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2461115030 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:27 PM PDT 24 29502242 ps
T957 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2986594215 Jul 11 04:58:18 PM PDT 24 Jul 11 04:58:32 PM PDT 24 26941283 ps
T87 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1911565416 Jul 11 04:58:30 PM PDT 24 Jul 11 04:58:40 PM PDT 24 213377840 ps
T958 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1254902014 Jul 11 04:58:25 PM PDT 24 Jul 11 04:58:36 PM PDT 24 59114514 ps
T959 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2029640078 Jul 11 04:58:18 PM PDT 24 Jul 11 04:58:33 PM PDT 24 61927242 ps
T960 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1559171642 Jul 11 04:58:22 PM PDT 24 Jul 11 04:58:37 PM PDT 24 637241292 ps
T88 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2935636027 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:26 PM PDT 24 906051117 ps
T138 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1790318723 Jul 11 04:58:20 PM PDT 24 Jul 11 04:58:34 PM PDT 24 743726463 ps
T961 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2698748929 Jul 11 04:58:31 PM PDT 24 Jul 11 04:58:40 PM PDT 24 28808002 ps
T962 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2393068654 Jul 11 04:58:22 PM PDT 24 Jul 11 04:58:35 PM PDT 24 108978108 ps
T135 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.863261455 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:25 PM PDT 24 99652650 ps
T963 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4114500015 Jul 11 04:58:33 PM PDT 24 Jul 11 04:58:41 PM PDT 24 26252635 ps
T964 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4219530117 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:22 PM PDT 24 25433993 ps
T965 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2177218579 Jul 11 04:58:14 PM PDT 24 Jul 11 04:58:28 PM PDT 24 74863485 ps
T966 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1061668021 Jul 11 04:58:17 PM PDT 24 Jul 11 04:58:30 PM PDT 24 16171444 ps
T967 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1193860926 Jul 11 04:58:28 PM PDT 24 Jul 11 04:58:38 PM PDT 24 14237302 ps
T968 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3701261598 Jul 11 04:58:29 PM PDT 24 Jul 11 04:58:39 PM PDT 24 14252651 ps
T969 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2307771594 Jul 11 04:58:30 PM PDT 24 Jul 11 04:58:40 PM PDT 24 58914464 ps
T970 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2313575927 Jul 11 04:58:21 PM PDT 24 Jul 11 04:58:34 PM PDT 24 69318590 ps
T971 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3372884188 Jul 11 04:58:18 PM PDT 24 Jul 11 04:58:35 PM PDT 24 170326526 ps
T972 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.256346799 Jul 11 04:58:28 PM PDT 24 Jul 11 04:58:38 PM PDT 24 59416750 ps
T973 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.607470002 Jul 11 04:58:32 PM PDT 24 Jul 11 04:58:41 PM PDT 24 80863921 ps
T89 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1899970822 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:18 PM PDT 24 38681467 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3488821592 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:23 PM PDT 24 21509046 ps
T975 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3914074752 Jul 11 04:58:35 PM PDT 24 Jul 11 04:58:43 PM PDT 24 56341548 ps
T976 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2302079005 Jul 11 04:58:38 PM PDT 24 Jul 11 04:58:42 PM PDT 24 29517390 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2954649166 Jul 11 04:58:15 PM PDT 24 Jul 11 04:58:28 PM PDT 24 31332022 ps
T978 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4060189195 Jul 11 04:58:21 PM PDT 24 Jul 11 04:58:36 PM PDT 24 152078566 ps
T979 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2759619493 Jul 11 04:58:25 PM PDT 24 Jul 11 04:58:37 PM PDT 24 72989675 ps
T90 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3414567275 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:22 PM PDT 24 1595232440 ps
T980 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3129655172 Jul 11 04:58:26 PM PDT 24 Jul 11 04:58:38 PM PDT 24 464247874 ps
T981 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1763192947 Jul 11 04:58:20 PM PDT 24 Jul 11 04:58:33 PM PDT 24 29575921 ps
T136 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1695315662 Jul 11 04:58:24 PM PDT 24 Jul 11 04:58:37 PM PDT 24 363050907 ps
T91 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3886681481 Jul 11 04:58:27 PM PDT 24 Jul 11 04:58:40 PM PDT 24 1611612738 ps
T982 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1810498937 Jul 11 04:58:19 PM PDT 24 Jul 11 04:58:33 PM PDT 24 160509329 ps
T983 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.74958608 Jul 11 04:58:23 PM PDT 24 Jul 11 04:58:35 PM PDT 24 47625919 ps
T984 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1216043046 Jul 11 04:58:30 PM PDT 24 Jul 11 04:58:40 PM PDT 24 27682475 ps
T985 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.658156676 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:16 PM PDT 24 35841845 ps
T92 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3576285862 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:26 PM PDT 24 780332093 ps
T986 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3327627310 Jul 11 04:58:22 PM PDT 24 Jul 11 04:58:35 PM PDT 24 355632193 ps
T99 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1780482451 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:22 PM PDT 24 211591747 ps
T139 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3188659923 Jul 11 04:58:22 PM PDT 24 Jul 11 04:58:36 PM PDT 24 744786682 ps
T987 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.92136287 Jul 11 04:58:14 PM PDT 24 Jul 11 04:58:28 PM PDT 24 29561915 ps
T988 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.334512456 Jul 11 04:58:25 PM PDT 24 Jul 11 04:58:37 PM PDT 24 239830121 ps
T989 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.181054464 Jul 11 04:58:33 PM PDT 24 Jul 11 04:58:45 PM PDT 24 150989312 ps
T990 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.40985363 Jul 11 04:58:27 PM PDT 24 Jul 11 04:58:38 PM PDT 24 23526658 ps
T100 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4150603278 Jul 11 04:58:30 PM PDT 24 Jul 11 04:58:42 PM PDT 24 437159651 ps
T991 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.615180131 Jul 11 04:58:28 PM PDT 24 Jul 11 04:58:40 PM PDT 24 1356462473 ps
T992 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3920950670 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:25 PM PDT 24 94257537 ps
T993 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2598279656 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:24 PM PDT 24 17528059 ps
T142 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.671469411 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:26 PM PDT 24 148975055 ps
T994 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3816688152 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:20 PM PDT 24 45384225 ps
T995 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2939490703 Jul 11 04:58:14 PM PDT 24 Jul 11 04:58:28 PM PDT 24 149880229 ps
T996 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2517830311 Jul 11 04:58:18 PM PDT 24 Jul 11 04:58:33 PM PDT 24 1198033102 ps
T997 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2194345037 Jul 11 04:58:19 PM PDT 24 Jul 11 04:58:32 PM PDT 24 19942278 ps
T998 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2105868307 Jul 11 04:58:06 PM PDT 24 Jul 11 04:58:16 PM PDT 24 134621118 ps
T999 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3033315440 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:27 PM PDT 24 27997466 ps
T101 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.948227401 Jul 11 04:58:31 PM PDT 24 Jul 11 04:58:41 PM PDT 24 717367693 ps
T1000 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4169196785 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:23 PM PDT 24 53102378 ps
T1001 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3079747517 Jul 11 04:58:29 PM PDT 24 Jul 11 04:58:39 PM PDT 24 39741085 ps
T1002 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.907984444 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:25 PM PDT 24 295068063 ps
T1003 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1213975179 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:26 PM PDT 24 74409935 ps
T105 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2107165591 Jul 11 04:58:40 PM PDT 24 Jul 11 04:58:45 PM PDT 24 444342462 ps
T102 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2589726969 Jul 11 04:58:37 PM PDT 24 Jul 11 04:58:45 PM PDT 24 422966474 ps
T1004 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2926388228 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:23 PM PDT 24 28300869 ps
T1005 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2770328998 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:17 PM PDT 24 103284688 ps
T103 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1073683460 Jul 11 04:58:21 PM PDT 24 Jul 11 04:58:34 PM PDT 24 29551497 ps
T133 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.517624269 Jul 11 04:58:21 PM PDT 24 Jul 11 04:58:35 PM PDT 24 152068406 ps
T104 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.509389379 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:25 PM PDT 24 336063401 ps
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