Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13994682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59971336

1

T1

318753

T2

3071

T3

480334

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36876275	1			T1	174015		T2	1024		T3	264337
values[0x0]	17147859	1			T1	83943		T2	1002		T3	126666
values[0x1]	19941884	1			T1	89892		T2	1045		T3	137165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6971271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66994747

1

T1

333364

T2

3071

T3

504385

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	328196	1			T1	1270		T2	14		T3	7699
valid_sources[0x01]	321014	1			T1	1366		T2	18		T3	777
valid_sources[0x02]	271479	1			T1	1386		T2	21		T3	1077
valid_sources[0x03]	314381	1			T1	1408		T2	19		T3	935
valid_sources[0x04]	254236	1			T1	1303		T2	8		T3	2318
valid_sources[0x05]	279258	1			T1	1315		T2	8		T3	1074
valid_sources[0x06]	321932	1			T1	1322		T2	9		T3	1035
valid_sources[0x07]	262874	1			T1	1349		T2	18		T3	903
valid_sources[0x08]	262622	1			T1	1356		T2	9		T3	11351
valid_sources[0x09]	310166	1			T1	1408		T2	11		T3	1350
valid_sources[0x0a]	310107	1			T1	1415		T2	12		T3	985
valid_sources[0x0b]	259944	1			T1	1383		T2	10		T3	799
valid_sources[0x0c]	285035	1			T1	1369		T2	3		T3	1637
valid_sources[0x0d]	267855	1			T1	1371		T2	16		T3	759
valid_sources[0x0e]	259879	1			T1	1335		T2	13		T3	484
valid_sources[0x0f]	261478	1			T1	1368		T2	10		T3	1179
valid_sources[0x10]	273681	1			T1	1311		T2	6		T3	891
valid_sources[0x11]	288001	1			T1	1394		T2	7		T3	369
valid_sources[0x12]	290432	1			T1	1296		T2	6		T3	602
valid_sources[0x13]	323291	1			T1	1357		T2	12		T3	350
valid_sources[0x14]	256307	1			T1	1394		T2	11		T3	240
valid_sources[0x15]	268990	1			T1	1419		T2	7		T3	699
valid_sources[0x16]	291003	1			T1	1353		T2	10		T3	1976
valid_sources[0x17]	254256	1			T1	1268		T2	11		T3	379
valid_sources[0x18]	253528	1			T1	1397		T2	10		T3	103
valid_sources[0x19]	266481	1			T1	1338		T2	12		T3	998
valid_sources[0x1a]	320625	1			T1	1351		T2	12		T3	1423
valid_sources[0x1b]	261439	1			T1	1367		T2	7		T3	1258
valid_sources[0x1c]	332882	1			T1	1386		T2	30		T3	899
valid_sources[0x1d]	304018	1			T1	1336		T2	7		T3	457
valid_sources[0x1e]	263385	1			T1	1355		T2	18		T3	378
valid_sources[0x1f]	268810	1			T1	1327		T2	25		T3	627
valid_sources[0x20]	260737	1			T1	1385		T2	11		T3	1228
valid_sources[0x21]	292624	1			T1	1397		T2	23		T3	1383
valid_sources[0x22]	275922	1			T1	1317		T2	11		T3	5949
valid_sources[0x23]	349214	1			T1	1370		T2	8		T3	1632
valid_sources[0x24]	277744	1			T1	1392		T2	15		T3	675
valid_sources[0x25]	291579	1			T1	1323		T2	15		T3	1057
valid_sources[0x26]	290297	1			T1	1338		T2	15		T3	15398
valid_sources[0x27]	287846	1			T1	1404		T2	19		T3	21996
valid_sources[0x28]	263815	1			T1	1291		T2	8		T3	484
valid_sources[0x29]	303942	1			T1	1279		T2	9		T3	621
valid_sources[0x2a]	299267	1			T1	1329		T2	4		T3	1195
valid_sources[0x2b]	328334	1			T1	1322		T2	19		T3	1150
valid_sources[0x2c]	269607	1			T1	1377		T2	3		T3	733
valid_sources[0x2d]	292626	1			T1	1355		T2	10		T3	9449
valid_sources[0x2e]	253766	1			T1	1361		T2	14		T3	679
valid_sources[0x2f]	273700	1			T1	1400		T2	20		T3	455
valid_sources[0x30]	260017	1			T1	1410		T2	14		T3	215
valid_sources[0x31]	291159	1			T1	1388		T2	14		T3	828
valid_sources[0x32]	260598	1			T1	1411		T2	10		T3	520
valid_sources[0x33]	264459	1			T1	1329		T2	7		T3	659
valid_sources[0x34]	295836	1			T1	1405		T2	6		T3	1296
valid_sources[0x35]	300707	1			T1	1373		T2	8		T3	10538
valid_sources[0x36]	269208	1			T1	1401		T2	8		T3	513
valid_sources[0x37]	279640	1			T1	1406		T2	17		T3	857
valid_sources[0x38]	292097	1			T1	1471		T2	5		T3	1437
valid_sources[0x39]	267874	1			T1	1341		T2	22		T3	1036
valid_sources[0x3a]	294268	1			T1	1370		T2	10		T3	971
valid_sources[0x3b]	262844	1			T1	1330		T2	15		T3	579
valid_sources[0x3c]	264366	1			T1	1350		T2	6		T3	696
valid_sources[0x3d]	291249	1			T1	1340		T2	18		T3	1536
valid_sources[0x3e]	307735	1			T1	1334		T2	17		T3	1293
valid_sources[0x3f]	317740	1			T1	1422		T2	13		T3	586
valid_sources[0x40]	302253	1			T1	1351		T2	5		T3	647
valid_sources[0x41]	373947	1			T1	1406		T2	27		T3	1123
valid_sources[0x42]	341351	1			T1	1350		T2	10		T3	684
valid_sources[0x43]	349509	1			T1	1379		T2	7		T3	564
valid_sources[0x44]	290963	1			T1	1422		T2	12		T3	154
valid_sources[0x45]	288053	1			T1	1400		T2	8		T3	464
valid_sources[0x46]	298266	1			T1	1334		T2	18		T3	34406
valid_sources[0x47]	257444	1			T1	1352		T2	35		T3	797
valid_sources[0x48]	263916	1			T1	1381		T2	16		T3	378
valid_sources[0x49]	325640	1			T1	1444		T2	9		T3	1079
valid_sources[0x4a]	294325	1			T1	1383		T2	13		T3	525
valid_sources[0x4b]	301173	1			T1	1343		T2	10		T3	531
valid_sources[0x4c]	324375	1			T1	1409		T2	6		T3	1058
valid_sources[0x4d]	275379	1			T1	1352		T2	9		T3	1205
valid_sources[0x4e]	261872	1			T1	1380		T2	23		T3	1682
valid_sources[0x4f]	358264	1			T1	1430		T2	9		T3	1167
valid_sources[0x50]	254982	1			T1	1328		T2	21		T3	1340
valid_sources[0x51]	283977	1			T1	1348		T2	10		T3	620
valid_sources[0x52]	311550	1			T1	1374		T2	16		T3	1527
valid_sources[0x53]	290524	1			T1	1523		T2	8		T3	1881
valid_sources[0x54]	302039	1			T1	1341		T2	18		T3	1142
valid_sources[0x55]	257554	1			T1	1278		T2	9		T3	240
valid_sources[0x56]	330883	1			T1	1305		T2	15		T3	808
valid_sources[0x57]	267169	1			T1	1421		T2	9		T3	1573
valid_sources[0x58]	262824	1			T1	1422		T2	14		T3	723
valid_sources[0x59]	264198	1			T1	1321		T2	19		T3	374
valid_sources[0x5a]	278110	1			T1	1361		T2	23		T3	1146
valid_sources[0x5b]	260480	1			T1	1377		T2	5		T3	345
valid_sources[0x5c]	272637	1			T1	1369		T2	13		T3	906
valid_sources[0x5d]	288375	1			T1	1364		T2	17		T3	30217
valid_sources[0x5e]	351998	1			T1	1388		T2	9		T3	167
valid_sources[0x5f]	371467	1			T1	1292		T2	4		T3	2294
valid_sources[0x60]	309088	1			T1	1334		T2	16		T3	628
valid_sources[0x61]	262817	1			T1	1313		T2	11		T3	1263
valid_sources[0x62]	325002	1			T1	1350		T2	15		T3	899
valid_sources[0x63]	263709	1			T1	1358		T2	20		T3	931
valid_sources[0x64]	265012	1			T1	1346		T2	2		T3	1466
valid_sources[0x65]	265186	1			T1	1439		T2	10		T3	668
valid_sources[0x66]	294128	1			T1	1429		T2	12		T3	225
valid_sources[0x67]	288738	1			T1	1374		T2	2		T3	1540
valid_sources[0x68]	282950	1			T1	1370		T2	7		T3	17979
valid_sources[0x69]	284917	1			T1	1365		T2	25		T3	439
valid_sources[0x6a]	265139	1			T1	1382		T2	12		T3	322
valid_sources[0x6b]	273788	1			T1	1375		T2	17		T3	1182
valid_sources[0x6c]	354670	1			T1	1343		T2	16		T3	1121
valid_sources[0x6d]	284252	1			T1	1316		T2	17		T3	1161
valid_sources[0x6e]	276964	1			T1	1390		T2	9		T3	1351
valid_sources[0x6f]	261136	1			T1	1350		T2	16		T3	747
valid_sources[0x70]	269192	1			T1	1379		T2	8		T3	964
valid_sources[0x71]	260219	1			T1	1347		T2	14		T3	1213
valid_sources[0x72]	263384	1			T1	1338		T2	8		T3	898
valid_sources[0x73]	268230	1			T1	1411		T2	11		T3	930
valid_sources[0x74]	305306	1			T1	1353		T2	18		T3	771
valid_sources[0x75]	310482	1			T1	1302		T2	13		T3	664
valid_sources[0x76]	278158	1			T1	1310		T2	11		T3	555
valid_sources[0x77]	296063	1			T1	1331		T2	3		T3	707
valid_sources[0x78]	286717	1			T1	1360		T2	10		T3	9340
valid_sources[0x79]	266643	1			T1	1255		T2	10		T3	1553
valid_sources[0x7a]	267819	1			T1	1338		T2	7		T3	1076
valid_sources[0x7b]	304996	1			T1	1438		T2	7		T3	704
valid_sources[0x7c]	284569	1			T1	1301		T2	17		T3	937
valid_sources[0x7d]	280954	1			T1	1332		T2	13		T3	1224
valid_sources[0x7e]	309008	1			T1	1385		T2	3		T3	2852
valid_sources[0x7f]	276936	1			T1	1366		T2	12		T3	11958
valid_sources[0x80]	260997	1			T1	1347		T2	7		T3	1243

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29883768

1

T1

159344

T2

1024

T3

240449

values[0x0]

all_enables

biggest_size

15047770

1

T1

79608

T2

1002

T3

119515

values[0x1]

all_enables

biggest_size

15039798

1

T1

79801

T2

1045

T3

120370

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124293

1

T1

31

T2

2

T3

70

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46043	1			T1	18		T3	62		T8	39
values[0x0]	54627	1			T1	30		T2	3		T3	69
values[0x1]	58580	1			T1	29		T2	2		T3	82

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132544

1

T1

40

T2

2

T3

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1287	1			T21	23		T22	156		T20	1
valid_sources[0x01]	372	1			T2	1		T21	20		T67	1
valid_sources[0x02]	638	1			T21	26		T22	3		T5	8
valid_sources[0x03]	582	1			T21	14		T18	7		T138	1
valid_sources[0x04]	568	1			T40	17		T21	22		T22	25
valid_sources[0x05]	600	1			T21	22		T145	3		T138	1
valid_sources[0x06]	859	1			T21	30		T22	45		T67	1
valid_sources[0x07]	785	1			T21	25		T67	1		T75	1
valid_sources[0x08]	524	1			T21	35		T138	1		T19	2
valid_sources[0x09]	541	1			T55	3		T21	30		T42	1
valid_sources[0x0a]	543	1			T21	26		T137	52		T146	2
valid_sources[0x0b]	526	1			T21	25		T75	1		T43	1
valid_sources[0x0c]	466	1			T21	27		T139	1		T147	1
valid_sources[0x0d]	641	1			T21	26		T42	1		T139	3
valid_sources[0x0e]	495	1			T13	1		T21	25		T139	2
valid_sources[0x0f]	724	1			T21	21		T42	1		T147	1
valid_sources[0x10]	1053	1			T21	35		T22	9		T75	1
valid_sources[0x11]	597	1			T3	29		T21	32		T5	6
valid_sources[0x12]	626	1			T21	28		T18	1		T75	2
valid_sources[0x13]	741	1			T21	26		T26	1		T75	1
valid_sources[0x14]	464	1			T21	20		T22	3		T75	2
valid_sources[0x15]	598	1			T21	27		T62	5		T143	1
valid_sources[0x16]	685	1			T21	17		T139	1		T14	1
valid_sources[0x17]	565	1			T21	33		T67	2		T148	2
valid_sources[0x18]	598	1			T21	24		T62	6		T100	1
valid_sources[0x19]	493	1			T21	24		T143	1		T149	15
valid_sources[0x1a]	648	1			T21	14		T139	1		T138	3
valid_sources[0x1b]	734	1			T21	22		T22	3		T150	1
valid_sources[0x1c]	937	1			T3	22		T21	26		T67	3
valid_sources[0x1d]	1053	1			T21	26		T22	176		T62	2
valid_sources[0x1e]	651	1			T21	35		T139	1		T150	1
valid_sources[0x1f]	524	1			T21	37		T75	1		T23	21
valid_sources[0x20]	498	1			T21	42		T14	1		T23	19
valid_sources[0x21]	508	1			T21	17		T5	5		T48	1
valid_sources[0x22]	542	1			T21	17		T146	1		T149	2
valid_sources[0x23]	539	1			T21	13		T23	29		T53	2
valid_sources[0x24]	482	1			T21	14		T150	1		T20	2
valid_sources[0x25]	509	1			T21	27		T18	1		T75	1
valid_sources[0x26]	969	1			T57	2		T21	34		T138	1
valid_sources[0x27]	457	1			T21	31		T24	4		T20	1
valid_sources[0x28]	575	1			T3	13		T12	2		T21	29
valid_sources[0x29]	757	1			T21	22		T18	1		T75	1
valid_sources[0x2a]	600	1			T21	22		T139	1		T143	2
valid_sources[0x2b]	679	1			T3	3		T21	31		T22	127
valid_sources[0x2c]	501	1			T21	35		T67	1		T75	2
valid_sources[0x2d]	828	1			T4	1		T21	16		T18	2
valid_sources[0x2e]	730	1			T21	28		T75	1		T147	1
valid_sources[0x2f]	619	1			T21	29		T146	5		T23	28
valid_sources[0x30]	672	1			T13	1		T21	41		T23	17
valid_sources[0x31]	532	1			T21	31		T138	3		T151	2
valid_sources[0x32]	534	1			T21	29		T138	1		T143	1
valid_sources[0x33]	598	1			T21	14		T75	1		T23	33
valid_sources[0x34]	472	1			T21	13		T18	1		T75	1
valid_sources[0x35]	478	1			T21	45		T24	2		T75	1
valid_sources[0x36]	701	1			T21	29		T62	4		T152	1
valid_sources[0x37]	567	1			T13	1		T21	29		T22	1
valid_sources[0x38]	700	1			T13	1		T21	27		T42	1
valid_sources[0x39]	843	1			T21	24		T18	1		T75	2
valid_sources[0x3a]	731	1			T13	1		T55	2		T21	15
valid_sources[0x3b]	683	1			T13	1		T21	25		T153	2
valid_sources[0x3c]	563	1			T55	1		T21	26		T145	5
valid_sources[0x3d]	680	1			T21	23		T62	9		T154	1
valid_sources[0x3e]	673	1			T21	11		T22	2		T18	3
valid_sources[0x3f]	682	1			T21	23		T18	5		T138	1
valid_sources[0x40]	520	1			T21	34		T19	1		T143	1
valid_sources[0x41]	514	1			T55	2		T21	21		T139	5
valid_sources[0x42]	501	1			T21	25		T147	1		T23	36
valid_sources[0x43]	521	1			T21	26		T41	17		T143	1
valid_sources[0x44]	489	1			T21	39		T75	1		T138	1
valid_sources[0x45]	590	1			T21	32		T18	1		T75	1
valid_sources[0x46]	691	1			T3	11		T21	29		T150	1
valid_sources[0x47]	555	1			T21	24		T43	2		T23	42
valid_sources[0x48]	734	1			T21	25		T23	14		T53	1
valid_sources[0x49]	622	1			T21	26		T18	3		T23	32
valid_sources[0x4a]	795	1			T21	40		T42	1		T75	1
valid_sources[0x4b]	616	1			T12	4		T21	22		T68	1
valid_sources[0x4c]	566	1			T21	35		T138	1		T19	2
valid_sources[0x4d]	606	1			T21	24		T68	3		T20	1
valid_sources[0x4e]	527	1			T21	14		T22	3		T75	1
valid_sources[0x4f]	733	1			T21	38		T143	2		T155	2
valid_sources[0x50]	481	1			T21	27		T138	1		T19	1
valid_sources[0x51]	614	1			T21	16		T62	4		T139	10
valid_sources[0x52]	442	1			T21	35		T75	1		T23	27
valid_sources[0x53]	474	1			T3	8		T21	41		T42	1
valid_sources[0x54]	567	1			T21	28		T18	2		T102	1
valid_sources[0x55]	618	1			T21	26		T138	1		T156	17
valid_sources[0x56]	644	1			T21	43		T75	3		T23	38
valid_sources[0x57]	548	1			T21	21		T144	1		T139	4
valid_sources[0x58]	525	1			T21	40		T138	1		T23	26
valid_sources[0x59]	524	1			T21	27		T68	3		T154	1
valid_sources[0x5a]	454	1			T38	3		T21	22		T47	1
valid_sources[0x5b]	854	1			T21	25		T5	1		T18	1
valid_sources[0x5c]	637	1			T21	43		T22	3		T147	1
valid_sources[0x5d]	550	1			T3	1		T11	2		T13	1
valid_sources[0x5e]	536	1			T21	29		T149	1		T23	26
valid_sources[0x5f]	434	1			T21	30		T5	10		T18	7
valid_sources[0x60]	498	1			T55	1		T21	21		T18	1
valid_sources[0x61]	592	1			T13	1		T55	1		T21	32
valid_sources[0x62]	534	1			T21	24		T22	93		T23	31
valid_sources[0x63]	602	1			T21	31		T67	2		T14	1
valid_sources[0x64]	655	1			T21	26		T145	1		T138	2
valid_sources[0x65]	746	1			T21	15		T5	1		T145	1
valid_sources[0x66]	468	1			T63	4		T21	17		T22	12
valid_sources[0x67]	669	1			T21	32		T75	2		T23	25
valid_sources[0x68]	577	1			T21	22		T75	1		T139	1
valid_sources[0x69]	622	1			T21	34		T22	103		T73	1
valid_sources[0x6a]	724	1			T21	30		T75	1		T138	1
valid_sources[0x6b]	829	1			T13	1		T21	24		T68	3
valid_sources[0x6c]	506	1			T3	7		T21	25		T18	2
valid_sources[0x6d]	812	1			T13	1		T21	16		T139	3
valid_sources[0x6e]	558	1			T21	35		T62	3		T145	4
valid_sources[0x6f]	530	1			T21	24		T75	1		T145	1
valid_sources[0x70]	728	1			T21	28		T102	1		T157	1
valid_sources[0x71]	563	1			T56	2		T21	18		T5	6
valid_sources[0x72]	645	1			T21	19		T22	3		T24	1
valid_sources[0x73]	655	1			T21	29		T18	2		T67	2
valid_sources[0x74]	807	1			T2	1		T3	17		T21	22
valid_sources[0x75]	664	1			T21	31		T24	4		T146	1
valid_sources[0x76]	886	1			T13	3		T21	32		T22	261
valid_sources[0x77]	545	1			T21	30		T48	1		T139	5
valid_sources[0x78]	539	1			T55	2		T21	28		T42	2
valid_sources[0x79]	586	1			T21	14		T75	1		T138	1
valid_sources[0x7a]	671	1			T21	22		T22	125		T139	1
valid_sources[0x7b]	478	1			T21	18		T62	4		T67	4
valid_sources[0x7c]	512	1			T21	22		T75	1		T139	1
valid_sources[0x7d]	820	1			T10	2		T21	22		T18	1
valid_sources[0x7e]	508	1			T21	34		T18	1		T75	1
valid_sources[0x7f]	998	1			T9	2		T21	23		T22	385
valid_sources[0x80]	953	1			T21	29		T22	111		T62	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34071

1

T1

9

T3

30

T8

16

values[0x0]

all_enables

biggest_size

46062

1

T1

17

T2

1

T3

26

values[0x1]

all_enables

biggest_size

44160

1

T1

5

T2

1

T3

14