Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13637749

1

T1

28982

T3

40852

T4

125

full_word

54725439

1

T1

317395

T2

3071

T3

410204

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68362908	1			T1	346377		T2	3071		T3	451056
auto[TlIntgErrCmd]	82	1			T59	3		T60	4		T61	3
auto[TlIntgErrData]	92	1			T59	3		T60	8		T61	5
auto[TlIntgErrBoth]	106	1			T59	4		T60	8		T61	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31231207

1

T1

173278

T2

1024

T3

189414

auto[1]

37131981

1

T1

173099

T2

2047

T3

261642

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6509811	1			T1	14611		T3	17130		T4	50
auto[TlIntgErrNone]	partial	auto[1]	7127688	1			T1	14371		T3	23722		T4	75
auto[TlIntgErrNone]	full_word	auto[0]	24721283	1			T1	158667		T2	1024		T3	172284
auto[TlIntgErrNone]	full_word	auto[1]	30004126	1			T1	158728		T2	2047		T3	237920
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T59	3		T61	2		T127	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T60	4		T61	1		T130	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T130	1		T131	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T125	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T59	1		T60	5		T61	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T59	1		T60	2		T61	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T60	1		T131	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	12	1			T59	1		T61	2		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T59	2		T60	3		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T59	2		T60	4		T61	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T128	1		T134	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T60	1		T135	1		T134	1