Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	692791	1			T3	289		T4	89		T40	201
auto[1]	10188132	1			T1	97301		T3	2295		T4	61
auto[2]	581608	1			T3	156		T4	63		T40	93
auto[3]	10082232	1			T1	97132		T3	2195		T4	34

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14220175	1			T1	162116		T3	3463		T4	190
auto[1]	2025726	1			T1	15460		T3	559		T4	24
auto[2]	2055347	1			T1	15323		T3	816		T4	28
auto[3]	3243515	1			T1	1534		T3	97		T4	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8627225

1

T1

194236

T3

4930

T4

247

auto[1]

12917538

1

T1

197

T3

5

T8

38

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	275782	1			T3	230		T4	75		T40	169
auto[0]	auto[0]	auto[1]	28080	1			T3	26		T4	8		T40	19
auto[0]	auto[0]	auto[2]	28079	1			T3	28		T4	5		T40	13
auto[0]	auto[0]	auto[3]	6671	1			T3	4		T4	1		T58	1
auto[0]	auto[1]	auto[0]	3276959	1			T1	80901		T3	1713		T4	44
auto[0]	auto[1]	auto[1]	343123	1			T1	7401		T3	357		T4	12
auto[0]	auto[1]	auto[2]	330249	1			T1	8134		T3	183		T4	3
auto[0]	auto[1]	auto[3]	72114	1			T1	779		T3	40		T4	2
auto[0]	auto[2]	auto[0]	233839	1			T4	49		T39	13		T21	28
auto[0]	auto[2]	auto[1]	23644	1			T4	2		T39	65		T21	1
auto[0]	auto[2]	auto[2]	26612	1			T3	141		T4	12		T40	87
auto[0]	auto[2]	auto[3]	5499	1			T3	14		T40	6		T58	9
auto[0]	auto[3]	auto[0]	3233500	1			T1	81050		T3	1517		T4	22
auto[0]	auto[3]	auto[1]	326571	1			T1	8042		T3	175		T4	2
auto[0]	auto[3]	auto[2]	342944	1			T1	7176		T3	463		T4	8
auto[0]	auto[3]	auto[3]	73559	1			T1	753		T3	39		T4	2
auto[1]	auto[0]	auto[0]	12018	1			T3	1		T5	17		T62	6
auto[1]	auto[0]	auto[1]	52835	1			T5	1		T104	648		T141	1837
auto[1]	auto[0]	auto[2]	52866	1			T5	4		T104	687		T141	1884
auto[1]	auto[0]	auto[3]	236460	1			T39	2		T104	3004		T140	1
auto[1]	auto[1]	auto[0]	3591379	1			T1	69		T3	1		T8	17
auto[1]	auto[1]	auto[1]	628774	1			T1	7		T3	1		T8	1
auto[1]	auto[1]	auto[2]	607023	1			T1	9		T8	2		T10	1
auto[1]	auto[1]	auto[3]	1338511	1			T1	1		T38	928		T63	52906
auto[1]	auto[2]	auto[0]	7723	1			T5	13		T62	2		T137	3
auto[1]	auto[2]	auto[1]	34196	1			T5	1		T141	1118		T142	4929
auto[1]	auto[2]	auto[2]	45658	1			T3	1		T5	1		T104	562
auto[1]	auto[2]	auto[3]	204437	1			T39	1		T5	1		T104	2718
auto[1]	auto[3]	auto[0]	3588975	1			T1	96		T3	1		T8	14
auto[1]	auto[3]	auto[1]	588503	1			T1	10		T8	3		T38	8828
auto[1]	auto[3]	auto[2]	621916	1			T1	4		T8	1		T10	1
auto[1]	auto[3]	auto[3]	1306264	1			T1	1		T38	875		T63	53469