Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	320388779	181409	0	0
ctrl_regwen_rd_A	320388779	3079	0	0
exec_rd_A	320388779	2777	0	0
exec_regwen_rd_A	320388779	3081	0	0
readback_rd_A	320388779	2146	0	0
readback_regwen_rd_A	320388779	1908	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320388779	181409	0	0
T5	435953	0	0	0
T18	117746	0	0	0
T21	335080	9491	0	0
T22	219092	5191	0	0
T23	0	11837	0	0
T24	114928	0	0	0
T41	144822	0	0	0
T45	0	1556	0	0
T46	0	5093	0	0
T53	0	1152	0	0
T54	0	3554	0	0
T62	178341	0	0	0
T69	0	3670	0	0
T70	0	2628	0	0
T71	0	2607	0	0
T72	225228	0	0	0
T73	11270	0	0	0
T74	5773	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320388779	3079	0	0
T46	170944	427	0	0
T70	0	176	0	0
T106	0	278	0	0
T107	0	104	0	0
T108	0	203	0	0
T109	0	114	0	0
T110	0	60	0	0
T111	0	59	0	0
T112	0	384	0	0
T113	0	136	0	0
T114	9162	0	0	0
T115	145120	0	0	0
T116	220141	0	0	0
T117	1184	0	0	0
T118	6528	0	0	0
T119	857597	0	0	0
T120	236458	0	0	0
T121	72892	0	0	0
T122	76568	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320388779	2777	0	0
T46	170944	275	0	0
T70	0	182	0	0
T106	0	299	0	0
T107	0	81	0	0
T108	0	198	0	0
T109	0	85	0	0
T110	0	49	0	0
T111	0	54	0	0
T112	0	341	0	0
T113	0	166	0	0
T114	9162	0	0	0
T115	145120	0	0	0
T116	220141	0	0	0
T117	1184	0	0	0
T118	6528	0	0	0
T119	857597	0	0	0
T120	236458	0	0	0
T121	72892	0	0	0
T122	76568	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320388779	3081	0	0
T46	170944	446	0	0
T70	0	205	0	0
T106	0	393	0	0
T107	0	57	0	0
T108	0	150	0	0
T109	0	160	0	0
T110	0	81	0	0
T111	0	77	0	0
T112	0	398	0	0
T113	0	128	0	0
T114	9162	0	0	0
T115	145120	0	0	0
T116	220141	0	0	0
T117	1184	0	0	0
T118	6528	0	0	0
T119	857597	0	0	0
T120	236458	0	0	0
T121	72892	0	0	0
T122	76568	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320388779	2146	0	0
T46	170944	397	0	0
T70	0	163	0	0
T106	0	313	0	0
T107	0	58	0	0
T108	0	135	0	0
T109	0	123	0	0
T110	0	42	0	0
T111	0	62	0	0
T112	0	401	0	0
T113	0	136	0	0
T114	9162	0	0	0
T115	145120	0	0	0
T116	220141	0	0	0
T117	1184	0	0	0
T118	6528	0	0	0
T119	857597	0	0	0
T120	236458	0	0	0
T121	72892	0	0	0
T122	76568	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320388779	1908	0	0
T46	170944	287	0	0
T70	0	132	0	0
T106	0	287	0	0
T107	0	59	0	0
T108	0	128	0	0
T109	0	82	0	0
T110	0	46	0	0
T111	0	77	0	0
T112	0	257	0	0
T113	0	173	0	0
T114	9162	0	0	0
T115	145120	0	0	0
T116	220141	0	0	0
T117	1184	0	0	0
T118	6528	0	0	0
T119	857597	0	0	0
T120	236458	0	0	0
T121	72892	0	0	0
T122	76568	0	0	0