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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T312 /workspace/coverage/default/42.sram_ctrl_regwen.634260058 Jul 12 05:16:48 PM PDT 24 Jul 12 05:20:52 PM PDT 24 1977345353 ps
T313 /workspace/coverage/default/32.sram_ctrl_bijection.2881270304 Jul 12 05:15:15 PM PDT 24 Jul 12 05:15:38 PM PDT 24 406261633 ps
T314 /workspace/coverage/default/49.sram_ctrl_alert_test.811344948 Jul 12 05:17:56 PM PDT 24 Jul 12 05:17:57 PM PDT 24 47048143 ps
T315 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2083320724 Jul 12 05:14:39 PM PDT 24 Jul 12 05:14:45 PM PDT 24 104695101 ps
T316 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2016511599 Jul 12 05:13:59 PM PDT 24 Jul 12 05:14:47 PM PDT 24 382918361 ps
T317 /workspace/coverage/default/29.sram_ctrl_mem_walk.1836463238 Jul 12 05:14:56 PM PDT 24 Jul 12 05:15:05 PM PDT 24 181808248 ps
T318 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.4194658862 Jul 12 05:14:39 PM PDT 24 Jul 12 05:17:49 PM PDT 24 2386986241 ps
T15 /workspace/coverage/default/3.sram_ctrl_sec_cm.78302109 Jul 12 05:12:43 PM PDT 24 Jul 12 05:12:49 PM PDT 24 426212816 ps
T29 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.435003983 Jul 12 05:15:13 PM PDT 24 Jul 12 05:16:25 PM PDT 24 452837948 ps
T30 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2997671533 Jul 12 05:16:33 PM PDT 24 Jul 12 05:23:18 PM PDT 24 1226187159 ps
T31 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2751536350 Jul 12 05:13:23 PM PDT 24 Jul 12 05:13:25 PM PDT 24 80456317 ps
T32 /workspace/coverage/default/30.sram_ctrl_mem_walk.2878262647 Jul 12 05:14:58 PM PDT 24 Jul 12 05:15:08 PM PDT 24 133781147 ps
T33 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3969088274 Jul 12 05:14:40 PM PDT 24 Jul 12 05:14:45 PM PDT 24 253290678 ps
T34 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4196103989 Jul 12 05:15:20 PM PDT 24 Jul 12 05:19:41 PM PDT 24 40038490970 ps
T35 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3587344009 Jul 12 05:14:06 PM PDT 24 Jul 12 05:16:47 PM PDT 24 6812462291 ps
T36 /workspace/coverage/default/2.sram_ctrl_smoke.1960262036 Jul 12 05:12:41 PM PDT 24 Jul 12 05:12:54 PM PDT 24 1026661680 ps
T37 /workspace/coverage/default/36.sram_ctrl_executable.1819539990 Jul 12 05:15:49 PM PDT 24 Jul 12 05:34:57 PM PDT 24 60701484411 ps
T319 /workspace/coverage/default/24.sram_ctrl_executable.3471389459 Jul 12 05:14:16 PM PDT 24 Jul 12 05:33:33 PM PDT 24 6924685999 ps
T320 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2513053927 Jul 12 05:14:56 PM PDT 24 Jul 12 05:18:19 PM PDT 24 8165379533 ps
T321 /workspace/coverage/default/23.sram_ctrl_executable.3569046115 Jul 12 05:14:08 PM PDT 24 Jul 12 05:24:55 PM PDT 24 30073692271 ps
T322 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3465608143 Jul 12 05:13:48 PM PDT 24 Jul 12 05:13:51 PM PDT 24 721556352 ps
T323 /workspace/coverage/default/16.sram_ctrl_bijection.3878996720 Jul 12 05:13:29 PM PDT 24 Jul 12 05:13:56 PM PDT 24 2345891446 ps
T324 /workspace/coverage/default/48.sram_ctrl_alert_test.3244028086 Jul 12 05:17:37 PM PDT 24 Jul 12 05:17:38 PM PDT 24 42928768 ps
T325 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2784329054 Jul 12 05:12:56 PM PDT 24 Jul 12 05:13:02 PM PDT 24 589411332 ps
T326 /workspace/coverage/default/11.sram_ctrl_alert_test.4067435540 Jul 12 05:13:20 PM PDT 24 Jul 12 05:13:21 PM PDT 24 26334104 ps
T327 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.717049098 Jul 12 05:17:40 PM PDT 24 Jul 12 05:20:27 PM PDT 24 578348162 ps
T328 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1870419660 Jul 12 05:16:56 PM PDT 24 Jul 12 05:20:41 PM PDT 24 11468239694 ps
T329 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3743021275 Jul 12 05:13:12 PM PDT 24 Jul 12 05:13:17 PM PDT 24 568693316 ps
T330 /workspace/coverage/default/48.sram_ctrl_mem_walk.1297751923 Jul 12 05:17:43 PM PDT 24 Jul 12 05:17:54 PM PDT 24 473252793 ps
T331 /workspace/coverage/default/42.sram_ctrl_bijection.3406653884 Jul 12 05:16:36 PM PDT 24 Jul 12 05:17:38 PM PDT 24 3554075169 ps
T332 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.430858056 Jul 12 05:15:40 PM PDT 24 Jul 12 05:23:29 PM PDT 24 1718657045 ps
T333 /workspace/coverage/default/38.sram_ctrl_smoke.594071417 Jul 12 05:15:57 PM PDT 24 Jul 12 05:17:12 PM PDT 24 808148948 ps
T334 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4070180934 Jul 12 05:13:05 PM PDT 24 Jul 12 05:31:17 PM PDT 24 2973185962 ps
T106 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1587713315 Jul 12 05:14:57 PM PDT 24 Jul 12 05:16:01 PM PDT 24 3121585648 ps
T16 /workspace/coverage/default/4.sram_ctrl_sec_cm.3423641463 Jul 12 05:12:50 PM PDT 24 Jul 12 05:12:55 PM PDT 24 176087081 ps
T335 /workspace/coverage/default/9.sram_ctrl_partial_access.1593066196 Jul 12 05:13:06 PM PDT 24 Jul 12 05:13:31 PM PDT 24 2414856545 ps
T336 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1767308738 Jul 12 05:12:50 PM PDT 24 Jul 12 05:12:58 PM PDT 24 92571425 ps
T337 /workspace/coverage/default/37.sram_ctrl_mem_walk.1665029116 Jul 12 05:15:57 PM PDT 24 Jul 12 05:16:08 PM PDT 24 1064186326 ps
T338 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3781392106 Jul 12 05:14:29 PM PDT 24 Jul 12 05:19:03 PM PDT 24 2749228341 ps
T339 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1480816908 Jul 12 05:13:30 PM PDT 24 Jul 12 05:18:36 PM PDT 24 36931441196 ps
T340 /workspace/coverage/default/40.sram_ctrl_multiple_keys.256627225 Jul 12 05:16:22 PM PDT 24 Jul 12 05:36:06 PM PDT 24 10377173560 ps
T341 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3536264591 Jul 12 05:16:28 PM PDT 24 Jul 12 05:34:44 PM PDT 24 3873324657 ps
T342 /workspace/coverage/default/49.sram_ctrl_mem_walk.1358601381 Jul 12 05:17:47 PM PDT 24 Jul 12 05:18:00 PM PDT 24 714197678 ps
T107 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3001257216 Jul 12 05:13:07 PM PDT 24 Jul 12 05:13:41 PM PDT 24 811074979 ps
T343 /workspace/coverage/default/38.sram_ctrl_max_throughput.3677904446 Jul 12 05:16:06 PM PDT 24 Jul 12 05:17:07 PM PDT 24 127844832 ps
T344 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2188107611 Jul 12 05:16:09 PM PDT 24 Jul 12 05:16:15 PM PDT 24 69566676 ps
T345 /workspace/coverage/default/49.sram_ctrl_regwen.3297498909 Jul 12 05:17:45 PM PDT 24 Jul 12 05:25:16 PM PDT 24 2812818618 ps
T346 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1034845446 Jul 12 05:14:57 PM PDT 24 Jul 12 05:19:42 PM PDT 24 1278863324 ps
T347 /workspace/coverage/default/31.sram_ctrl_stress_all.3879087264 Jul 12 05:15:07 PM PDT 24 Jul 12 06:57:22 PM PDT 24 74347031838 ps
T348 /workspace/coverage/default/27.sram_ctrl_regwen.1544290695 Jul 12 05:14:38 PM PDT 24 Jul 12 05:17:00 PM PDT 24 953499953 ps
T349 /workspace/coverage/default/37.sram_ctrl_alert_test.3845684675 Jul 12 05:15:57 PM PDT 24 Jul 12 05:15:58 PM PDT 24 50305078 ps
T350 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1734841820 Jul 12 05:14:56 PM PDT 24 Jul 12 05:20:14 PM PDT 24 19764255861 ps
T351 /workspace/coverage/default/23.sram_ctrl_lc_escalation.632583059 Jul 12 05:14:15 PM PDT 24 Jul 12 05:14:25 PM PDT 24 3986002700 ps
T352 /workspace/coverage/default/23.sram_ctrl_partial_access.845789971 Jul 12 05:14:08 PM PDT 24 Jul 12 05:14:16 PM PDT 24 380914672 ps
T108 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.828627763 Jul 12 05:13:26 PM PDT 24 Jul 12 05:15:25 PM PDT 24 7219379460 ps
T353 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3871742310 Jul 12 05:13:03 PM PDT 24 Jul 12 05:30:51 PM PDT 24 4423199338 ps
T354 /workspace/coverage/default/44.sram_ctrl_ram_cfg.3482494944 Jul 12 05:17:14 PM PDT 24 Jul 12 05:17:16 PM PDT 24 83481001 ps
T355 /workspace/coverage/default/43.sram_ctrl_mem_walk.2027012929 Jul 12 05:16:47 PM PDT 24 Jul 12 05:16:54 PM PDT 24 187809165 ps
T356 /workspace/coverage/default/32.sram_ctrl_executable.59091184 Jul 12 05:15:19 PM PDT 24 Jul 12 05:38:43 PM PDT 24 96315143164 ps
T357 /workspace/coverage/default/22.sram_ctrl_multiple_keys.1165386501 Jul 12 05:14:08 PM PDT 24 Jul 12 05:35:40 PM PDT 24 12922595537 ps
T358 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1641027436 Jul 12 05:14:23 PM PDT 24 Jul 12 05:18:28 PM PDT 24 9925639806 ps
T359 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1797130444 Jul 12 05:16:22 PM PDT 24 Jul 12 05:18:26 PM PDT 24 186481105 ps
T360 /workspace/coverage/default/0.sram_ctrl_max_throughput.733284418 Jul 12 05:12:33 PM PDT 24 Jul 12 05:13:40 PM PDT 24 122256202 ps
T361 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2678151914 Jul 12 05:16:16 PM PDT 24 Jul 12 05:16:22 PM PDT 24 336304187 ps
T362 /workspace/coverage/default/6.sram_ctrl_mem_walk.830474823 Jul 12 05:12:57 PM PDT 24 Jul 12 05:13:07 PM PDT 24 1025476391 ps
T363 /workspace/coverage/default/43.sram_ctrl_max_throughput.3586439187 Jul 12 05:16:56 PM PDT 24 Jul 12 05:18:04 PM PDT 24 536409897 ps
T364 /workspace/coverage/default/19.sram_ctrl_ram_cfg.2768758003 Jul 12 05:13:58 PM PDT 24 Jul 12 05:14:01 PM PDT 24 198241134 ps
T365 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2603629058 Jul 12 05:12:39 PM PDT 24 Jul 12 05:13:39 PM PDT 24 209612117 ps
T366 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2319352508 Jul 12 05:16:36 PM PDT 24 Jul 12 05:16:37 PM PDT 24 42183633 ps
T367 /workspace/coverage/default/1.sram_ctrl_partial_access.1125545988 Jul 12 05:12:34 PM PDT 24 Jul 12 05:12:43 PM PDT 24 263655144 ps
T368 /workspace/coverage/default/24.sram_ctrl_regwen.565987184 Jul 12 05:14:17 PM PDT 24 Jul 12 05:27:19 PM PDT 24 8723709678 ps
T369 /workspace/coverage/default/39.sram_ctrl_executable.2011207762 Jul 12 05:16:13 PM PDT 24 Jul 12 05:33:15 PM PDT 24 35468909091 ps
T370 /workspace/coverage/default/24.sram_ctrl_multiple_keys.4212093510 Jul 12 05:14:14 PM PDT 24 Jul 12 05:38:15 PM PDT 24 11920635425 ps
T371 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3649066501 Jul 12 05:13:25 PM PDT 24 Jul 12 05:13:29 PM PDT 24 580461489 ps
T372 /workspace/coverage/default/45.sram_ctrl_max_throughput.1273079132 Jul 12 05:17:04 PM PDT 24 Jul 12 05:19:33 PM PDT 24 142870176 ps
T373 /workspace/coverage/default/2.sram_ctrl_lc_escalation.3558829100 Jul 12 05:12:41 PM PDT 24 Jul 12 05:12:48 PM PDT 24 578089378 ps
T374 /workspace/coverage/default/11.sram_ctrl_ram_cfg.583392803 Jul 12 05:13:09 PM PDT 24 Jul 12 05:13:10 PM PDT 24 74760665 ps
T375 /workspace/coverage/default/43.sram_ctrl_regwen.1906947355 Jul 12 05:16:48 PM PDT 24 Jul 12 05:20:11 PM PDT 24 6467516051 ps
T376 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3198818407 Jul 12 05:16:49 PM PDT 24 Jul 12 05:23:19 PM PDT 24 15996999802 ps
T377 /workspace/coverage/default/4.sram_ctrl_ram_cfg.236355111 Jul 12 05:12:48 PM PDT 24 Jul 12 05:12:52 PM PDT 24 27363173 ps
T378 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3237069936 Jul 12 05:13:10 PM PDT 24 Jul 12 05:14:59 PM PDT 24 2322822849 ps
T379 /workspace/coverage/default/11.sram_ctrl_regwen.3985535829 Jul 12 05:13:14 PM PDT 24 Jul 12 05:32:55 PM PDT 24 62727236459 ps
T380 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3840227870 Jul 12 05:14:47 PM PDT 24 Jul 12 05:16:49 PM PDT 24 1151673516 ps
T381 /workspace/coverage/default/12.sram_ctrl_max_throughput.1984414606 Jul 12 05:13:11 PM PDT 24 Jul 12 05:13:23 PM PDT 24 593661400 ps
T382 /workspace/coverage/default/1.sram_ctrl_regwen.1437477895 Jul 12 05:12:35 PM PDT 24 Jul 12 05:31:30 PM PDT 24 11591177600 ps
T383 /workspace/coverage/default/31.sram_ctrl_bijection.3795223775 Jul 12 05:15:05 PM PDT 24 Jul 12 05:15:34 PM PDT 24 3562354862 ps
T384 /workspace/coverage/default/34.sram_ctrl_executable.3429316129 Jul 12 05:15:28 PM PDT 24 Jul 12 05:19:32 PM PDT 24 5461257331 ps
T385 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.357473717 Jul 12 05:15:38 PM PDT 24 Jul 12 05:22:47 PM PDT 24 1559887725 ps
T386 /workspace/coverage/default/29.sram_ctrl_ram_cfg.693006084 Jul 12 05:14:57 PM PDT 24 Jul 12 05:14:59 PM PDT 24 46369802 ps
T387 /workspace/coverage/default/22.sram_ctrl_ram_cfg.3833807559 Jul 12 05:14:12 PM PDT 24 Jul 12 05:14:14 PM PDT 24 50853254 ps
T388 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4290749947 Jul 12 05:12:50 PM PDT 24 Jul 12 05:15:56 PM PDT 24 3854799319 ps
T389 /workspace/coverage/default/28.sram_ctrl_bijection.1082868668 Jul 12 05:14:54 PM PDT 24 Jul 12 05:16:05 PM PDT 24 4729961122 ps
T390 /workspace/coverage/default/28.sram_ctrl_multiple_keys.2026647688 Jul 12 05:14:48 PM PDT 24 Jul 12 05:23:49 PM PDT 24 20841508217 ps
T391 /workspace/coverage/default/14.sram_ctrl_partial_access.2747328110 Jul 12 05:13:12 PM PDT 24 Jul 12 05:13:28 PM PDT 24 785005369 ps
T392 /workspace/coverage/default/39.sram_ctrl_partial_access.1649948454 Jul 12 05:16:12 PM PDT 24 Jul 12 05:17:30 PM PDT 24 205520607 ps
T393 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2174796695 Jul 12 05:13:10 PM PDT 24 Jul 12 05:19:00 PM PDT 24 53709009761 ps
T394 /workspace/coverage/default/2.sram_ctrl_max_throughput.4289531319 Jul 12 05:12:49 PM PDT 24 Jul 12 05:14:00 PM PDT 24 433285035 ps
T395 /workspace/coverage/default/48.sram_ctrl_stress_all.499506876 Jul 12 05:17:40 PM PDT 24 Jul 12 05:21:32 PM PDT 24 2451386165 ps
T396 /workspace/coverage/default/6.sram_ctrl_max_throughput.1774128586 Jul 12 05:12:56 PM PDT 24 Jul 12 05:13:41 PM PDT 24 280023147 ps
T397 /workspace/coverage/default/23.sram_ctrl_alert_test.2983501988 Jul 12 05:14:16 PM PDT 24 Jul 12 05:14:18 PM PDT 24 19724830 ps
T398 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1535735100 Jul 12 05:16:18 PM PDT 24 Jul 12 05:22:12 PM PDT 24 16089413653 ps
T399 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.442238308 Jul 12 05:16:08 PM PDT 24 Jul 12 05:16:51 PM PDT 24 109649630 ps
T400 /workspace/coverage/default/10.sram_ctrl_max_throughput.2450241478 Jul 12 05:13:04 PM PDT 24 Jul 12 05:13:49 PM PDT 24 379066110 ps
T401 /workspace/coverage/default/25.sram_ctrl_smoke.1362865677 Jul 12 05:14:26 PM PDT 24 Jul 12 05:15:16 PM PDT 24 102070529 ps
T402 /workspace/coverage/default/13.sram_ctrl_smoke.3364302163 Jul 12 05:13:11 PM PDT 24 Jul 12 05:13:21 PM PDT 24 150612560 ps
T403 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1527901798 Jul 12 05:16:07 PM PDT 24 Jul 12 05:43:11 PM PDT 24 7335814711 ps
T404 /workspace/coverage/default/11.sram_ctrl_multiple_keys.4287596809 Jul 12 05:13:13 PM PDT 24 Jul 12 05:29:11 PM PDT 24 15728827937 ps
T405 /workspace/coverage/default/39.sram_ctrl_mem_walk.641242527 Jul 12 05:16:12 PM PDT 24 Jul 12 05:16:25 PM PDT 24 2268276537 ps
T406 /workspace/coverage/default/47.sram_ctrl_alert_test.1186494432 Jul 12 05:17:31 PM PDT 24 Jul 12 05:17:33 PM PDT 24 11430146 ps
T109 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2274789758 Jul 12 05:12:46 PM PDT 24 Jul 12 05:13:18 PM PDT 24 8756098750 ps
T407 /workspace/coverage/default/9.sram_ctrl_alert_test.1239643359 Jul 12 05:13:13 PM PDT 24 Jul 12 05:13:15 PM PDT 24 20321037 ps
T408 /workspace/coverage/default/20.sram_ctrl_lc_escalation.2055961425 Jul 12 05:14:02 PM PDT 24 Jul 12 05:14:09 PM PDT 24 2325495062 ps
T409 /workspace/coverage/default/18.sram_ctrl_mem_walk.821002378 Jul 12 05:13:44 PM PDT 24 Jul 12 05:13:56 PM PDT 24 884230156 ps
T410 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.894514859 Jul 12 05:15:46 PM PDT 24 Jul 12 05:19:32 PM PDT 24 2344262586 ps
T411 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.817207357 Jul 12 05:17:00 PM PDT 24 Jul 12 05:17:07 PM PDT 24 200578198 ps
T412 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.4201067971 Jul 12 05:12:42 PM PDT 24 Jul 12 05:12:46 PM PDT 24 61216822 ps
T413 /workspace/coverage/default/6.sram_ctrl_stress_all.2057193596 Jul 12 05:12:56 PM PDT 24 Jul 12 05:16:56 PM PDT 24 3243667482 ps
T414 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1581005028 Jul 12 05:15:38 PM PDT 24 Jul 12 05:20:48 PM PDT 24 50763940472 ps
T415 /workspace/coverage/default/16.sram_ctrl_alert_test.3195187216 Jul 12 05:13:29 PM PDT 24 Jul 12 05:13:31 PM PDT 24 43516947 ps
T416 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1453461158 Jul 12 05:12:43 PM PDT 24 Jul 12 05:12:46 PM PDT 24 127590551 ps
T417 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1480801911 Jul 12 05:14:24 PM PDT 24 Jul 12 05:18:29 PM PDT 24 5068824313 ps
T418 /workspace/coverage/default/7.sram_ctrl_multiple_keys.3848055417 Jul 12 05:12:59 PM PDT 24 Jul 12 05:27:19 PM PDT 24 32316094146 ps
T419 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1490585921 Jul 12 05:12:55 PM PDT 24 Jul 12 05:13:19 PM PDT 24 786655404 ps
T420 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2172861105 Jul 12 05:15:25 PM PDT 24 Jul 12 05:18:39 PM PDT 24 7630897254 ps
T421 /workspace/coverage/default/41.sram_ctrl_regwen.3395368497 Jul 12 05:16:36 PM PDT 24 Jul 12 05:40:07 PM PDT 24 137506528878 ps
T422 /workspace/coverage/default/33.sram_ctrl_multiple_keys.1824691188 Jul 12 05:15:21 PM PDT 24 Jul 12 05:33:29 PM PDT 24 12779263246 ps
T423 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1530652567 Jul 12 05:12:34 PM PDT 24 Jul 12 05:12:41 PM PDT 24 335263574 ps
T424 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.622071532 Jul 12 05:16:49 PM PDT 24 Jul 12 05:27:11 PM PDT 24 3113622870 ps
T425 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.531702008 Jul 12 05:16:04 PM PDT 24 Jul 12 05:21:56 PM PDT 24 27102820156 ps
T426 /workspace/coverage/default/48.sram_ctrl_executable.738142043 Jul 12 05:17:42 PM PDT 24 Jul 12 05:31:09 PM PDT 24 39361631947 ps
T427 /workspace/coverage/default/40.sram_ctrl_max_throughput.3738428237 Jul 12 05:16:24 PM PDT 24 Jul 12 05:17:22 PM PDT 24 101977593 ps
T428 /workspace/coverage/default/34.sram_ctrl_partial_access.4269247065 Jul 12 05:15:25 PM PDT 24 Jul 12 05:17:24 PM PDT 24 203549376 ps
T429 /workspace/coverage/default/15.sram_ctrl_stress_all.1121935747 Jul 12 05:13:23 PM PDT 24 Jul 12 06:10:35 PM PDT 24 37025934556 ps
T430 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3499512866 Jul 12 05:13:59 PM PDT 24 Jul 12 05:14:05 PM PDT 24 119666932 ps
T431 /workspace/coverage/default/2.sram_ctrl_regwen.1996804652 Jul 12 05:12:41 PM PDT 24 Jul 12 05:24:26 PM PDT 24 13592838162 ps
T432 /workspace/coverage/default/9.sram_ctrl_multiple_keys.302770797 Jul 12 05:13:02 PM PDT 24 Jul 12 05:28:21 PM PDT 24 8573597892 ps
T433 /workspace/coverage/default/2.sram_ctrl_mem_walk.2563515859 Jul 12 05:12:41 PM PDT 24 Jul 12 05:12:48 PM PDT 24 1250551496 ps
T434 /workspace/coverage/default/6.sram_ctrl_multiple_keys.3316053995 Jul 12 05:12:47 PM PDT 24 Jul 12 05:27:25 PM PDT 24 52840962712 ps
T435 /workspace/coverage/default/24.sram_ctrl_partial_access.1500102264 Jul 12 05:14:15 PM PDT 24 Jul 12 05:14:31 PM PDT 24 2866841336 ps
T436 /workspace/coverage/default/49.sram_ctrl_stress_all.4019266364 Jul 12 05:17:53 PM PDT 24 Jul 12 06:12:04 PM PDT 24 39224684122 ps
T437 /workspace/coverage/default/0.sram_ctrl_executable.2094641380 Jul 12 05:12:34 PM PDT 24 Jul 12 05:15:02 PM PDT 24 1095002812 ps
T438 /workspace/coverage/default/49.sram_ctrl_executable.849200291 Jul 12 05:17:47 PM PDT 24 Jul 12 05:29:51 PM PDT 24 11141802318 ps
T439 /workspace/coverage/default/48.sram_ctrl_partial_access.1302258715 Jul 12 05:17:40 PM PDT 24 Jul 12 05:17:56 PM PDT 24 540686032 ps
T440 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2288657459 Jul 12 05:16:28 PM PDT 24 Jul 12 05:20:16 PM PDT 24 10074627241 ps
T441 /workspace/coverage/default/33.sram_ctrl_smoke.3298554997 Jul 12 05:15:19 PM PDT 24 Jul 12 05:16:25 PM PDT 24 1227835426 ps
T442 /workspace/coverage/default/6.sram_ctrl_regwen.3448732913 Jul 12 05:12:57 PM PDT 24 Jul 12 05:32:22 PM PDT 24 8062156266 ps
T443 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2926525470 Jul 12 05:13:15 PM PDT 24 Jul 12 05:14:45 PM PDT 24 716336726 ps
T444 /workspace/coverage/default/8.sram_ctrl_partial_access.2692476471 Jul 12 05:13:01 PM PDT 24 Jul 12 05:13:20 PM PDT 24 607888195 ps
T445 /workspace/coverage/default/13.sram_ctrl_mem_walk.3153052194 Jul 12 05:13:15 PM PDT 24 Jul 12 05:13:25 PM PDT 24 180461621 ps
T446 /workspace/coverage/default/1.sram_ctrl_lc_escalation.205055039 Jul 12 05:12:41 PM PDT 24 Jul 12 05:12:45 PM PDT 24 549848528 ps
T447 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3369160043 Jul 12 05:12:38 PM PDT 24 Jul 12 05:12:39 PM PDT 24 86510672 ps
T448 /workspace/coverage/default/5.sram_ctrl_stress_all.2804447443 Jul 12 05:12:56 PM PDT 24 Jul 12 05:40:09 PM PDT 24 59633059983 ps
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T450 /workspace/coverage/default/44.sram_ctrl_mem_walk.2042927413 Jul 12 05:17:10 PM PDT 24 Jul 12 05:17:23 PM PDT 24 2976984568 ps
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T453 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4192100774 Jul 12 05:14:23 PM PDT 24 Jul 12 05:16:48 PM PDT 24 954147246 ps
T454 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3142788132 Jul 12 05:12:51 PM PDT 24 Jul 12 05:15:23 PM PDT 24 12489552682 ps
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T456 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3437671583 Jul 12 05:17:39 PM PDT 24 Jul 12 05:19:03 PM PDT 24 1046917366 ps
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T458 /workspace/coverage/default/27.sram_ctrl_lc_escalation.531002804 Jul 12 05:14:38 PM PDT 24 Jul 12 05:14:48 PM PDT 24 2511800779 ps
T459 /workspace/coverage/default/23.sram_ctrl_multiple_keys.564051666 Jul 12 05:14:09 PM PDT 24 Jul 12 05:21:24 PM PDT 24 45676507860 ps
T460 /workspace/coverage/default/42.sram_ctrl_partial_access.3886898173 Jul 12 05:16:35 PM PDT 24 Jul 12 05:16:54 PM PDT 24 1953622126 ps
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T462 /workspace/coverage/default/11.sram_ctrl_max_throughput.3638616583 Jul 12 05:13:12 PM PDT 24 Jul 12 05:13:29 PM PDT 24 86681685 ps
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T466 /workspace/coverage/default/34.sram_ctrl_lc_escalation.2690469807 Jul 12 05:15:26 PM PDT 24 Jul 12 05:15:36 PM PDT 24 841399278 ps
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T471 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3904330024 Jul 12 05:13:11 PM PDT 24 Jul 12 05:13:20 PM PDT 24 721434690 ps
T472 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3758046361 Jul 12 05:15:21 PM PDT 24 Jul 12 05:15:27 PM PDT 24 214125204 ps
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T475 /workspace/coverage/default/35.sram_ctrl_lc_escalation.1515618170 Jul 12 05:15:43 PM PDT 24 Jul 12 05:15:46 PM PDT 24 163810456 ps
T476 /workspace/coverage/default/21.sram_ctrl_multiple_keys.825477603 Jul 12 05:14:16 PM PDT 24 Jul 12 05:37:50 PM PDT 24 59929079936 ps
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T488 /workspace/coverage/default/43.sram_ctrl_ram_cfg.3497910845 Jul 12 05:16:56 PM PDT 24 Jul 12 05:16:57 PM PDT 24 76880920 ps
T489 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3484342004 Jul 12 05:12:58 PM PDT 24 Jul 12 05:17:26 PM PDT 24 21601779768 ps
T490 /workspace/coverage/default/34.sram_ctrl_alert_test.1035831057 Jul 12 05:15:32 PM PDT 24 Jul 12 05:15:34 PM PDT 24 17391861 ps
T491 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.797210412 Jul 12 05:13:05 PM PDT 24 Jul 12 05:13:10 PM PDT 24 179891974 ps
T492 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3336497301 Jul 12 05:15:21 PM PDT 24 Jul 12 05:15:26 PM PDT 24 302129247 ps
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T494 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4121833421 Jul 12 05:50:14 PM PDT 24 Jul 12 05:50:26 PM PDT 24 281654362 ps
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T497 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2046699021 Jul 12 05:12:48 PM PDT 24 Jul 12 05:12:55 PM PDT 24 1372651296 ps
T498 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.333834813 Jul 12 05:14:24 PM PDT 24 Jul 12 05:14:30 PM PDT 24 636008521 ps
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T500 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3300965859 Jul 12 05:16:17 PM PDT 24 Jul 12 05:20:54 PM PDT 24 6852469973 ps
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T502 /workspace/coverage/default/33.sram_ctrl_ram_cfg.3804354064 Jul 12 05:15:23 PM PDT 24 Jul 12 05:15:24 PM PDT 24 80220370 ps
T503 /workspace/coverage/default/46.sram_ctrl_alert_test.3042996599 Jul 12 05:17:24 PM PDT 24 Jul 12 05:17:26 PM PDT 24 13208299 ps
T504 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2928887065 Jul 12 05:13:59 PM PDT 24 Jul 12 05:14:05 PM PDT 24 296494617 ps
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T506 /workspace/coverage/default/31.sram_ctrl_multiple_keys.3257074925 Jul 12 05:15:14 PM PDT 24 Jul 12 05:16:31 PM PDT 24 16791765483 ps
T507 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1482664374 Jul 12 05:14:46 PM PDT 24 Jul 12 05:15:09 PM PDT 24 453188199 ps
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T509 /workspace/coverage/default/21.sram_ctrl_ram_cfg.3596529965 Jul 12 05:14:15 PM PDT 24 Jul 12 05:14:16 PM PDT 24 42757639 ps
T510 /workspace/coverage/default/21.sram_ctrl_stress_all.2812420250 Jul 12 05:14:15 PM PDT 24 Jul 12 05:51:10 PM PDT 24 50499286292 ps
T511 /workspace/coverage/default/16.sram_ctrl_executable.570954456 Jul 12 05:13:33 PM PDT 24 Jul 12 05:20:17 PM PDT 24 17689027754 ps
T512 /workspace/coverage/default/13.sram_ctrl_partial_access.1784389065 Jul 12 05:13:23 PM PDT 24 Jul 12 05:13:26 PM PDT 24 176485900 ps
T513 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1270251621 Jul 12 05:17:26 PM PDT 24 Jul 12 05:19:43 PM PDT 24 571853521 ps
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T515 /workspace/coverage/default/38.sram_ctrl_partial_access.3840196861 Jul 12 05:16:08 PM PDT 24 Jul 12 05:16:27 PM PDT 24 3801981854 ps
T516 /workspace/coverage/default/19.sram_ctrl_max_throughput.1859719250 Jul 12 05:13:45 PM PDT 24 Jul 12 05:14:03 PM PDT 24 78922279 ps
T517 /workspace/coverage/default/29.sram_ctrl_bijection.347483118 Jul 12 05:14:59 PM PDT 24 Jul 12 05:15:39 PM PDT 24 10903771549 ps
T518 /workspace/coverage/default/6.sram_ctrl_executable.2439548575 Jul 12 05:12:57 PM PDT 24 Jul 12 05:28:48 PM PDT 24 37608671104 ps
T519 /workspace/coverage/default/47.sram_ctrl_partial_access.1873054857 Jul 12 05:17:33 PM PDT 24 Jul 12 05:17:42 PM PDT 24 418578562 ps
T520 /workspace/coverage/default/32.sram_ctrl_lc_escalation.4274299726 Jul 12 05:15:19 PM PDT 24 Jul 12 05:15:29 PM PDT 24 6797113124 ps
T521 /workspace/coverage/default/15.sram_ctrl_max_throughput.3463879565 Jul 12 05:13:23 PM PDT 24 Jul 12 05:13:29 PM PDT 24 226437139 ps
T522 /workspace/coverage/default/41.sram_ctrl_mem_walk.2391639628 Jul 12 05:16:38 PM PDT 24 Jul 12 05:16:45 PM PDT 24 2376426377 ps
T523 /workspace/coverage/default/2.sram_ctrl_ram_cfg.113492733 Jul 12 05:12:43 PM PDT 24 Jul 12 05:12:45 PM PDT 24 81867671 ps
T524 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1337714711 Jul 12 05:14:12 PM PDT 24 Jul 12 05:20:43 PM PDT 24 64189687599 ps
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T526 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.105695099 Jul 12 05:12:34 PM PDT 24 Jul 12 05:17:09 PM PDT 24 3669191721 ps
T527 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.146853785 Jul 12 05:14:14 PM PDT 24 Jul 12 05:21:31 PM PDT 24 600106194 ps
T528 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.292043172 Jul 12 05:12:46 PM PDT 24 Jul 12 05:16:07 PM PDT 24 12973731740 ps
T529 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1160385827 Jul 12 05:17:41 PM PDT 24 Jul 12 05:21:18 PM PDT 24 2222218491 ps
T530 /workspace/coverage/default/32.sram_ctrl_mem_walk.261527645 Jul 12 05:15:12 PM PDT 24 Jul 12 05:15:23 PM PDT 24 1835928148 ps
T531 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2509293303 Jul 12 05:14:09 PM PDT 24 Jul 12 05:14:13 PM PDT 24 563050593 ps
T532 /workspace/coverage/default/47.sram_ctrl_smoke.1328192232 Jul 12 05:17:20 PM PDT 24 Jul 12 05:17:39 PM PDT 24 812423658 ps
T533 /workspace/coverage/default/10.sram_ctrl_ram_cfg.2668137035 Jul 12 05:13:06 PM PDT 24 Jul 12 05:13:09 PM PDT 24 127088253 ps
T534 /workspace/coverage/default/2.sram_ctrl_bijection.435455322 Jul 12 05:12:41 PM PDT 24 Jul 12 05:13:09 PM PDT 24 2521609967 ps
T535 /workspace/coverage/default/44.sram_ctrl_max_throughput.2523563750 Jul 12 05:17:02 PM PDT 24 Jul 12 05:17:47 PM PDT 24 99420520 ps
T536 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2726107845 Jul 12 05:13:45 PM PDT 24 Jul 12 05:14:33 PM PDT 24 524860820 ps
T537 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.507478942 Jul 12 05:15:57 PM PDT 24 Jul 12 05:23:29 PM PDT 24 17686099265 ps
T538 /workspace/coverage/default/46.sram_ctrl_regwen.3654542988 Jul 12 05:17:28 PM PDT 24 Jul 12 05:38:47 PM PDT 24 64196010243 ps
T539 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.328663085 Jul 12 05:15:12 PM PDT 24 Jul 12 05:21:36 PM PDT 24 14670555866 ps
T540 /workspace/coverage/default/10.sram_ctrl_mem_walk.1927719200 Jul 12 05:13:06 PM PDT 24 Jul 12 05:13:19 PM PDT 24 3695954403 ps
T541 /workspace/coverage/default/13.sram_ctrl_bijection.1332499997 Jul 12 05:13:09 PM PDT 24 Jul 12 05:14:20 PM PDT 24 14944145736 ps
T542 /workspace/coverage/default/26.sram_ctrl_lc_escalation.31914551 Jul 12 05:14:30 PM PDT 24 Jul 12 05:14:38 PM PDT 24 635711966 ps
T543 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1365773708 Jul 12 05:13:02 PM PDT 24 Jul 12 05:13:07 PM PDT 24 104450065 ps
T544 /workspace/coverage/default/18.sram_ctrl_max_throughput.2574942367 Jul 12 05:13:44 PM PDT 24 Jul 12 05:13:46 PM PDT 24 40599800 ps
T545 /workspace/coverage/default/46.sram_ctrl_ram_cfg.1693504356 Jul 12 05:17:21 PM PDT 24 Jul 12 05:17:23 PM PDT 24 28149048 ps
T546 /workspace/coverage/default/26.sram_ctrl_regwen.3243124154 Jul 12 05:14:31 PM PDT 24 Jul 12 05:17:39 PM PDT 24 6916594497 ps
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