| T791 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.853078424 |
|
|
Jul 12 05:15:31 PM PDT 24 |
Jul 12 05:34:55 PM PDT 24 |
62081498288 ps |
| T792 |
/workspace/coverage/default/40.sram_ctrl_bijection.3212339726 |
|
|
Jul 12 05:16:19 PM PDT 24 |
Jul 12 05:16:46 PM PDT 24 |
408656928 ps |
| T793 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.167225003 |
|
|
Jul 12 05:13:09 PM PDT 24 |
Jul 12 05:13:11 PM PDT 24 |
279420141 ps |
| T794 |
/workspace/coverage/default/28.sram_ctrl_executable.727697571 |
|
|
Jul 12 05:14:49 PM PDT 24 |
Jul 12 05:40:42 PM PDT 24 |
46444290234 ps |
| T795 |
/workspace/coverage/default/46.sram_ctrl_executable.956684769 |
|
|
Jul 12 05:17:22 PM PDT 24 |
Jul 12 05:37:54 PM PDT 24 |
16105454172 ps |
| T796 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2194257005 |
|
|
Jul 12 05:16:17 PM PDT 24 |
Jul 12 05:17:42 PM PDT 24 |
793574099 ps |
| T797 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.965832845 |
|
|
Jul 12 05:14:49 PM PDT 24 |
Jul 12 05:18:21 PM PDT 24 |
2921569074 ps |
| T798 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.4125435079 |
|
|
Jul 12 05:15:39 PM PDT 24 |
Jul 12 05:15:47 PM PDT 24 |
4503145090 ps |
| T799 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3604213070 |
|
|
Jul 12 05:13:46 PM PDT 24 |
Jul 12 05:15:27 PM PDT 24 |
6552418077 ps |
| T800 |
/workspace/coverage/default/43.sram_ctrl_bijection.2752198261 |
|
|
Jul 12 05:16:54 PM PDT 24 |
Jul 12 05:17:36 PM PDT 24 |
9526975858 ps |
| T801 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3379647579 |
|
|
Jul 12 05:17:27 PM PDT 24 |
Jul 12 05:17:37 PM PDT 24 |
3209913926 ps |
| T802 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2876321508 |
|
|
Jul 12 05:12:58 PM PDT 24 |
Jul 12 05:30:18 PM PDT 24 |
13639151642 ps |
| T803 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2370539961 |
|
|
Jul 12 05:17:49 PM PDT 24 |
Jul 12 05:17:50 PM PDT 24 |
55997394 ps |
| T804 |
/workspace/coverage/default/19.sram_ctrl_partial_access.498142927 |
|
|
Jul 12 05:13:46 PM PDT 24 |
Jul 12 05:13:58 PM PDT 24 |
782804149 ps |
| T805 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1950446926 |
|
|
Jul 12 05:13:16 PM PDT 24 |
Jul 12 05:13:18 PM PDT 24 |
79595562 ps |
| T806 |
/workspace/coverage/default/45.sram_ctrl_alert_test.770224279 |
|
|
Jul 12 05:17:18 PM PDT 24 |
Jul 12 05:17:19 PM PDT 24 |
36999781 ps |
| T807 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.465272623 |
|
|
Jul 12 05:13:36 PM PDT 24 |
Jul 12 05:13:42 PM PDT 24 |
435468545 ps |
| T808 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1582927496 |
|
|
Jul 12 05:17:32 PM PDT 24 |
Jul 12 05:31:22 PM PDT 24 |
4691853575 ps |
| T809 |
/workspace/coverage/default/27.sram_ctrl_alert_test.2176236088 |
|
|
Jul 12 05:14:40 PM PDT 24 |
Jul 12 05:14:42 PM PDT 24 |
22105144 ps |
| T810 |
/workspace/coverage/default/8.sram_ctrl_bijection.2656507450 |
|
|
Jul 12 05:12:58 PM PDT 24 |
Jul 12 05:13:39 PM PDT 24 |
586954915 ps |
| T811 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1260508321 |
|
|
Jul 12 05:13:06 PM PDT 24 |
Jul 12 05:13:32 PM PDT 24 |
334362242 ps |
| T812 |
/workspace/coverage/default/32.sram_ctrl_partial_access.171522887 |
|
|
Jul 12 05:15:11 PM PDT 24 |
Jul 12 05:15:29 PM PDT 24 |
933855111 ps |
| T813 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1326162198 |
|
|
Jul 12 05:14:29 PM PDT 24 |
Jul 12 05:33:24 PM PDT 24 |
9516223571 ps |
| T814 |
/workspace/coverage/default/48.sram_ctrl_bijection.1598491761 |
|
|
Jul 12 05:17:34 PM PDT 24 |
Jul 12 05:18:16 PM PDT 24 |
4731966898 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_executable.3387350986 |
|
|
Jul 12 05:14:17 PM PDT 24 |
Jul 12 05:16:22 PM PDT 24 |
5752039786 ps |
| T816 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3885283716 |
|
|
Jul 12 05:13:18 PM PDT 24 |
Jul 12 05:16:19 PM PDT 24 |
8706363700 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3401901515 |
|
|
Jul 12 05:15:33 PM PDT 24 |
Jul 12 06:03:39 PM PDT 24 |
161906363094 ps |
| T818 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2115438233 |
|
|
Jul 12 05:13:00 PM PDT 24 |
Jul 12 05:54:07 PM PDT 24 |
7877799444 ps |
| T819 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2889428874 |
|
|
Jul 12 05:13:45 PM PDT 24 |
Jul 12 05:13:52 PM PDT 24 |
1316330636 ps |
| T820 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.295387811 |
|
|
Jul 12 05:15:58 PM PDT 24 |
Jul 12 05:19:32 PM PDT 24 |
2383710886 ps |
| T821 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3369770700 |
|
|
Jul 12 05:16:33 PM PDT 24 |
Jul 12 05:16:35 PM PDT 24 |
14976766 ps |
| T822 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1861976275 |
|
|
Jul 12 05:14:50 PM PDT 24 |
Jul 12 05:15:01 PM PDT 24 |
874574733 ps |
| T823 |
/workspace/coverage/default/30.sram_ctrl_partial_access.4077561498 |
|
|
Jul 12 05:14:59 PM PDT 24 |
Jul 12 05:15:06 PM PDT 24 |
157603917 ps |
| T824 |
/workspace/coverage/default/14.sram_ctrl_bijection.1456037471 |
|
|
Jul 12 05:13:25 PM PDT 24 |
Jul 12 05:14:44 PM PDT 24 |
22686812928 ps |
| T825 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.838980137 |
|
|
Jul 12 05:12:56 PM PDT 24 |
Jul 12 05:33:17 PM PDT 24 |
25306744654 ps |
| T826 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2029879942 |
|
|
Jul 12 05:14:12 PM PDT 24 |
Jul 12 05:15:55 PM PDT 24 |
155839864 ps |
| T827 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1592539648 |
|
|
Jul 12 05:17:11 PM PDT 24 |
Jul 12 05:17:12 PM PDT 24 |
88714081 ps |
| T828 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1816139451 |
|
|
Jul 12 05:12:58 PM PDT 24 |
Jul 12 05:13:08 PM PDT 24 |
205896883 ps |
| T829 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.4075287631 |
|
|
Jul 12 05:12:52 PM PDT 24 |
Jul 12 05:13:04 PM PDT 24 |
497093888 ps |
| T830 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1746629903 |
|
|
Jul 12 05:13:15 PM PDT 24 |
Jul 12 05:13:18 PM PDT 24 |
165208008 ps |
| T831 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1765786252 |
|
|
Jul 12 05:16:53 PM PDT 24 |
Jul 12 05:16:54 PM PDT 24 |
17602507 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1676217827 |
|
|
Jul 12 05:14:14 PM PDT 24 |
Jul 12 05:35:46 PM PDT 24 |
15568616311 ps |
| T833 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3453532935 |
|
|
Jul 12 05:17:36 PM PDT 24 |
Jul 12 05:22:52 PM PDT 24 |
13626785405 ps |
| T834 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4213803529 |
|
|
Jul 12 05:12:50 PM PDT 24 |
Jul 12 05:16:00 PM PDT 24 |
434062422 ps |
| T835 |
/workspace/coverage/default/35.sram_ctrl_bijection.2702097919 |
|
|
Jul 12 05:15:32 PM PDT 24 |
Jul 12 05:16:38 PM PDT 24 |
3837317969 ps |
| T836 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.381460581 |
|
|
Jul 12 05:13:35 PM PDT 24 |
Jul 12 05:19:16 PM PDT 24 |
1756232306 ps |
| T837 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2598188199 |
|
|
Jul 12 05:14:00 PM PDT 24 |
Jul 12 05:18:58 PM PDT 24 |
12693623644 ps |
| T838 |
/workspace/coverage/default/45.sram_ctrl_stress_all.4108066306 |
|
|
Jul 12 05:17:19 PM PDT 24 |
Jul 12 05:47:22 PM PDT 24 |
30348678516 ps |
| T839 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1023356664 |
|
|
Jul 12 05:14:15 PM PDT 24 |
Jul 12 05:14:22 PM PDT 24 |
3625745100 ps |
| T840 |
/workspace/coverage/default/29.sram_ctrl_stress_all.845071844 |
|
|
Jul 12 05:14:54 PM PDT 24 |
Jul 12 05:56:58 PM PDT 24 |
117982969251 ps |
| T841 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1962761618 |
|
|
Jul 12 05:15:38 PM PDT 24 |
Jul 12 05:15:39 PM PDT 24 |
63814889 ps |
| T842 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3951777681 |
|
|
Jul 12 05:15:20 PM PDT 24 |
Jul 12 05:15:22 PM PDT 24 |
76867953 ps |
| T843 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2023867412 |
|
|
Jul 12 05:15:30 PM PDT 24 |
Jul 12 05:15:32 PM PDT 24 |
30692100 ps |
| T844 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2999854779 |
|
|
Jul 12 05:13:05 PM PDT 24 |
Jul 12 05:30:46 PM PDT 24 |
71091390610 ps |
| T845 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.383235609 |
|
|
Jul 12 05:12:59 PM PDT 24 |
Jul 12 05:13:37 PM PDT 24 |
204928254 ps |
| T846 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3898927481 |
|
|
Jul 12 05:12:43 PM PDT 24 |
Jul 12 05:13:03 PM PDT 24 |
80981657 ps |
| T847 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2725340042 |
|
|
Jul 12 05:13:24 PM PDT 24 |
Jul 12 05:13:28 PM PDT 24 |
315924140 ps |
| T848 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1562660247 |
|
|
Jul 12 05:12:48 PM PDT 24 |
Jul 12 05:14:29 PM PDT 24 |
143475720 ps |
| T849 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1527674107 |
|
|
Jul 12 05:13:23 PM PDT 24 |
Jul 12 05:13:29 PM PDT 24 |
1158611008 ps |
| T850 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4287629848 |
|
|
Jul 12 05:14:09 PM PDT 24 |
Jul 12 05:14:13 PM PDT 24 |
259406985 ps |
| T851 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2545053676 |
|
|
Jul 12 05:15:46 PM PDT 24 |
Jul 12 05:15:50 PM PDT 24 |
42312398 ps |
| T852 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4048873548 |
|
|
Jul 12 05:13:15 PM PDT 24 |
Jul 12 05:13:21 PM PDT 24 |
2955176422 ps |
| T853 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3644780105 |
|
|
Jul 12 05:15:38 PM PDT 24 |
Jul 12 05:15:45 PM PDT 24 |
660136209 ps |
| T854 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3023227848 |
|
|
Jul 12 05:13:16 PM PDT 24 |
Jul 12 05:13:21 PM PDT 24 |
328856718 ps |
| T855 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2288891172 |
|
|
Jul 12 05:14:21 PM PDT 24 |
Jul 12 05:14:22 PM PDT 24 |
92093849 ps |
| T856 |
/workspace/coverage/default/27.sram_ctrl_smoke.2686352357 |
|
|
Jul 12 05:14:40 PM PDT 24 |
Jul 12 05:16:58 PM PDT 24 |
657360378 ps |
| T857 |
/workspace/coverage/default/30.sram_ctrl_regwen.1356413185 |
|
|
Jul 12 05:15:00 PM PDT 24 |
Jul 12 05:34:45 PM PDT 24 |
11171504831 ps |
| T858 |
/workspace/coverage/default/37.sram_ctrl_stress_all.522230979 |
|
|
Jul 12 05:15:58 PM PDT 24 |
Jul 12 06:22:53 PM PDT 24 |
45075851802 ps |
| T859 |
/workspace/coverage/default/35.sram_ctrl_executable.2121310089 |
|
|
Jul 12 05:15:40 PM PDT 24 |
Jul 12 05:24:43 PM PDT 24 |
1878136437 ps |
| T860 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3557647132 |
|
|
Jul 12 05:12:57 PM PDT 24 |
Jul 12 05:13:01 PM PDT 24 |
90881476 ps |
| T861 |
/workspace/coverage/default/20.sram_ctrl_bijection.2362613353 |
|
|
Jul 12 05:14:00 PM PDT 24 |
Jul 12 05:15:07 PM PDT 24 |
6992411225 ps |
| T862 |
/workspace/coverage/default/19.sram_ctrl_bijection.2227442279 |
|
|
Jul 12 05:13:47 PM PDT 24 |
Jul 12 05:15:00 PM PDT 24 |
10143039845 ps |
| T863 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3023496749 |
|
|
Jul 12 05:17:06 PM PDT 24 |
Jul 12 05:17:07 PM PDT 24 |
40956230 ps |
| T864 |
/workspace/coverage/default/30.sram_ctrl_executable.3502469996 |
|
|
Jul 12 05:14:56 PM PDT 24 |
Jul 12 05:24:12 PM PDT 24 |
11725478514 ps |
| T865 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.462757522 |
|
|
Jul 12 05:12:55 PM PDT 24 |
Jul 12 05:12:59 PM PDT 24 |
64078800 ps |
| T866 |
/workspace/coverage/default/44.sram_ctrl_bijection.2891333593 |
|
|
Jul 12 05:16:58 PM PDT 24 |
Jul 12 05:17:16 PM PDT 24 |
949651071 ps |
| T867 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2924929166 |
|
|
Jul 12 05:14:02 PM PDT 24 |
Jul 12 06:14:40 PM PDT 24 |
12323491349 ps |
| T868 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2035282876 |
|
|
Jul 12 05:13:06 PM PDT 24 |
Jul 12 05:13:29 PM PDT 24 |
688714808 ps |
| T869 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2244101952 |
|
|
Jul 12 05:14:30 PM PDT 24 |
Jul 12 05:18:38 PM PDT 24 |
1151032644 ps |
| T870 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1593142747 |
|
|
Jul 12 05:13:06 PM PDT 24 |
Jul 12 05:33:23 PM PDT 24 |
25628650008 ps |
| T871 |
/workspace/coverage/default/3.sram_ctrl_smoke.2998416057 |
|
|
Jul 12 05:12:41 PM PDT 24 |
Jul 12 05:13:42 PM PDT 24 |
120704302 ps |
| T113 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2082612546 |
|
|
Jul 12 05:14:29 PM PDT 24 |
Jul 12 05:14:45 PM PDT 24 |
1732058806 ps |
| T872 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3164120145 |
|
|
Jul 12 05:13:58 PM PDT 24 |
Jul 12 05:15:05 PM PDT 24 |
1517446001 ps |
| T873 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1888563368 |
|
|
Jul 12 05:15:06 PM PDT 24 |
Jul 12 05:17:02 PM PDT 24 |
524443144 ps |
| T874 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.541306960 |
|
|
Jul 12 05:17:44 PM PDT 24 |
Jul 12 05:22:38 PM PDT 24 |
3977961371 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3649281181 |
|
|
Jul 12 05:14:59 PM PDT 24 |
Jul 12 05:15:13 PM PDT 24 |
266483710 ps |
| T876 |
/workspace/coverage/default/12.sram_ctrl_executable.876646400 |
|
|
Jul 12 05:13:10 PM PDT 24 |
Jul 12 05:20:12 PM PDT 24 |
15853222105 ps |
| T877 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.740400137 |
|
|
Jul 12 05:13:13 PM PDT 24 |
Jul 12 05:13:19 PM PDT 24 |
172422102 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2378402731 |
|
|
Jul 12 05:14:32 PM PDT 24 |
Jul 12 05:14:44 PM PDT 24 |
2579052980 ps |
| T879 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1409523332 |
|
|
Jul 12 05:17:11 PM PDT 24 |
Jul 12 05:21:34 PM PDT 24 |
27537761784 ps |
| T880 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2201522379 |
|
|
Jul 12 05:13:34 PM PDT 24 |
Jul 12 05:17:58 PM PDT 24 |
3113793403 ps |
| T881 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1622337688 |
|
|
Jul 12 05:12:56 PM PDT 24 |
Jul 12 05:13:03 PM PDT 24 |
269561544 ps |
| T28 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3627894757 |
|
|
Jul 12 05:12:45 PM PDT 24 |
Jul 12 05:12:49 PM PDT 24 |
677721763 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_smoke.2489438147 |
|
|
Jul 12 05:15:35 PM PDT 24 |
Jul 12 05:15:50 PM PDT 24 |
235103242 ps |
| T883 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.683243595 |
|
|
Jul 12 05:13:22 PM PDT 24 |
Jul 12 05:13:23 PM PDT 24 |
31743855 ps |
| T884 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3261635530 |
|
|
Jul 12 05:16:48 PM PDT 24 |
Jul 12 05:17:25 PM PDT 24 |
2297956671 ps |
| T885 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2086031859 |
|
|
Jul 12 05:15:58 PM PDT 24 |
Jul 12 05:36:13 PM PDT 24 |
3387679783 ps |
| T886 |
/workspace/coverage/default/17.sram_ctrl_regwen.974384402 |
|
|
Jul 12 05:13:43 PM PDT 24 |
Jul 12 05:16:26 PM PDT 24 |
3999433744 ps |
| T887 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3434695506 |
|
|
Jul 12 05:15:30 PM PDT 24 |
Jul 12 05:15:32 PM PDT 24 |
86063201 ps |
| T888 |
/workspace/coverage/default/24.sram_ctrl_bijection.675013378 |
|
|
Jul 12 05:14:16 PM PDT 24 |
Jul 12 05:14:38 PM PDT 24 |
3689629845 ps |
| T889 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1568713282 |
|
|
Jul 12 05:14:33 PM PDT 24 |
Jul 12 05:14:43 PM PDT 24 |
68113965 ps |
| T890 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3375051995 |
|
|
Jul 12 05:15:47 PM PDT 24 |
Jul 12 05:38:49 PM PDT 24 |
15152702320 ps |
| T891 |
/workspace/coverage/default/33.sram_ctrl_bijection.2853297537 |
|
|
Jul 12 05:15:22 PM PDT 24 |
Jul 12 05:16:05 PM PDT 24 |
8270938784 ps |
| T892 |
/workspace/coverage/default/36.sram_ctrl_partial_access.722737869 |
|
|
Jul 12 05:15:40 PM PDT 24 |
Jul 12 05:16:06 PM PDT 24 |
456748431 ps |
| T893 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1956633453 |
|
|
Jul 12 05:16:19 PM PDT 24 |
Jul 12 05:16:25 PM PDT 24 |
662425223 ps |
| T894 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1185772466 |
|
|
Jul 12 05:17:25 PM PDT 24 |
Jul 12 05:17:37 PM PDT 24 |
265661099 ps |
| T895 |
/workspace/coverage/default/10.sram_ctrl_bijection.3504795979 |
|
|
Jul 12 05:13:05 PM PDT 24 |
Jul 12 05:13:56 PM PDT 24 |
720497128 ps |
| T896 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2453426401 |
|
|
Jul 12 05:14:56 PM PDT 24 |
Jul 12 05:16:13 PM PDT 24 |
212951438 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_partial_access.4240098563 |
|
|
Jul 12 05:16:28 PM PDT 24 |
Jul 12 05:16:34 PM PDT 24 |
754375668 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.245940751 |
|
|
Jul 12 05:14:30 PM PDT 24 |
Jul 12 05:19:08 PM PDT 24 |
13490999249 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2061113000 |
|
|
Jul 12 05:14:56 PM PDT 24 |
Jul 12 05:14:58 PM PDT 24 |
251167038 ps |
| T900 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2777755559 |
|
|
Jul 12 05:15:07 PM PDT 24 |
Jul 12 05:15:09 PM PDT 24 |
30919979 ps |
| T901 |
/workspace/coverage/default/25.sram_ctrl_alert_test.243324722 |
|
|
Jul 12 05:14:23 PM PDT 24 |
Jul 12 05:14:25 PM PDT 24 |
75940145 ps |
| T902 |
/workspace/coverage/default/39.sram_ctrl_regwen.2402243258 |
|
|
Jul 12 05:16:13 PM PDT 24 |
Jul 12 05:19:08 PM PDT 24 |
487379106 ps |
| T903 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2065693205 |
|
|
Jul 12 05:14:34 PM PDT 24 |
Jul 12 05:14:41 PM PDT 24 |
193223253 ps |
| T904 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3424814597 |
|
|
Jul 12 05:13:59 PM PDT 24 |
Jul 12 05:14:01 PM PDT 24 |
14563068 ps |
| T905 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.175899177 |
|
|
Jul 12 05:12:50 PM PDT 24 |
Jul 12 05:13:21 PM PDT 24 |
371838797 ps |
| T906 |
/workspace/coverage/default/37.sram_ctrl_smoke.3581793001 |
|
|
Jul 12 05:15:46 PM PDT 24 |
Jul 12 05:15:57 PM PDT 24 |
615017712 ps |
| T907 |
/workspace/coverage/default/16.sram_ctrl_stress_all.600296710 |
|
|
Jul 12 05:13:30 PM PDT 24 |
Jul 12 05:36:05 PM PDT 24 |
57695137819 ps |
| T908 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1827383635 |
|
|
Jul 12 05:13:15 PM PDT 24 |
Jul 12 05:47:34 PM PDT 24 |
38463128217 ps |
| T909 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1751836100 |
|
|
Jul 12 05:15:32 PM PDT 24 |
Jul 12 05:15:41 PM PDT 24 |
127173833 ps |
| T910 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2092400779 |
|
|
Jul 12 05:16:12 PM PDT 24 |
Jul 12 05:24:44 PM PDT 24 |
78847686780 ps |
| T911 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2623711607 |
|
|
Jul 12 05:13:01 PM PDT 24 |
Jul 12 05:13:04 PM PDT 24 |
49907113 ps |
| T912 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2089050275 |
|
|
Jul 12 05:13:16 PM PDT 24 |
Jul 12 05:26:43 PM PDT 24 |
2900400046 ps |
| T913 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1652025922 |
|
|
Jul 12 05:15:05 PM PDT 24 |
Jul 12 05:33:51 PM PDT 24 |
21248296035 ps |
| T914 |
/workspace/coverage/default/4.sram_ctrl_smoke.1576702654 |
|
|
Jul 12 05:12:51 PM PDT 24 |
Jul 12 05:13:05 PM PDT 24 |
678927293 ps |
| T915 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2203869375 |
|
|
Jul 12 05:14:40 PM PDT 24 |
Jul 12 06:11:20 PM PDT 24 |
271001340359 ps |
| T916 |
/workspace/coverage/default/40.sram_ctrl_regwen.1903546924 |
|
|
Jul 12 05:16:20 PM PDT 24 |
Jul 12 05:18:24 PM PDT 24 |
1946233950 ps |
| T917 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3704912898 |
|
|
Jul 12 05:14:16 PM PDT 24 |
Jul 12 05:14:23 PM PDT 24 |
236698017 ps |
| T918 |
/workspace/coverage/default/18.sram_ctrl_executable.2160316694 |
|
|
Jul 12 05:13:46 PM PDT 24 |
Jul 12 05:42:57 PM PDT 24 |
21122958967 ps |
| T919 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.167706956 |
|
|
Jul 12 05:16:12 PM PDT 24 |
Jul 12 05:16:18 PM PDT 24 |
257487510 ps |
| T920 |
/workspace/coverage/default/7.sram_ctrl_regwen.682456460 |
|
|
Jul 12 05:12:58 PM PDT 24 |
Jul 12 05:35:53 PM PDT 24 |
11707714061 ps |
| T921 |
/workspace/coverage/default/46.sram_ctrl_smoke.2112597516 |
|
|
Jul 12 05:17:23 PM PDT 24 |
Jul 12 05:19:16 PM PDT 24 |
571484447 ps |
| T922 |
/workspace/coverage/default/26.sram_ctrl_stress_all.3756227792 |
|
|
Jul 12 05:14:31 PM PDT 24 |
Jul 12 05:23:27 PM PDT 24 |
2967219623 ps |
| T923 |
/workspace/coverage/default/29.sram_ctrl_alert_test.621413051 |
|
|
Jul 12 05:14:59 PM PDT 24 |
Jul 12 05:15:00 PM PDT 24 |
20494707 ps |
| T924 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3077128470 |
|
|
Jul 12 05:14:39 PM PDT 24 |
Jul 12 05:14:46 PM PDT 24 |
217806991 ps |
| T925 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.810412218 |
|
|
Jul 12 05:14:10 PM PDT 24 |
Jul 12 05:14:18 PM PDT 24 |
66530346 ps |
| T926 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2563328108 |
|
|
Jul 12 05:14:13 PM PDT 24 |
Jul 12 05:14:14 PM PDT 24 |
11828057 ps |
| T927 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.233948191 |
|
|
Jul 12 05:12:44 PM PDT 24 |
Jul 12 05:20:57 PM PDT 24 |
84291362546 ps |
| T928 |
/workspace/coverage/default/23.sram_ctrl_smoke.1137829493 |
|
|
Jul 12 05:14:12 PM PDT 24 |
Jul 12 05:16:00 PM PDT 24 |
2914037344 ps |
| T929 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4011750910 |
|
|
Jul 12 06:05:44 PM PDT 24 |
Jul 12 06:05:48 PM PDT 24 |
142142683 ps |
| T64 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2196469676 |
|
|
Jul 12 06:06:27 PM PDT 24 |
Jul 12 06:06:28 PM PDT 24 |
37147948 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1743486600 |
|
|
Jul 12 06:05:56 PM PDT 24 |
Jul 12 06:05:57 PM PDT 24 |
159836478 ps |
| T66 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2270626601 |
|
|
Jul 12 06:06:22 PM PDT 24 |
Jul 12 06:06:24 PM PDT 24 |
34149703 ps |
| T96 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2584549704 |
|
|
Jul 12 06:05:59 PM PDT 24 |
Jul 12 06:06:01 PM PDT 24 |
81527884 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1085641893 |
|
|
Jul 12 06:06:09 PM PDT 24 |
Jul 12 06:06:10 PM PDT 24 |
14148986 ps |
| T59 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2896361690 |
|
|
Jul 12 06:06:09 PM PDT 24 |
Jul 12 06:06:12 PM PDT 24 |
547676883 ps |
| T77 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1141130342 |
|
|
Jul 12 06:06:34 PM PDT 24 |
Jul 12 06:06:36 PM PDT 24 |
39699600 ps |
| T60 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4272982583 |
|
|
Jul 12 06:06:36 PM PDT 24 |
Jul 12 06:06:42 PM PDT 24 |
870935549 ps |
| T105 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3693867070 |
|
|
Jul 12 06:05:52 PM PDT 24 |
Jul 12 06:05:54 PM PDT 24 |
16405113 ps |
| T78 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3866879065 |
|
|
Jul 12 06:06:36 PM PDT 24 |
Jul 12 06:06:44 PM PDT 24 |
398173433 ps |
| T930 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2020272456 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:58 PM PDT 24 |
144655990 ps |
| T79 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.794960739 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:38 PM PDT 24 |
19105897 ps |
| T931 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2388929801 |
|
|
Jul 12 06:05:46 PM PDT 24 |
Jul 12 06:05:47 PM PDT 24 |
68570407 ps |
| T932 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.671858282 |
|
|
Jul 12 06:06:00 PM PDT 24 |
Jul 12 06:06:02 PM PDT 24 |
70749755 ps |
| T61 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1403689335 |
|
|
Jul 12 06:05:51 PM PDT 24 |
Jul 12 06:05:54 PM PDT 24 |
524488642 ps |
| T933 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.334665904 |
|
|
Jul 12 06:06:08 PM PDT 24 |
Jul 12 06:06:14 PM PDT 24 |
1549334813 ps |
| T80 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4149918996 |
|
|
Jul 12 06:06:31 PM PDT 24 |
Jul 12 06:06:36 PM PDT 24 |
577292305 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2612477156 |
|
|
Jul 12 06:06:15 PM PDT 24 |
Jul 12 06:06:16 PM PDT 24 |
26221444 ps |
| T934 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2668398946 |
|
|
Jul 12 06:06:36 PM PDT 24 |
Jul 12 06:06:43 PM PDT 24 |
80232158 ps |
| T99 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1510819183 |
|
|
Jul 12 06:05:51 PM PDT 24 |
Jul 12 06:05:52 PM PDT 24 |
27663976 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4004149534 |
|
|
Jul 12 06:06:30 PM PDT 24 |
Jul 12 06:06:33 PM PDT 24 |
134075212 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.185649994 |
|
|
Jul 12 06:06:12 PM PDT 24 |
Jul 12 06:06:13 PM PDT 24 |
11894872 ps |
| T935 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2605709063 |
|
|
Jul 12 06:05:57 PM PDT 24 |
Jul 12 06:06:00 PM PDT 24 |
82118405 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1785377311 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:57 PM PDT 24 |
1587701037 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3582712716 |
|
|
Jul 12 06:05:52 PM PDT 24 |
Jul 12 06:05:55 PM PDT 24 |
78428884 ps |
| T82 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1446185416 |
|
|
Jul 12 06:06:19 PM PDT 24 |
Jul 12 06:06:23 PM PDT 24 |
484048450 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3320242520 |
|
|
Jul 12 06:06:02 PM PDT 24 |
Jul 12 06:06:04 PM PDT 24 |
248101948 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4034724822 |
|
|
Jul 12 06:06:15 PM PDT 24 |
Jul 12 06:06:18 PM PDT 24 |
203907187 ps |
| T937 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.402704783 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:55 PM PDT 24 |
140061583 ps |
| T938 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3013815043 |
|
|
Jul 12 06:06:37 PM PDT 24 |
Jul 12 06:06:43 PM PDT 24 |
15048740 ps |
| T131 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.880365393 |
|
|
Jul 12 06:05:54 PM PDT 24 |
Jul 12 06:05:58 PM PDT 24 |
98923664 ps |
| T939 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.469762683 |
|
|
Jul 12 06:05:52 PM PDT 24 |
Jul 12 06:05:55 PM PDT 24 |
161210224 ps |
| T85 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3635591829 |
|
|
Jul 12 06:06:23 PM PDT 24 |
Jul 12 06:06:25 PM PDT 24 |
32602295 ps |
| T940 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1108143873 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:41 PM PDT 24 |
139034268 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1855124196 |
|
|
Jul 12 06:06:21 PM PDT 24 |
Jul 12 06:06:23 PM PDT 24 |
262311623 ps |
| T942 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3528450975 |
|
|
Jul 12 06:06:23 PM PDT 24 |
Jul 12 06:06:27 PM PDT 24 |
462188463 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1949099159 |
|
|
Jul 12 06:05:52 PM PDT 24 |
Jul 12 06:05:54 PM PDT 24 |
189270067 ps |
| T943 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.188076294 |
|
|
Jul 12 06:06:42 PM PDT 24 |
Jul 12 06:06:51 PM PDT 24 |
20469597 ps |
| T944 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3426850395 |
|
|
Jul 12 06:06:31 PM PDT 24 |
Jul 12 06:06:34 PM PDT 24 |
110908034 ps |
| T945 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1338538357 |
|
|
Jul 12 06:06:27 PM PDT 24 |
Jul 12 06:06:28 PM PDT 24 |
29271008 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.77370890 |
|
|
Jul 12 06:06:51 PM PDT 24 |
Jul 12 06:07:08 PM PDT 24 |
32746364 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3064033315 |
|
|
Jul 12 06:05:49 PM PDT 24 |
Jul 12 06:05:51 PM PDT 24 |
22995518 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1165452824 |
|
|
Jul 12 06:05:59 PM PDT 24 |
Jul 12 06:06:01 PM PDT 24 |
105678838 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.806222195 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:41 PM PDT 24 |
1973899728 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3833066382 |
|
|
Jul 12 06:06:39 PM PDT 24 |
Jul 12 06:06:47 PM PDT 24 |
193859394 ps |
| T950 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3807295295 |
|
|
Jul 12 06:06:09 PM PDT 24 |
Jul 12 06:06:11 PM PDT 24 |
35628083 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1726235348 |
|
|
Jul 12 06:06:14 PM PDT 24 |
Jul 12 06:06:16 PM PDT 24 |
83156316 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.783496013 |
|
|
Jul 12 06:06:04 PM PDT 24 |
Jul 12 06:06:06 PM PDT 24 |
230668766 ps |
| T92 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2978960685 |
|
|
Jul 12 06:05:54 PM PDT 24 |
Jul 12 06:05:59 PM PDT 24 |
2277482253 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2591144893 |
|
|
Jul 12 06:05:52 PM PDT 24 |
Jul 12 06:05:55 PM PDT 24 |
14305517 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.309674569 |
|
|
Jul 12 06:05:55 PM PDT 24 |
Jul 12 06:05:57 PM PDT 24 |
45732297 ps |
| T93 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3332609100 |
|
|
Jul 12 06:05:45 PM PDT 24 |
Jul 12 06:05:48 PM PDT 24 |
2023961134 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3604180000 |
|
|
Jul 12 06:06:38 PM PDT 24 |
Jul 12 06:06:46 PM PDT 24 |
30635131 ps |
| T956 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2098936015 |
|
|
Jul 12 06:06:37 PM PDT 24 |
Jul 12 06:06:46 PM PDT 24 |
67669396 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1801272513 |
|
|
Jul 12 06:06:00 PM PDT 24 |
Jul 12 06:06:02 PM PDT 24 |
75979641 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1115988283 |
|
|
Jul 12 06:06:36 PM PDT 24 |
Jul 12 06:06:41 PM PDT 24 |
427111449 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2379685170 |
|
|
Jul 12 06:05:59 PM PDT 24 |
Jul 12 06:06:01 PM PDT 24 |
113398336 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3626013892 |
|
|
Jul 12 06:06:39 PM PDT 24 |
Jul 12 06:06:48 PM PDT 24 |
1580524923 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.235786590 |
|
|
Jul 12 06:05:49 PM PDT 24 |
Jul 12 06:05:51 PM PDT 24 |
100110685 ps |
| T961 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3916395967 |
|
|
Jul 12 06:06:20 PM PDT 24 |
Jul 12 06:06:22 PM PDT 24 |
205735010 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.225359969 |
|
|
Jul 12 06:06:14 PM PDT 24 |
Jul 12 06:06:16 PM PDT 24 |
28683279 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2060052368 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:57 PM PDT 24 |
130080076 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1001029539 |
|
|
Jul 12 06:06:30 PM PDT 24 |
Jul 12 06:06:31 PM PDT 24 |
153521222 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3780488138 |
|
|
Jul 12 06:06:21 PM PDT 24 |
Jul 12 06:06:24 PM PDT 24 |
1601673254 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2295593408 |
|
|
Jul 12 06:06:01 PM PDT 24 |
Jul 12 06:06:03 PM PDT 24 |
21760896 ps |
| T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.268078048 |
|
|
Jul 12 06:06:30 PM PDT 24 |
Jul 12 06:06:36 PM PDT 24 |
483340355 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.44694509 |
|
|
Jul 12 06:06:12 PM PDT 24 |
Jul 12 06:06:13 PM PDT 24 |
23900651 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3309180133 |
|
|
Jul 12 06:06:22 PM PDT 24 |
Jul 12 06:06:24 PM PDT 24 |
935045664 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3016687096 |
|
|
Jul 12 06:06:36 PM PDT 24 |
Jul 12 06:06:40 PM PDT 24 |
17820842 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1550662861 |
|
|
Jul 12 06:06:30 PM PDT 24 |
Jul 12 06:06:32 PM PDT 24 |
15872457 ps |
| T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.981833404 |
|
|
Jul 12 06:06:32 PM PDT 24 |
Jul 12 06:06:37 PM PDT 24 |
671097419 ps |
| T972 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1889912086 |
|
|
Jul 12 06:06:24 PM PDT 24 |
Jul 12 06:06:28 PM PDT 24 |
174538476 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1024956699 |
|
|
Jul 12 06:05:48 PM PDT 24 |
Jul 12 06:05:51 PM PDT 24 |
184896867 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1358139449 |
|
|
Jul 12 06:05:44 PM PDT 24 |
Jul 12 06:05:45 PM PDT 24 |
15499750 ps |
| T974 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3065860841 |
|
|
Jul 12 06:06:37 PM PDT 24 |
Jul 12 06:06:44 PM PDT 24 |
28322511 ps |
| T975 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1895677871 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:40 PM PDT 24 |
355538072 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3656752201 |
|
|
Jul 12 06:05:54 PM PDT 24 |
Jul 12 06:05:57 PM PDT 24 |
35732568 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4189998767 |
|
|
Jul 12 06:06:22 PM PDT 24 |
Jul 12 06:06:26 PM PDT 24 |
388152120 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3971868014 |
|
|
Jul 12 06:06:29 PM PDT 24 |
Jul 12 06:06:31 PM PDT 24 |
20585381 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.903732255 |
|
|
Jul 12 06:06:26 PM PDT 24 |
Jul 12 06:06:29 PM PDT 24 |
372809995 ps |
| T980 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1229317627 |
|
|
Jul 12 06:06:33 PM PDT 24 |
Jul 12 06:06:35 PM PDT 24 |
12004083 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2631333795 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:56 PM PDT 24 |
29740731 ps |
| T982 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3273930451 |
|
|
Jul 12 06:06:14 PM PDT 24 |
Jul 12 06:06:15 PM PDT 24 |
35623080 ps |
| T983 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1090979463 |
|
|
Jul 12 06:06:24 PM PDT 24 |
Jul 12 06:06:26 PM PDT 24 |
55951222 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2013609067 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:57 PM PDT 24 |
1071411392 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3663863878 |
|
|
Jul 12 06:05:52 PM PDT 24 |
Jul 12 06:05:53 PM PDT 24 |
22418158 ps |
| T129 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2308406004 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:40 PM PDT 24 |
180846153 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2040539739 |
|
|
Jul 12 06:06:03 PM PDT 24 |
Jul 12 06:06:04 PM PDT 24 |
13515493 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3458101228 |
|
|
Jul 12 06:06:19 PM PDT 24 |
Jul 12 06:06:20 PM PDT 24 |
16286166 ps |
| T988 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.693355382 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:39 PM PDT 24 |
119770760 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1113125231 |
|
|
Jul 12 06:06:21 PM PDT 24 |
Jul 12 06:06:23 PM PDT 24 |
29157524 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2736110396 |
|
|
Jul 12 06:06:37 PM PDT 24 |
Jul 12 06:06:44 PM PDT 24 |
153748013 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4228715255 |
|
|
Jul 12 06:06:24 PM PDT 24 |
Jul 12 06:06:26 PM PDT 24 |
27167520 ps |
| T992 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3342711692 |
|
|
Jul 12 06:06:35 PM PDT 24 |
Jul 12 06:06:39 PM PDT 24 |
28131611 ps |
| T993 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1827637990 |
|
|
Jul 12 06:06:06 PM PDT 24 |
Jul 12 06:06:10 PM PDT 24 |
382134121 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1086177555 |
|
|
Jul 12 06:06:14 PM PDT 24 |
Jul 12 06:06:19 PM PDT 24 |
138908804 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.770416437 |
|
|
Jul 12 06:06:03 PM PDT 24 |
Jul 12 06:06:08 PM PDT 24 |
2599332246 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1988727646 |
|
|
Jul 12 06:06:38 PM PDT 24 |
Jul 12 06:06:47 PM PDT 24 |
265600923 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3118410919 |
|
|
Jul 12 06:06:38 PM PDT 24 |
Jul 12 06:06:44 PM PDT 24 |
20036381 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3297976981 |
|
|
Jul 12 06:06:01 PM PDT 24 |
Jul 12 06:06:04 PM PDT 24 |
44235087 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4062932382 |
|
|
Jul 12 06:06:09 PM PDT 24 |
Jul 12 06:06:10 PM PDT 24 |
66950191 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3187176526 |
|
|
Jul 12 06:05:45 PM PDT 24 |
Jul 12 06:05:47 PM PDT 24 |
30941118 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2177162536 |
|
|
Jul 12 06:06:29 PM PDT 24 |
Jul 12 06:06:31 PM PDT 24 |
101288474 ps |
| T1002 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2945511066 |
|
|
Jul 12 06:06:36 PM PDT 24 |
Jul 12 06:06:41 PM PDT 24 |
25477238 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4027132663 |
|
|
Jul 12 06:06:08 PM PDT 24 |
Jul 12 06:06:11 PM PDT 24 |
76868915 ps |
| T135 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3802347868 |
|
|
Jul 12 06:06:26 PM PDT 24 |
Jul 12 06:06:28 PM PDT 24 |
1452097327 ps |
| T1004 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1860058546 |
|
|
Jul 12 06:06:23 PM PDT 24 |
Jul 12 06:06:24 PM PDT 24 |
13102474 ps |
| T1005 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1072065179 |
|
|
Jul 12 06:05:46 PM PDT 24 |
Jul 12 06:05:47 PM PDT 24 |
30723138 ps |
| T1006 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4007989833 |
|
|
Jul 12 06:05:53 PM PDT 24 |
Jul 12 06:05:55 PM PDT 24 |
13542243 ps |