Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13658708

1

T1

9062

T3

137184

T4

15386

full_word

54200648

1

T1

89982

T3

30500

T4

92315

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67859026	1			T1	99044		T3	167684		T4	107701
auto[TlIntgErrCmd]	100	1			T56	4		T57	7		T58	6
auto[TlIntgErrData]	110	1			T56	3		T57	8		T58	1
auto[TlIntgErrBoth]	120	1			T56	3		T57	5		T58	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30991467

1

T1

49738

T3

84056

T4

40206

auto[1]

36867889

1

T1

49306

T3

83628

T4

67495

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6517958	1			T1	4460		T3	68853		T4	4039
auto[TlIntgErrNone]	partial	auto[1]	7140452	1			T1	4602		T3	68331		T4	11347
auto[TlIntgErrNone]	full_word	auto[0]	24473353	1			T1	45278		T3	15203		T4	36167
auto[TlIntgErrNone]	full_word	auto[1]	29727263	1			T1	44704		T3	15297		T4	56148
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T56	3		T57	2		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T56	1		T57	3		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T57	1		T121	2		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T57	1		T58	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T56	1		T57	5		T58	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T56	2		T57	3		T121	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T124	1		T129	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T123	1		T131	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T56	1		T57	2		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T56	2		T57	3		T58	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T123	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T121	1		T133	1		T124	1