Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	661125	1			T3	3530		T20	37		T21	246
auto[1]	10535675	1			T1	21886		T3	9923		T4	1160
auto[2]	541484	1			T3	2617		T20	41		T21	151
auto[3]	10418803	1			T1	21636		T3	8816		T4	1203

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14364515	1			T1	35927		T3	381		T4	1952
auto[1]	2109226	1			T1	3601		T3	2481		T4	209
auto[2]	2128747	1			T1	3639		T3	3493		T4	182
auto[3]	3554599	1			T1	355		T3	18531		T4	20

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8381194

1

T1

43480

T3

5

T4

2359

auto[1]

13775893

1

T1

42

T3

24881

T4

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	213788	1			T20	37		T21	207		T41	1662
auto[0]	auto[0]	auto[1]	22111	1			T21	20		T41	175		T42	66
auto[0]	auto[0]	auto[2]	22001	1			T21	16		T41	177		T42	49
auto[0]	auto[0]	auto[3]	6990	1			T3	1		T21	3		T41	12
auto[0]	auto[1]	auto[0]	3249565	1			T1	18089		T4	960		T12	9015
auto[0]	auto[1]	auto[1]	331080	1			T1	1781		T3	1		T4	111
auto[0]	auto[1]	auto[2]	325939	1			T1	1820		T3	1		T4	79
auto[0]	auto[1]	auto[3]	63200	1			T1	177		T3	1		T4	8
auto[0]	auto[2]	auto[0]	175132	1			T41	952		T42	350		T50	1
auto[0]	auto[2]	auto[1]	18091	1			T41	88		T42	41		T135	693
auto[0]	auto[2]	auto[2]	22143	1			T20	38		T21	138		T41	167
auto[0]	auto[2]	auto[3]	6041	1			T20	3		T21	13		T41	9
auto[0]	auto[3]	auto[0]	3206671	1			T1	17803		T4	989		T12	9023
auto[0]	auto[3]	auto[1]	321800	1			T1	1817		T4	98		T12	913
auto[0]	auto[3]	auto[2]	331577	1			T1	1816		T4	102		T12	823
auto[0]	auto[3]	auto[3]	65065	1			T1	177		T3	1		T4	12
auto[1]	auto[0]	auto[0]	13376	1			T3	100		T100	181		T135	12
auto[1]	auto[0]	auto[1]	58927	1			T3	554		T100	755		T135	1
auto[1]	auto[0]	auto[2]	58852	1			T3	493		T100	763		T101	1690
auto[1]	auto[0]	auto[3]	265080	1			T3	2382		T100	3429		T101	8001
auto[1]	auto[1]	auto[0]	3749568	1			T1	17		T3	198		T4	2
auto[1]	auto[1]	auto[1]	675543	1			T1	2		T3	1491		T14	5
auto[1]	auto[1]	auto[2]	653721	1			T3	994		T14	4		T68	1
auto[1]	auto[1]	auto[3]	1487059	1			T3	7237		T69	508		T22	1
auto[1]	auto[2]	auto[0]	9842	1			T41	1		T135	7		T138	3
auto[1]	auto[2]	auto[1]	43333	1			T135	1		T101	1039		T139	3738
auto[1]	auto[2]	auto[2]	48444	1			T3	465		T100	622		T135	1
auto[1]	auto[2]	auto[3]	218458	1			T3	2152		T100	3062		T101	8859
auto[1]	auto[3]	auto[0]	3746573	1			T1	18		T3	83		T4	1
auto[1]	auto[3]	auto[1]	638341	1			T1	1		T3	435		T12	1
auto[1]	auto[3]	auto[2]	666070	1			T1	3		T3	1540		T4	1
auto[1]	auto[3]	auto[3]	1442706	1			T1	1		T3	6757		T38	1