Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	317077445	186317	0	0
ctrl_regwen_rd_A	317077445	4679	0	0
exec_rd_A	317077445	4318	0	0
exec_regwen_rd_A	317077445	4671	0	0
readback_rd_A	317077445	2690	0	0
readback_regwen_rd_A	317077445	2506	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317077445	186317	0	0
T4	225896	10816	0	0
T5	72777	0	0	0
T6	9230	0	0	0
T11	107093	0	0	0
T12	125199	0	0	0
T13	1943	0	0	0
T14	256069	0	0	0
T20	198735	0	0	0
T24	0	740	0	0
T25	0	2963	0	0
T38	9267	0	0	0
T39	5110	0	0	0
T45	0	2725	0	0
T49	0	6532	0	0
T50	0	4404	0	0
T53	0	3130	0	0
T62	0	4606	0	0
T63	0	1063	0	0
T64	0	3319	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317077445	4679	0	0
T21	229304	0	0	0
T24	12678	46	0	0
T25	69581	0	0	0
T26	2068	0	0	0
T45	0	244	0	0
T48	9400	0	0	0
T50	0	409	0	0
T63	0	92	0	0
T67	62325	0	0	0
T68	12004	0	0	0
T69	169731	0	0	0
T79	247096	0	0	0
T113	0	220	0	0
T114	0	229	0	0
T115	0	198	0	0
T116	0	278	0	0
T117	0	448	0	0
T118	0	39	0	0
T119	198527	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317077445	4318	0	0
T21	229304	0	0	0
T24	12678	48	0	0
T25	69581	0	0	0
T26	2068	0	0	0
T45	0	202	0	0
T48	9400	0	0	0
T50	0	347	0	0
T63	0	98	0	0
T67	62325	0	0	0
T68	12004	0	0	0
T69	169731	0	0	0
T79	247096	0	0	0
T113	0	198	0	0
T114	0	161	0	0
T115	0	175	0	0
T116	0	247	0	0
T117	0	311	0	0
T118	0	36	0	0
T119	198527	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317077445	4671	0	0
T21	229304	0	0	0
T24	12678	79	0	0
T25	69581	0	0	0
T26	2068	0	0	0
T45	0	194	0	0
T48	9400	0	0	0
T50	0	326	0	0
T63	0	90	0	0
T67	62325	0	0	0
T68	12004	0	0	0
T69	169731	0	0	0
T79	247096	0	0	0
T113	0	214	0	0
T114	0	200	0	0
T115	0	209	0	0
T116	0	272	0	0
T117	0	382	0	0
T118	0	58	0	0
T119	198527	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317077445	2690	0	0
T21	229304	0	0	0
T24	12678	41	0	0
T25	69581	0	0	0
T26	2068	0	0	0
T45	0	230	0	0
T48	9400	0	0	0
T50	0	416	0	0
T63	0	86	0	0
T67	62325	0	0	0
T68	12004	0	0	0
T69	169731	0	0	0
T79	247096	0	0	0
T113	0	200	0	0
T114	0	127	0	0
T115	0	189	0	0
T116	0	287	0	0
T117	0	268	0	0
T118	0	53	0	0
T119	198527	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317077445	2506	0	0
T21	229304	0	0	0
T24	12678	87	0	0
T25	69581	0	0	0
T26	2068	0	0	0
T45	0	208	0	0
T48	9400	0	0	0
T50	0	297	0	0
T63	0	59	0	0
T67	62325	0	0	0
T68	12004	0	0	0
T69	169731	0	0	0
T79	247096	0	0	0
T113	0	187	0	0
T114	0	133	0	0
T115	0	151	0	0
T116	0	326	0	0
T117	0	376	0	0
T118	0	70	0	0
T119	198527	0	0	0