| T792 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.1196684516 |
|
|
Jul 13 04:40:44 PM PDT 24 |
Jul 13 04:43:43 PM PDT 24 |
8141020458 ps |
| T793 |
/workspace/coverage/default/25.sram_ctrl_regwen.3948134257 |
|
|
Jul 13 04:40:46 PM PDT 24 |
Jul 13 04:59:25 PM PDT 24 |
1983855100 ps |
| T794 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.403016060 |
|
|
Jul 13 04:41:13 PM PDT 24 |
Jul 13 04:46:03 PM PDT 24 |
13413149482 ps |
| T795 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3760430574 |
|
|
Jul 13 04:39:59 PM PDT 24 |
Jul 13 04:41:12 PM PDT 24 |
229664662 ps |
| T796 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1935682279 |
|
|
Jul 13 04:40:13 PM PDT 24 |
Jul 13 05:21:23 PM PDT 24 |
29805916364 ps |
| T797 |
/workspace/coverage/default/27.sram_ctrl_regwen.314018710 |
|
|
Jul 13 04:40:54 PM PDT 24 |
Jul 13 04:44:38 PM PDT 24 |
1923512081 ps |
| T798 |
/workspace/coverage/default/5.sram_ctrl_executable.290368903 |
|
|
Jul 13 04:39:57 PM PDT 24 |
Jul 13 04:43:19 PM PDT 24 |
2236784015 ps |
| T799 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3646046953 |
|
|
Jul 13 04:41:53 PM PDT 24 |
Jul 13 04:41:59 PM PDT 24 |
3161338263 ps |
| T800 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1915384669 |
|
|
Jul 13 04:40:08 PM PDT 24 |
Jul 13 04:40:24 PM PDT 24 |
663286774 ps |
| T801 |
/workspace/coverage/default/27.sram_ctrl_bijection.3111629433 |
|
|
Jul 13 04:40:49 PM PDT 24 |
Jul 13 04:42:06 PM PDT 24 |
3521865152 ps |
| T802 |
/workspace/coverage/default/44.sram_ctrl_bijection.721682303 |
|
|
Jul 13 04:41:58 PM PDT 24 |
Jul 13 04:42:37 PM PDT 24 |
3341627883 ps |
| T803 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1970249451 |
|
|
Jul 13 04:40:52 PM PDT 24 |
Jul 13 04:43:28 PM PDT 24 |
6052788370 ps |
| T804 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3862699482 |
|
|
Jul 13 04:39:50 PM PDT 24 |
Jul 13 04:46:05 PM PDT 24 |
19663437045 ps |
| T805 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1679528336 |
|
|
Jul 13 04:41:38 PM PDT 24 |
Jul 13 04:42:48 PM PDT 24 |
226715259 ps |
| T806 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1383210666 |
|
|
Jul 13 04:40:10 PM PDT 24 |
Jul 13 04:42:17 PM PDT 24 |
311472897 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1314741119 |
|
|
Jul 13 04:41:24 PM PDT 24 |
Jul 13 04:41:25 PM PDT 24 |
14415432 ps |
| T808 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.686620936 |
|
|
Jul 13 04:39:45 PM PDT 24 |
Jul 13 04:45:18 PM PDT 24 |
117495167305 ps |
| T809 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1278778623 |
|
|
Jul 13 04:40:06 PM PDT 24 |
Jul 13 05:22:37 PM PDT 24 |
95697919093 ps |
| T810 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.742686209 |
|
|
Jul 13 04:39:28 PM PDT 24 |
Jul 13 04:40:58 PM PDT 24 |
1157055309 ps |
| T811 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.385694962 |
|
|
Jul 13 04:41:57 PM PDT 24 |
Jul 13 04:41:59 PM PDT 24 |
48072574 ps |
| T812 |
/workspace/coverage/default/44.sram_ctrl_regwen.584737944 |
|
|
Jul 13 04:41:41 PM PDT 24 |
Jul 13 04:49:28 PM PDT 24 |
9209754345 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_executable.3324485269 |
|
|
Jul 13 04:40:02 PM PDT 24 |
Jul 13 04:55:58 PM PDT 24 |
8677899326 ps |
| T814 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.808992257 |
|
|
Jul 13 04:40:48 PM PDT 24 |
Jul 13 04:47:01 PM PDT 24 |
116494157157 ps |
| T815 |
/workspace/coverage/default/0.sram_ctrl_smoke.384449876 |
|
|
Jul 13 04:39:26 PM PDT 24 |
Jul 13 04:39:39 PM PDT 24 |
591310625 ps |
| T816 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2691900887 |
|
|
Jul 13 04:40:12 PM PDT 24 |
Jul 13 04:40:17 PM PDT 24 |
98779667 ps |
| T817 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1507485609 |
|
|
Jul 13 04:42:15 PM PDT 24 |
Jul 13 04:42:18 PM PDT 24 |
582626334 ps |
| T818 |
/workspace/coverage/default/17.sram_ctrl_regwen.886291313 |
|
|
Jul 13 04:40:08 PM PDT 24 |
Jul 13 04:48:13 PM PDT 24 |
16754580007 ps |
| T819 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3501267739 |
|
|
Jul 13 04:40:17 PM PDT 24 |
Jul 13 04:40:28 PM PDT 24 |
699801864 ps |
| T820 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.347250206 |
|
|
Jul 13 04:40:02 PM PDT 24 |
Jul 13 04:40:06 PM PDT 24 |
113742204 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3395931815 |
|
|
Jul 13 04:41:15 PM PDT 24 |
Jul 13 04:42:55 PM PDT 24 |
596381348 ps |
| T822 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4036651235 |
|
|
Jul 13 04:40:49 PM PDT 24 |
Jul 13 04:52:26 PM PDT 24 |
19362882572 ps |
| T823 |
/workspace/coverage/default/35.sram_ctrl_executable.3430266848 |
|
|
Jul 13 04:41:19 PM PDT 24 |
Jul 13 04:41:49 PM PDT 24 |
3733196794 ps |
| T824 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1251916437 |
|
|
Jul 13 04:41:35 PM PDT 24 |
Jul 13 04:41:48 PM PDT 24 |
925746308 ps |
| T825 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2617712793 |
|
|
Jul 13 04:41:39 PM PDT 24 |
Jul 13 04:41:44 PM PDT 24 |
58242104 ps |
| T826 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.567722912 |
|
|
Jul 13 04:41:43 PM PDT 24 |
Jul 13 04:44:17 PM PDT 24 |
1428329478 ps |
| T827 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1691571973 |
|
|
Jul 13 04:40:24 PM PDT 24 |
Jul 13 04:40:30 PM PDT 24 |
472365310 ps |
| T828 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3957484163 |
|
|
Jul 13 04:40:33 PM PDT 24 |
Jul 13 04:47:18 PM PDT 24 |
7035703648 ps |
| T829 |
/workspace/coverage/default/23.sram_ctrl_regwen.2961269683 |
|
|
Jul 13 04:40:48 PM PDT 24 |
Jul 13 04:53:14 PM PDT 24 |
20189336485 ps |
| T830 |
/workspace/coverage/default/31.sram_ctrl_alert_test.648189637 |
|
|
Jul 13 04:41:01 PM PDT 24 |
Jul 13 04:41:03 PM PDT 24 |
22817063 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2629135830 |
|
|
Jul 13 04:39:50 PM PDT 24 |
Jul 13 04:46:19 PM PDT 24 |
1603988904 ps |
| T832 |
/workspace/coverage/default/24.sram_ctrl_bijection.1481083668 |
|
|
Jul 13 04:40:44 PM PDT 24 |
Jul 13 04:41:26 PM PDT 24 |
1327287801 ps |
| T833 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.95642022 |
|
|
Jul 13 04:41:12 PM PDT 24 |
Jul 13 04:41:20 PM PDT 24 |
1222434255 ps |
| T834 |
/workspace/coverage/default/32.sram_ctrl_executable.750318125 |
|
|
Jul 13 04:40:57 PM PDT 24 |
Jul 13 05:14:36 PM PDT 24 |
169672482877 ps |
| T835 |
/workspace/coverage/default/43.sram_ctrl_regwen.717917016 |
|
|
Jul 13 04:41:39 PM PDT 24 |
Jul 13 04:45:44 PM PDT 24 |
9964485307 ps |
| T836 |
/workspace/coverage/default/46.sram_ctrl_smoke.2978316841 |
|
|
Jul 13 04:41:49 PM PDT 24 |
Jul 13 04:41:51 PM PDT 24 |
127702644 ps |
| T837 |
/workspace/coverage/default/38.sram_ctrl_smoke.1134100559 |
|
|
Jul 13 04:41:24 PM PDT 24 |
Jul 13 04:41:35 PM PDT 24 |
597943967 ps |
| T838 |
/workspace/coverage/default/37.sram_ctrl_regwen.4087804835 |
|
|
Jul 13 04:41:15 PM PDT 24 |
Jul 13 04:57:10 PM PDT 24 |
27311006783 ps |
| T839 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1711103658 |
|
|
Jul 13 04:40:04 PM PDT 24 |
Jul 13 04:55:15 PM PDT 24 |
30007138124 ps |
| T840 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.597556666 |
|
|
Jul 13 04:40:42 PM PDT 24 |
Jul 13 04:43:55 PM PDT 24 |
2408298543 ps |
| T841 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.582263581 |
|
|
Jul 13 04:40:15 PM PDT 24 |
Jul 13 04:55:49 PM PDT 24 |
12969570232 ps |
| T842 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2639893184 |
|
|
Jul 13 04:39:25 PM PDT 24 |
Jul 13 04:39:27 PM PDT 24 |
18067632 ps |
| T843 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2203968321 |
|
|
Jul 13 04:40:11 PM PDT 24 |
Jul 13 04:44:04 PM PDT 24 |
9515038161 ps |
| T844 |
/workspace/coverage/default/32.sram_ctrl_stress_all.448042295 |
|
|
Jul 13 04:41:14 PM PDT 24 |
Jul 13 05:19:45 PM PDT 24 |
6970049263 ps |
| T845 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3285942219 |
|
|
Jul 13 04:39:59 PM PDT 24 |
Jul 13 04:48:19 PM PDT 24 |
26348129476 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1939310673 |
|
|
Jul 13 04:40:23 PM PDT 24 |
Jul 13 04:44:55 PM PDT 24 |
1553076901 ps |
| T847 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2412956915 |
|
|
Jul 13 04:40:50 PM PDT 24 |
Jul 13 04:40:55 PM PDT 24 |
85225114 ps |
| T848 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.4182320267 |
|
|
Jul 13 04:40:30 PM PDT 24 |
Jul 13 04:40:34 PM PDT 24 |
395319810 ps |
| T849 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2284022068 |
|
|
Jul 13 04:41:35 PM PDT 24 |
Jul 13 04:47:06 PM PDT 24 |
14218474288 ps |
| T850 |
/workspace/coverage/default/29.sram_ctrl_executable.3795012757 |
|
|
Jul 13 04:40:55 PM PDT 24 |
Jul 13 04:44:14 PM PDT 24 |
5313396234 ps |
| T851 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2146410916 |
|
|
Jul 13 04:41:29 PM PDT 24 |
Jul 13 04:55:21 PM PDT 24 |
2515957704 ps |
| T852 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2908573306 |
|
|
Jul 13 04:41:13 PM PDT 24 |
Jul 13 04:41:16 PM PDT 24 |
77143188 ps |
| T853 |
/workspace/coverage/default/46.sram_ctrl_regwen.2129375148 |
|
|
Jul 13 04:41:48 PM PDT 24 |
Jul 13 05:00:18 PM PDT 24 |
12866002730 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.476981035 |
|
|
Jul 13 04:40:38 PM PDT 24 |
Jul 13 04:40:43 PM PDT 24 |
715611936 ps |
| T855 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3829047645 |
|
|
Jul 13 04:41:38 PM PDT 24 |
Jul 13 04:41:45 PM PDT 24 |
665399317 ps |
| T856 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1699290938 |
|
|
Jul 13 04:41:27 PM PDT 24 |
Jul 13 04:54:37 PM PDT 24 |
7176297705 ps |
| T857 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.728228660 |
|
|
Jul 13 04:40:01 PM PDT 24 |
Jul 13 04:40:08 PM PDT 24 |
1332619568 ps |
| T858 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.603601176 |
|
|
Jul 13 04:42:09 PM PDT 24 |
Jul 13 04:42:11 PM PDT 24 |
95866881 ps |
| T859 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.4052629518 |
|
|
Jul 13 04:40:14 PM PDT 24 |
Jul 13 04:55:30 PM PDT 24 |
2213413512 ps |
| T860 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3444949032 |
|
|
Jul 13 04:40:14 PM PDT 24 |
Jul 13 04:59:23 PM PDT 24 |
16273661655 ps |
| T861 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.316610800 |
|
|
Jul 13 04:40:46 PM PDT 24 |
Jul 13 04:40:48 PM PDT 24 |
39320158 ps |
| T862 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2736475220 |
|
|
Jul 13 04:40:18 PM PDT 24 |
Jul 13 04:40:25 PM PDT 24 |
366519619 ps |
| T863 |
/workspace/coverage/default/12.sram_ctrl_smoke.189916240 |
|
|
Jul 13 04:40:12 PM PDT 24 |
Jul 13 04:40:23 PM PDT 24 |
413644397 ps |
| T864 |
/workspace/coverage/default/6.sram_ctrl_bijection.2361951126 |
|
|
Jul 13 04:40:05 PM PDT 24 |
Jul 13 04:40:56 PM PDT 24 |
2432880828 ps |
| T865 |
/workspace/coverage/default/17.sram_ctrl_bijection.3375382327 |
|
|
Jul 13 04:40:10 PM PDT 24 |
Jul 13 04:41:03 PM PDT 24 |
3065604426 ps |
| T866 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2142143577 |
|
|
Jul 13 04:39:44 PM PDT 24 |
Jul 13 04:54:58 PM PDT 24 |
4069409694 ps |
| T867 |
/workspace/coverage/default/25.sram_ctrl_smoke.422370051 |
|
|
Jul 13 04:40:48 PM PDT 24 |
Jul 13 04:40:53 PM PDT 24 |
385741484 ps |
| T868 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2430990602 |
|
|
Jul 13 04:39:56 PM PDT 24 |
Jul 13 04:41:31 PM PDT 24 |
550790033 ps |
| T869 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3745165038 |
|
|
Jul 13 04:40:13 PM PDT 24 |
Jul 13 04:40:27 PM PDT 24 |
4150795915 ps |
| T870 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3129232980 |
|
|
Jul 13 04:40:13 PM PDT 24 |
Jul 13 04:40:31 PM PDT 24 |
3576566175 ps |
| T871 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.851859868 |
|
|
Jul 13 04:40:47 PM PDT 24 |
Jul 13 04:40:54 PM PDT 24 |
559696093 ps |
| T872 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3196006251 |
|
|
Jul 13 04:41:49 PM PDT 24 |
Jul 13 04:41:51 PM PDT 24 |
27372155 ps |
| T873 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3698171278 |
|
|
Jul 13 04:40:43 PM PDT 24 |
Jul 13 04:41:19 PM PDT 24 |
1212398704 ps |
| T874 |
/workspace/coverage/default/16.sram_ctrl_alert_test.4154714326 |
|
|
Jul 13 04:40:41 PM PDT 24 |
Jul 13 04:40:43 PM PDT 24 |
16036084 ps |
| T875 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1712849514 |
|
|
Jul 13 04:40:14 PM PDT 24 |
Jul 13 04:40:21 PM PDT 24 |
292119455 ps |
| T876 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3772916073 |
|
|
Jul 13 04:40:57 PM PDT 24 |
Jul 13 05:26:04 PM PDT 24 |
45823367170 ps |
| T877 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1348079483 |
|
|
Jul 13 04:41:34 PM PDT 24 |
Jul 13 04:41:56 PM PDT 24 |
2406675557 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1957976344 |
|
|
Jul 13 04:39:48 PM PDT 24 |
Jul 13 04:39:50 PM PDT 24 |
50291404 ps |
| T879 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1678008252 |
|
|
Jul 13 04:40:14 PM PDT 24 |
Jul 13 04:40:30 PM PDT 24 |
663793935 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1746233593 |
|
|
Jul 13 04:41:19 PM PDT 24 |
Jul 13 04:42:13 PM PDT 24 |
4183122427 ps |
| T881 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1123646274 |
|
|
Jul 13 04:40:26 PM PDT 24 |
Jul 13 04:53:04 PM PDT 24 |
3659941485 ps |
| T882 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4217180941 |
|
|
Jul 13 04:40:30 PM PDT 24 |
Jul 13 04:40:32 PM PDT 24 |
61808855 ps |
| T883 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2555844374 |
|
|
Jul 13 04:40:50 PM PDT 24 |
Jul 13 04:40:58 PM PDT 24 |
961645282 ps |
| T884 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3676350630 |
|
|
Jul 13 04:40:40 PM PDT 24 |
Jul 13 04:40:46 PM PDT 24 |
131935300 ps |
| T885 |
/workspace/coverage/default/42.sram_ctrl_smoke.703777308 |
|
|
Jul 13 04:41:30 PM PDT 24 |
Jul 13 04:41:45 PM PDT 24 |
922881343 ps |
| T886 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2677532165 |
|
|
Jul 13 04:40:20 PM PDT 24 |
Jul 13 04:40:28 PM PDT 24 |
54371754 ps |
| T887 |
/workspace/coverage/default/10.sram_ctrl_regwen.3059284553 |
|
|
Jul 13 04:40:29 PM PDT 24 |
Jul 13 04:42:32 PM PDT 24 |
1061299803 ps |
| T888 |
/workspace/coverage/default/47.sram_ctrl_alert_test.4088930974 |
|
|
Jul 13 04:41:55 PM PDT 24 |
Jul 13 04:41:56 PM PDT 24 |
38536199 ps |
| T889 |
/workspace/coverage/default/42.sram_ctrl_executable.884022635 |
|
|
Jul 13 04:41:59 PM PDT 24 |
Jul 13 04:56:17 PM PDT 24 |
16695909452 ps |
| T890 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.407441991 |
|
|
Jul 13 04:40:02 PM PDT 24 |
Jul 13 04:41:14 PM PDT 24 |
8219993032 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1064072279 |
|
|
Jul 13 04:40:23 PM PDT 24 |
Jul 13 04:41:35 PM PDT 24 |
800889912 ps |
| T892 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3883088159 |
|
|
Jul 13 04:41:40 PM PDT 24 |
Jul 13 04:42:55 PM PDT 24 |
905544466 ps |
| T893 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2387725656 |
|
|
Jul 13 04:39:44 PM PDT 24 |
Jul 13 04:46:39 PM PDT 24 |
33321619672 ps |
| T894 |
/workspace/coverage/default/12.sram_ctrl_regwen.1750035140 |
|
|
Jul 13 04:40:23 PM PDT 24 |
Jul 13 05:07:43 PM PDT 24 |
19493748457 ps |
| T895 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3877150722 |
|
|
Jul 13 04:41:52 PM PDT 24 |
Jul 13 04:41:54 PM PDT 24 |
201585567 ps |
| T896 |
/workspace/coverage/default/9.sram_ctrl_regwen.1918337671 |
|
|
Jul 13 04:40:26 PM PDT 24 |
Jul 13 04:50:10 PM PDT 24 |
7007550432 ps |
| T897 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.4258510313 |
|
|
Jul 13 04:41:04 PM PDT 24 |
Jul 13 04:41:10 PM PDT 24 |
541645345 ps |
| T898 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1722689123 |
|
|
Jul 13 04:40:41 PM PDT 24 |
Jul 13 04:47:21 PM PDT 24 |
30972441956 ps |
| T899 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2858536265 |
|
|
Jul 13 04:41:06 PM PDT 24 |
Jul 13 04:41:15 PM PDT 24 |
1559757435 ps |
| T900 |
/workspace/coverage/default/39.sram_ctrl_executable.309096502 |
|
|
Jul 13 04:41:40 PM PDT 24 |
Jul 13 04:53:01 PM PDT 24 |
6107185178 ps |
| T901 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3299908631 |
|
|
Jul 13 04:40:56 PM PDT 24 |
Jul 13 04:41:01 PM PDT 24 |
280371850 ps |
| T902 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2938029990 |
|
|
Jul 13 04:41:33 PM PDT 24 |
Jul 13 04:41:35 PM PDT 24 |
29399795 ps |
| T903 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3181077715 |
|
|
Jul 13 04:40:50 PM PDT 24 |
Jul 13 04:43:25 PM PDT 24 |
618673343 ps |
| T904 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2886771324 |
|
|
Jul 13 04:42:00 PM PDT 24 |
Jul 13 04:42:04 PM PDT 24 |
544951305 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1617107013 |
|
|
Jul 13 04:41:28 PM PDT 24 |
Jul 13 04:41:29 PM PDT 24 |
36565081 ps |
| T906 |
/workspace/coverage/default/11.sram_ctrl_regwen.1834421025 |
|
|
Jul 13 04:40:13 PM PDT 24 |
Jul 13 04:54:46 PM PDT 24 |
77822494682 ps |
| T907 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2868831585 |
|
|
Jul 13 04:42:00 PM PDT 24 |
Jul 13 04:42:01 PM PDT 24 |
76186246 ps |
| T908 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2115454166 |
|
|
Jul 13 04:41:04 PM PDT 24 |
Jul 13 04:42:04 PM PDT 24 |
107740030 ps |
| T909 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2670196916 |
|
|
Jul 13 04:40:39 PM PDT 24 |
Jul 13 04:40:50 PM PDT 24 |
3430327251 ps |
| T910 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3781627178 |
|
|
Jul 13 04:40:02 PM PDT 24 |
Jul 13 04:40:03 PM PDT 24 |
42047833 ps |
| T911 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4178149523 |
|
|
Jul 13 04:41:46 PM PDT 24 |
Jul 13 04:43:56 PM PDT 24 |
5058294626 ps |
| T912 |
/workspace/coverage/default/26.sram_ctrl_smoke.3830152752 |
|
|
Jul 13 04:40:56 PM PDT 24 |
Jul 13 04:41:14 PM PDT 24 |
951134046 ps |
| T913 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2868952069 |
|
|
Jul 13 04:40:10 PM PDT 24 |
Jul 13 05:07:19 PM PDT 24 |
9894378405 ps |
| T914 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1860018324 |
|
|
Jul 13 04:40:41 PM PDT 24 |
Jul 13 05:02:31 PM PDT 24 |
38139111851 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_smoke.4210523713 |
|
|
Jul 13 04:40:03 PM PDT 24 |
Jul 13 04:41:14 PM PDT 24 |
665916079 ps |
| T916 |
/workspace/coverage/default/31.sram_ctrl_stress_all.4191342625 |
|
|
Jul 13 04:41:14 PM PDT 24 |
Jul 13 05:44:04 PM PDT 24 |
7213794254 ps |
| T917 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3499834606 |
|
|
Jul 13 04:40:12 PM PDT 24 |
Jul 13 04:40:23 PM PDT 24 |
1961522301 ps |
| T918 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1044903315 |
|
|
Jul 13 04:40:31 PM PDT 24 |
Jul 13 05:09:35 PM PDT 24 |
5684380019 ps |
| T919 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1216169370 |
|
|
Jul 13 04:40:39 PM PDT 24 |
Jul 13 04:54:30 PM PDT 24 |
3329949338 ps |
| T920 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.2008168351 |
|
|
Jul 13 04:41:20 PM PDT 24 |
Jul 13 04:41:57 PM PDT 24 |
91395189 ps |
| T921 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2019608064 |
|
|
Jul 13 04:39:45 PM PDT 24 |
Jul 13 04:39:48 PM PDT 24 |
15364396 ps |
| T922 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1182229514 |
|
|
Jul 13 04:40:09 PM PDT 24 |
Jul 13 05:54:54 PM PDT 24 |
53767132707 ps |
| T923 |
/workspace/coverage/default/20.sram_ctrl_smoke.279714446 |
|
|
Jul 13 04:40:20 PM PDT 24 |
Jul 13 04:40:25 PM PDT 24 |
55176403 ps |
| T924 |
/workspace/coverage/default/12.sram_ctrl_partial_access.294177631 |
|
|
Jul 13 04:40:44 PM PDT 24 |
Jul 13 04:41:07 PM PDT 24 |
441194211 ps |
| T925 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3406577215 |
|
|
Jul 13 04:40:49 PM PDT 24 |
Jul 13 04:41:00 PM PDT 24 |
218021833 ps |
| T926 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1963381585 |
|
|
Jul 13 04:40:44 PM PDT 24 |
Jul 13 04:46:21 PM PDT 24 |
3325344177 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3278495392 |
|
|
Jul 13 04:41:11 PM PDT 24 |
Jul 13 04:43:34 PM PDT 24 |
320654471 ps |
| T928 |
/workspace/coverage/default/48.sram_ctrl_bijection.257340372 |
|
|
Jul 13 04:41:56 PM PDT 24 |
Jul 13 04:43:15 PM PDT 24 |
4872791858 ps |
| T929 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2913337749 |
|
|
Jul 13 04:42:01 PM PDT 24 |
Jul 13 04:46:48 PM PDT 24 |
1770929389 ps |
| T56 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3836938457 |
|
|
Jul 13 04:38:38 PM PDT 24 |
Jul 13 04:38:41 PM PDT 24 |
349163176 ps |
| T59 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2508049059 |
|
|
Jul 13 04:38:19 PM PDT 24 |
Jul 13 04:38:22 PM PDT 24 |
151773901 ps |
| T60 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4036522083 |
|
|
Jul 13 04:38:05 PM PDT 24 |
Jul 13 04:38:15 PM PDT 24 |
355443073 ps |
| T930 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2337782050 |
|
|
Jul 13 04:38:38 PM PDT 24 |
Jul 13 04:38:46 PM PDT 24 |
46663001 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3280938144 |
|
|
Jul 13 04:38:19 PM PDT 24 |
Jul 13 04:38:24 PM PDT 24 |
818182305 ps |
| T57 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2940034194 |
|
|
Jul 13 04:38:45 PM PDT 24 |
Jul 13 04:38:48 PM PDT 24 |
573568514 ps |
| T931 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.340880602 |
|
|
Jul 13 04:38:09 PM PDT 24 |
Jul 13 04:38:16 PM PDT 24 |
115789964 ps |
| T71 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4154685338 |
|
|
Jul 13 04:38:05 PM PDT 24 |
Jul 13 04:38:15 PM PDT 24 |
887113119 ps |
| T932 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4264961144 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:34 PM PDT 24 |
515569355 ps |
| T72 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1204143646 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
418052584 ps |
| T933 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3653644852 |
|
|
Jul 13 04:38:31 PM PDT 24 |
Jul 13 04:38:35 PM PDT 24 |
71808268 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2649041980 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:19 PM PDT 24 |
145157472 ps |
| T58 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2524129953 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:32 PM PDT 24 |
172319328 ps |
| T934 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2855132905 |
|
|
Jul 13 04:38:09 PM PDT 24 |
Jul 13 04:38:19 PM PDT 24 |
148633463 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1012855839 |
|
|
Jul 13 04:38:24 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
34058506 ps |
| T75 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1390292115 |
|
|
Jul 13 04:38:18 PM PDT 24 |
Jul 13 04:38:20 PM PDT 24 |
15160867 ps |
| T112 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4131217144 |
|
|
Jul 13 04:38:22 PM PDT 24 |
Jul 13 04:38:26 PM PDT 24 |
10775719 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2920186041 |
|
|
Jul 13 04:38:24 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
33167458 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.207046238 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:20 PM PDT 24 |
36942736 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3274330026 |
|
|
Jul 13 04:38:07 PM PDT 24 |
Jul 13 04:38:16 PM PDT 24 |
41972203 ps |
| T937 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.501204446 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
233902862 ps |
| T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4009362027 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:20 PM PDT 24 |
58783560 ps |
| T938 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.52569917 |
|
|
Jul 13 04:38:22 PM PDT 24 |
Jul 13 04:38:26 PM PDT 24 |
121158041 ps |
| T77 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3962150625 |
|
|
Jul 13 04:38:03 PM PDT 24 |
Jul 13 04:38:12 PM PDT 24 |
12432113 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.981689024 |
|
|
Jul 13 04:38:10 PM PDT 24 |
Jul 13 04:38:17 PM PDT 24 |
182340123 ps |
| T939 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.836688178 |
|
|
Jul 13 04:38:24 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
32083677 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3723405682 |
|
|
Jul 13 04:38:26 PM PDT 24 |
Jul 13 04:38:29 PM PDT 24 |
24383831 ps |
| T941 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3426251106 |
|
|
Jul 13 04:38:05 PM PDT 24 |
Jul 13 04:38:13 PM PDT 24 |
69340529 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.845178132 |
|
|
Jul 13 04:38:16 PM PDT 24 |
Jul 13 04:38:19 PM PDT 24 |
15673071 ps |
| T942 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3813533731 |
|
|
Jul 13 04:38:19 PM PDT 24 |
Jul 13 04:38:22 PM PDT 24 |
37076873 ps |
| T83 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3311822105 |
|
|
Jul 13 04:38:36 PM PDT 24 |
Jul 13 04:38:39 PM PDT 24 |
17458533 ps |
| T943 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.164338135 |
|
|
Jul 13 04:38:02 PM PDT 24 |
Jul 13 04:38:11 PM PDT 24 |
30480892 ps |
| T84 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2307093461 |
|
|
Jul 13 04:38:24 PM PDT 24 |
Jul 13 04:38:30 PM PDT 24 |
426511976 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.203491320 |
|
|
Jul 13 04:38:09 PM PDT 24 |
Jul 13 04:38:15 PM PDT 24 |
33898773 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2388872231 |
|
|
Jul 13 04:38:08 PM PDT 24 |
Jul 13 04:38:15 PM PDT 24 |
33049277 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2123971557 |
|
|
Jul 13 04:38:14 PM PDT 24 |
Jul 13 04:38:20 PM PDT 24 |
47975313 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3949416040 |
|
|
Jul 13 04:38:15 PM PDT 24 |
Jul 13 04:38:19 PM PDT 24 |
811938386 ps |
| T86 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2112546561 |
|
|
Jul 13 04:38:29 PM PDT 24 |
Jul 13 04:38:34 PM PDT 24 |
757615796 ps |
| T121 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2833312992 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:33 PM PDT 24 |
639331681 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3166975217 |
|
|
Jul 13 04:38:27 PM PDT 24 |
Jul 13 04:38:30 PM PDT 24 |
95973417 ps |
| T948 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2153566196 |
|
|
Jul 13 04:38:19 PM PDT 24 |
Jul 13 04:38:23 PM PDT 24 |
94363657 ps |
| T949 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2170392989 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:25 PM PDT 24 |
195131744 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.835167514 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
34694943 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4226506877 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:21 PM PDT 24 |
207867086 ps |
| T952 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1853834697 |
|
|
Jul 13 04:38:25 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
49600790 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3841017235 |
|
|
Jul 13 04:38:31 PM PDT 24 |
Jul 13 04:38:34 PM PDT 24 |
1232944075 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1327401460 |
|
|
Jul 13 04:38:22 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
2102649727 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1743476881 |
|
|
Jul 13 04:38:22 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
211546554 ps |
| T953 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1305899049 |
|
|
Jul 13 04:38:06 PM PDT 24 |
Jul 13 04:38:14 PM PDT 24 |
144202377 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.766046837 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
111669924 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1997471053 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:26 PM PDT 24 |
16234552 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2405996430 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:22 PM PDT 24 |
190087429 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1306368269 |
|
|
Jul 13 04:38:12 PM PDT 24 |
Jul 13 04:38:17 PM PDT 24 |
242421455 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1273212598 |
|
|
Jul 13 04:38:02 PM PDT 24 |
Jul 13 04:38:11 PM PDT 24 |
66868300 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2637798998 |
|
|
Jul 13 04:38:31 PM PDT 24 |
Jul 13 04:38:34 PM PDT 24 |
35697315 ps |
| T958 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1405684197 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:20 PM PDT 24 |
47154454 ps |
| T959 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4072227052 |
|
|
Jul 13 04:38:03 PM PDT 24 |
Jul 13 04:38:11 PM PDT 24 |
33448121 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2073006647 |
|
|
Jul 13 04:38:18 PM PDT 24 |
Jul 13 04:38:21 PM PDT 24 |
78924204 ps |
| T123 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.213540331 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
812946136 ps |
| T124 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3555653959 |
|
|
Jul 13 04:38:20 PM PDT 24 |
Jul 13 04:38:26 PM PDT 24 |
3119530211 ps |
| T961 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.148623349 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:24 PM PDT 24 |
37244185 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2428673074 |
|
|
Jul 13 04:38:46 PM PDT 24 |
Jul 13 04:38:47 PM PDT 24 |
20253667 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3994610777 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:24 PM PDT 24 |
53083692 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1496524717 |
|
|
Jul 13 04:38:25 PM PDT 24 |
Jul 13 04:38:31 PM PDT 24 |
555483969 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.788786882 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:26 PM PDT 24 |
255600264 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.133457328 |
|
|
Jul 13 04:38:14 PM PDT 24 |
Jul 13 04:38:17 PM PDT 24 |
24715453 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1508610098 |
|
|
Jul 13 04:37:56 PM PDT 24 |
Jul 13 04:38:05 PM PDT 24 |
145026414 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.242979279 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:31 PM PDT 24 |
38446110 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2027845511 |
|
|
Jul 13 04:38:03 PM PDT 24 |
Jul 13 04:38:13 PM PDT 24 |
195482863 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4046592018 |
|
|
Jul 13 04:38:24 PM PDT 24 |
Jul 13 04:38:30 PM PDT 24 |
321949716 ps |
| T971 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1907166877 |
|
|
Jul 13 04:38:49 PM PDT 24 |
Jul 13 04:38:51 PM PDT 24 |
38939067 ps |
| T129 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.869766311 |
|
|
Jul 13 04:38:36 PM PDT 24 |
Jul 13 04:38:40 PM PDT 24 |
171061943 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1625508050 |
|
|
Jul 13 04:38:06 PM PDT 24 |
Jul 13 04:38:13 PM PDT 24 |
22671483 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1870393641 |
|
|
Jul 13 04:38:19 PM PDT 24 |
Jul 13 04:38:23 PM PDT 24 |
121662282 ps |
| T131 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1773436938 |
|
|
Jul 13 04:38:40 PM PDT 24 |
Jul 13 04:38:43 PM PDT 24 |
167357297 ps |
| T125 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.845980476 |
|
|
Jul 13 04:38:30 PM PDT 24 |
Jul 13 04:38:34 PM PDT 24 |
136673150 ps |
| T95 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2233599533 |
|
|
Jul 13 04:38:17 PM PDT 24 |
Jul 13 04:38:21 PM PDT 24 |
189834990 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1631022341 |
|
|
Jul 13 04:38:25 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
59747757 ps |
| T93 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2556316550 |
|
|
Jul 13 04:38:09 PM PDT 24 |
Jul 13 04:38:18 PM PDT 24 |
1507854867 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1083345563 |
|
|
Jul 13 04:38:33 PM PDT 24 |
Jul 13 04:38:36 PM PDT 24 |
15444563 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1660852375 |
|
|
Jul 13 04:38:27 PM PDT 24 |
Jul 13 04:38:33 PM PDT 24 |
618121911 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2480315564 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:34 PM PDT 24 |
72911802 ps |
| T978 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.254451203 |
|
|
Jul 13 04:38:43 PM PDT 24 |
Jul 13 04:38:46 PM PDT 24 |
193194942 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1426333385 |
|
|
Jul 13 04:38:22 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
41617563 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2089503520 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:24 PM PDT 24 |
401053268 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2551364319 |
|
|
Jul 13 04:38:01 PM PDT 24 |
Jul 13 04:38:13 PM PDT 24 |
212517382 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.658756148 |
|
|
Jul 13 04:38:20 PM PDT 24 |
Jul 13 04:38:23 PM PDT 24 |
402345095 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3483953138 |
|
|
Jul 13 04:38:12 PM PDT 24 |
Jul 13 04:38:17 PM PDT 24 |
65072171 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3502605402 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:23 PM PDT 24 |
146774549 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2129466565 |
|
|
Jul 13 04:38:37 PM PDT 24 |
Jul 13 04:38:40 PM PDT 24 |
14020045 ps |
| T986 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1037117456 |
|
|
Jul 13 04:38:26 PM PDT 24 |
Jul 13 04:38:30 PM PDT 24 |
20423231 ps |
| T987 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1359243539 |
|
|
Jul 13 04:38:25 PM PDT 24 |
Jul 13 04:38:30 PM PDT 24 |
103681696 ps |
| T132 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1725834093 |
|
|
Jul 13 04:38:26 PM PDT 24 |
Jul 13 04:38:31 PM PDT 24 |
266192511 ps |
| T128 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1469694893 |
|
|
Jul 13 04:38:31 PM PDT 24 |
Jul 13 04:38:35 PM PDT 24 |
253110358 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.455071034 |
|
|
Jul 13 04:37:59 PM PDT 24 |
Jul 13 04:38:09 PM PDT 24 |
68513163 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3769025959 |
|
|
Jul 13 04:38:24 PM PDT 24 |
Jul 13 04:38:27 PM PDT 24 |
12844031 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1914581641 |
|
|
Jul 13 04:38:13 PM PDT 24 |
Jul 13 04:38:19 PM PDT 24 |
425532359 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.466122993 |
|
|
Jul 13 04:38:29 PM PDT 24 |
Jul 13 04:38:32 PM PDT 24 |
44393974 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2470657300 |
|
|
Jul 13 04:38:19 PM PDT 24 |
Jul 13 04:38:23 PM PDT 24 |
246465728 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.170541648 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:31 PM PDT 24 |
15158176 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3117874761 |
|
|
Jul 13 04:38:11 PM PDT 24 |
Jul 13 04:38:16 PM PDT 24 |
55913068 ps |
| T995 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3117925333 |
|
|
Jul 13 04:38:28 PM PDT 24 |
Jul 13 04:38:32 PM PDT 24 |
489681258 ps |
| T126 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2440421169 |
|
|
Jul 13 04:38:16 PM PDT 24 |
Jul 13 04:38:19 PM PDT 24 |
105995822 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.81862493 |
|
|
Jul 13 04:38:03 PM PDT 24 |
Jul 13 04:38:11 PM PDT 24 |
30682699 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.979960253 |
|
|
Jul 13 04:38:35 PM PDT 24 |
Jul 13 04:38:37 PM PDT 24 |
21750746 ps |
| T998 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.652303698 |
|
|
Jul 13 04:38:21 PM PDT 24 |
Jul 13 04:38:24 PM PDT 24 |
307428001 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1726609437 |
|
|
Jul 13 04:38:46 PM PDT 24 |
Jul 13 04:38:48 PM PDT 24 |
107017180 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2528844657 |
|
|
Jul 13 04:38:05 PM PDT 24 |
Jul 13 04:38:13 PM PDT 24 |
15959144 ps |
| T127 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.840692273 |
|
|
Jul 13 04:38:48 PM PDT 24 |
Jul 13 04:38:51 PM PDT 24 |
397394678 ps |
| T94 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1545406061 |
|
|
Jul 13 04:38:30 PM PDT 24 |
Jul 13 04:38:35 PM PDT 24 |
1339791488 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.212405807 |
|
|
Jul 13 04:38:04 PM PDT 24 |
Jul 13 04:38:12 PM PDT 24 |
14673034 ps |
| T1001 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1844779872 |
|
|
Jul 13 04:38:23 PM PDT 24 |
Jul 13 04:38:28 PM PDT 24 |
70590486 ps |