Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14204520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59376677

1

T1

3071

T2

4046

T3

162637

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36679022	1			T1	1024		T2	2405		T3	89081
values[0x0]	17024570	1			T1	1031		T2	1153		T3	43226
values[0x1]	19877605	1			T1	1016		T2	1326		T3	46562

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7075795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66505402

1

T1

3071

T2

4452

T3

170798

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	273275	1			T2	5		T3	623		T4	5
valid_sources[0x01]	318324	1			T2	11		T3	664		T4	3
valid_sources[0x02]	264093	1			T1	9		T2	5		T3	742
valid_sources[0x03]	311244	1			T1	4		T3	657		T4	2
valid_sources[0x04]	364673	1			T1	11		T2	56		T3	678
valid_sources[0x05]	296687	1			T2	4		T3	726		T4	4
valid_sources[0x06]	317186	1			T1	53		T3	675		T4	5
valid_sources[0x07]	314922	1			T2	69		T3	700		T4	6
valid_sources[0x08]	260447	1			T1	1		T2	7		T3	729
valid_sources[0x09]	255639	1			T3	742		T4	9		T8	11
valid_sources[0x0a]	269808	1			T2	15		T3	665		T4	3
valid_sources[0x0b]	265508	1			T2	67		T3	670		T4	8
valid_sources[0x0c]	283500	1			T2	12		T3	739		T4	3
valid_sources[0x0d]	273538	1			T2	11		T3	694		T4	4
valid_sources[0x0e]	325089	1			T2	8		T3	652		T4	6
valid_sources[0x0f]	269125	1			T2	16		T3	703		T4	5
valid_sources[0x10]	300409	1			T2	10		T3	728		T4	4
valid_sources[0x11]	263697	1			T1	49		T2	32		T3	725
valid_sources[0x12]	256049	1			T2	24		T3	691		T4	2
valid_sources[0x13]	279331	1			T2	20		T3	728		T4	9
valid_sources[0x14]	266385	1			T1	15		T2	29		T3	652
valid_sources[0x15]	280916	1			T1	5		T2	10		T3	683
valid_sources[0x16]	384391	1			T1	33		T2	22		T3	680
valid_sources[0x17]	269871	1			T2	24		T3	697		T4	3
valid_sources[0x18]	278267	1			T2	13		T3	660		T4	2
valid_sources[0x19]	329874	1			T2	19		T3	713		T4	7
valid_sources[0x1a]	269666	1			T1	67		T2	7		T3	721
valid_sources[0x1b]	274296	1			T2	13		T3	710		T4	3
valid_sources[0x1c]	303515	1			T3	714		T4	5		T9	379
valid_sources[0x1d]	265331	1			T3	710		T4	10		T8	2
valid_sources[0x1e]	289119	1			T2	23		T3	690		T4	5
valid_sources[0x1f]	267370	1			T2	59		T3	681		T4	5
valid_sources[0x20]	300137	1			T1	22		T3	720		T4	1
valid_sources[0x21]	249983	1			T3	698		T4	8		T9	460
valid_sources[0x22]	333588	1			T2	39		T3	698		T4	7
valid_sources[0x23]	333235	1			T1	14		T2	12		T3	692
valid_sources[0x24]	259879	1			T2	11		T3	710		T4	4
valid_sources[0x25]	326873	1			T1	4		T2	41		T3	663
valid_sources[0x26]	281611	1			T1	1		T2	43		T3	696
valid_sources[0x27]	291320	1			T2	22		T3	674		T4	2
valid_sources[0x28]	336483	1			T1	28		T2	14		T3	670
valid_sources[0x29]	312152	1			T1	48		T2	3		T3	678
valid_sources[0x2a]	277080	1			T1	8		T3	697		T4	1
valid_sources[0x2b]	270183	1			T2	10		T3	766		T4	5
valid_sources[0x2c]	275416	1			T2	10		T3	692		T4	8
valid_sources[0x2d]	373335	1			T2	16		T3	717		T4	3
valid_sources[0x2e]	297335	1			T2	10		T3	719		T4	6
valid_sources[0x2f]	312004	1			T1	2		T2	5		T3	661
valid_sources[0x30]	255845	1			T2	36		T3	702		T4	3
valid_sources[0x31]	275237	1			T2	29		T3	734		T4	7
valid_sources[0x32]	263769	1			T2	29		T3	680		T4	6
valid_sources[0x33]	309243	1			T1	19		T3	696		T4	6
valid_sources[0x34]	255429	1			T1	14		T2	49		T3	677
valid_sources[0x35]	269931	1			T1	40		T2	44		T3	712
valid_sources[0x36]	290967	1			T1	28		T3	745		T4	7
valid_sources[0x37]	254876	1			T2	98		T3	693		T4	5
valid_sources[0x38]	316018	1			T1	29		T2	52		T3	713
valid_sources[0x39]	361301	1			T1	4		T2	39		T3	676
valid_sources[0x3a]	309709	1			T1	128		T2	90		T3	661
valid_sources[0x3b]	262717	1			T2	12		T3	671		T4	8
valid_sources[0x3c]	268198	1			T1	62		T2	61		T3	644
valid_sources[0x3d]	287879	1			T1	2		T2	2		T3	661
valid_sources[0x3e]	358607	1			T2	23		T3	682		T4	8
valid_sources[0x3f]	260405	1			T2	18		T3	734		T4	10
valid_sources[0x40]	310226	1			T1	44		T2	30		T3	669
valid_sources[0x41]	292121	1			T1	51		T2	43		T3	714
valid_sources[0x42]	330266	1			T1	25		T2	20		T3	717
valid_sources[0x43]	280758	1			T1	3		T2	37		T3	705
valid_sources[0x44]	257629	1			T2	6		T3	723		T4	4
valid_sources[0x45]	257225	1			T2	25		T3	694		T4	6
valid_sources[0x46]	251620	1			T1	26		T3	717		T4	6
valid_sources[0x47]	303064	1			T1	43		T3	715		T4	3
valid_sources[0x48]	328991	1			T2	11		T3	713		T4	7
valid_sources[0x49]	282536	1			T3	736		T4	2		T9	290
valid_sources[0x4a]	262613	1			T1	61		T3	704		T4	2
valid_sources[0x4b]	254984	1			T2	12		T3	721		T4	4
valid_sources[0x4c]	287142	1			T1	50		T2	5		T3	717
valid_sources[0x4d]	277488	1			T1	24		T2	5		T3	713
valid_sources[0x4e]	265144	1			T1	32		T2	13		T3	693
valid_sources[0x4f]	283830	1			T1	42		T2	74		T3	741
valid_sources[0x50]	292488	1			T2	2		T3	736		T4	6
valid_sources[0x51]	327486	1			T2	5		T3	683		T4	4
valid_sources[0x52]	350864	1			T1	22		T3	707		T4	1
valid_sources[0x53]	313058	1			T1	7		T2	28		T3	718
valid_sources[0x54]	263232	1			T1	67		T2	54		T3	701
valid_sources[0x55]	315093	1			T2	14		T3	673		T4	2
valid_sources[0x56]	259489	1			T1	35		T2	34		T3	665
valid_sources[0x57]	267891	1			T1	46		T2	2		T3	669
valid_sources[0x58]	260235	1			T3	687		T4	4		T9	347
valid_sources[0x59]	273452	1			T1	24		T2	16		T3	700
valid_sources[0x5a]	261614	1			T1	17		T2	8		T3	669
valid_sources[0x5b]	288187	1			T1	9		T2	19		T3	716
valid_sources[0x5c]	269139	1			T2	56		T3	678		T4	8
valid_sources[0x5d]	251962	1			T1	22		T2	32		T3	732
valid_sources[0x5e]	263518	1			T1	20		T2	18		T3	733
valid_sources[0x5f]	329088	1			T2	19		T3	737		T4	4
valid_sources[0x60]	311779	1			T3	677		T4	7		T9	414
valid_sources[0x61]	278288	1			T2	9		T3	709		T4	4
valid_sources[0x62]	277260	1			T2	5		T3	649		T4	6
valid_sources[0x63]	259592	1			T1	17		T2	6		T3	706
valid_sources[0x64]	262222	1			T1	34		T2	14		T3	693
valid_sources[0x65]	282492	1			T1	17		T2	35		T3	719
valid_sources[0x66]	262378	1			T1	2		T2	13		T3	720
valid_sources[0x67]	258116	1			T2	7		T3	718		T4	7
valid_sources[0x68]	277101	1			T2	15		T3	731		T4	7
valid_sources[0x69]	272364	1			T1	7		T2	6		T3	687
valid_sources[0x6a]	264198	1			T1	7		T2	18		T3	708
valid_sources[0x6b]	327679	1			T2	35		T3	742		T4	3
valid_sources[0x6c]	275313	1			T2	7		T3	659		T4	6
valid_sources[0x6d]	345493	1			T1	15		T2	1		T3	686
valid_sources[0x6e]	310542	1			T1	40		T2	31		T3	760
valid_sources[0x6f]	295646	1			T2	48		T3	679		T4	4
valid_sources[0x70]	358406	1			T2	52		T3	670		T4	2
valid_sources[0x71]	289104	1			T2	42		T3	723		T4	6
valid_sources[0x72]	285063	1			T2	17		T3	719		T4	6
valid_sources[0x73]	332081	1			T2	50		T3	710		T4	6
valid_sources[0x74]	267763	1			T2	24		T3	661		T4	6
valid_sources[0x75]	271147	1			T2	8		T3	770		T4	7
valid_sources[0x76]	280649	1			T2	6		T3	694		T4	3
valid_sources[0x77]	332997	1			T1	16		T2	10		T3	695
valid_sources[0x78]	268667	1			T3	691		T4	6		T9	299
valid_sources[0x79]	271426	1			T2	26		T3	693		T4	4
valid_sources[0x7a]	302763	1			T1	15		T3	664		T4	4
valid_sources[0x7b]	283635	1			T3	649		T4	3		T8	4
valid_sources[0x7c]	275427	1			T1	11		T2	55		T3	708
valid_sources[0x7d]	273012	1			T1	5		T2	39		T3	683
valid_sources[0x7e]	275425	1			T1	31		T3	706		T4	7
valid_sources[0x7f]	266349	1			T1	6		T2	108		T3	665
valid_sources[0x80]	291795	1			T1	55		T3	719		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29581038

1

T1

1024

T2

1985

T3

80902

values[0x0]

all_enables

biggest_size

14891025

1

T1

1031

T2

1024

T3

40815

values[0x1]

all_enables

biggest_size

14904614

1

T1

1016

T2

1037

T3

40920

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

139430

1

T1

2

T2

1

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51208	1			T3	24		T13	21		T5	26
values[0x0]	60445	1			T1	3		T2	1		T3	45
values[0x1]	64750	1			T1	5		T2	1		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148374

1

T1

5

T2

1

T3

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	629	1			T24	2		T6	13		T28	6
valid_sources[0x01]	825	1			T24	7		T28	8		T29	13
valid_sources[0x02]	511	1			T24	6		T28	3		T20	1
valid_sources[0x03]	1060	1			T67	1		T24	10		T7	2
valid_sources[0x04]	606	1			T24	8		T29	20		T161	1
valid_sources[0x05]	502	1			T3	2		T67	1		T24	9
valid_sources[0x06]	728	1			T71	4		T24	2		T28	2
valid_sources[0x07]	609	1			T5	1		T24	4		T7	1
valid_sources[0x08]	660	1			T46	3		T24	4		T28	4
valid_sources[0x09]	873	1			T67	2		T24	18		T80	2
valid_sources[0x0a]	714	1			T75	1		T24	1		T28	1
valid_sources[0x0b]	650	1			T164	1		T24	4		T72	1
valid_sources[0x0c]	545	1			T3	1		T24	1		T7	1
valid_sources[0x0d]	716	1			T13	2		T71	1		T24	1
valid_sources[0x0e]	508	1			T67	1		T76	5		T24	5
valid_sources[0x0f]	547	1			T3	1		T24	3		T7	2
valid_sources[0x10]	696	1			T5	1		T67	1		T71	1
valid_sources[0x11]	793	1			T24	9		T28	2		T20	2
valid_sources[0x12]	705	1			T67	3		T24	1		T28	2
valid_sources[0x13]	690	1			T13	2		T5	1		T76	2
valid_sources[0x14]	608	1			T3	1		T5	1		T24	3
valid_sources[0x15]	477	1			T5	1		T160	1		T28	4
valid_sources[0x16]	1026	1			T13	2		T43	6		T5	1
valid_sources[0x17]	672	1			T13	1		T24	1		T7	1
valid_sources[0x18]	563	1			T67	4		T46	6		T24	3
valid_sources[0x19]	580	1			T72	1		T28	4		T159	2
valid_sources[0x1a]	691	1			T12	1		T13	3		T24	10
valid_sources[0x1b]	842	1			T5	4		T67	2		T24	18
valid_sources[0x1c]	1224	1			T71	5		T24	4		T72	1
valid_sources[0x1d]	1208	1			T67	1		T24	7		T7	2
valid_sources[0x1e]	723	1			T67	2		T71	1		T24	4
valid_sources[0x1f]	696	1			T67	1		T71	1		T24	1
valid_sources[0x20]	708	1			T24	6		T72	1		T28	2
valid_sources[0x21]	537	1			T5	2		T24	9		T28	2
valid_sources[0x22]	834	1			T3	1		T5	1		T24	13
valid_sources[0x23]	578	1			T5	2		T24	2		T28	2
valid_sources[0x24]	738	1			T5	1		T24	8		T7	2
valid_sources[0x25]	1161	1			T3	1		T13	6		T5	2
valid_sources[0x26]	572	1			T5	1		T55	2		T24	7
valid_sources[0x27]	467	1			T67	1		T55	2		T24	18
valid_sources[0x28]	439	1			T71	1		T75	1		T24	6
valid_sources[0x29]	533	1			T13	2		T5	2		T67	2
valid_sources[0x2a]	598	1			T5	1		T67	1		T24	16
valid_sources[0x2b]	624	1			T5	3		T24	4		T7	1
valid_sources[0x2c]	835	1			T67	2		T24	1		T77	96
valid_sources[0x2d]	860	1			T66	87		T46	6		T24	19
valid_sources[0x2e]	674	1			T71	3		T24	5		T7	1
valid_sources[0x2f]	714	1			T13	3		T67	1		T24	8
valid_sources[0x30]	762	1			T42	1		T24	3		T28	2
valid_sources[0x31]	523	1			T13	5		T71	2		T24	3
valid_sources[0x32]	503	1			T3	1		T24	9		T7	2
valid_sources[0x33]	506	1			T24	7		T7	1		T28	1
valid_sources[0x34]	588	1			T28	1		T29	13		T59	3
valid_sources[0x35]	728	1			T13	2		T67	1		T47	5
valid_sources[0x36]	791	1			T67	1		T45	1		T24	12
valid_sources[0x37]	746	1			T24	1		T28	4		T155	1
valid_sources[0x38]	787	1			T3	1		T13	2		T76	4
valid_sources[0x39]	1082	1			T3	10		T13	1		T24	2
valid_sources[0x3a]	646	1			T8	1		T67	1		T71	1
valid_sources[0x3b]	616	1			T5	1		T24	1		T28	6
valid_sources[0x3c]	790	1			T54	1		T76	1		T24	2
valid_sources[0x3d]	1072	1			T67	1		T45	1		T24	7
valid_sources[0x3e]	862	1			T44	1		T24	15		T6	7
valid_sources[0x3f]	800	1			T24	5		T28	5		T29	17
valid_sources[0x40]	690	1			T5	1		T46	6		T24	8
valid_sources[0x41]	744	1			T67	1		T24	4		T7	2
valid_sources[0x42]	853	1			T5	1		T45	3		T76	1
valid_sources[0x43]	719	1			T67	1		T7	1		T28	6
valid_sources[0x44]	630	1			T67	1		T71	1		T24	8
valid_sources[0x45]	611	1			T24	3		T7	1		T28	4
valid_sources[0x46]	645	1			T67	1		T24	13		T28	3
valid_sources[0x47]	699	1			T5	1		T71	2		T76	1
valid_sources[0x48]	910	1			T13	1		T67	1		T24	1
valid_sources[0x49]	563	1			T11	1		T5	1		T65	3
valid_sources[0x4a]	726	1			T24	4		T7	1		T28	3
valid_sources[0x4b]	652	1			T66	17		T24	7		T7	3
valid_sources[0x4c]	665	1			T14	18		T24	6		T28	1
valid_sources[0x4d]	645	1			T24	1		T72	1		T7	1
valid_sources[0x4e]	686	1			T24	2		T28	3		T29	16
valid_sources[0x4f]	707	1			T3	1		T13	2		T24	7
valid_sources[0x50]	539	1			T3	1		T67	3		T55	1
valid_sources[0x51]	694	1			T46	4		T24	11		T28	3
valid_sources[0x52]	569	1			T9	1		T76	2		T24	4
valid_sources[0x53]	546	1			T5	4		T67	4		T76	1
valid_sources[0x54]	508	1			T24	5		T6	1		T28	2
valid_sources[0x55]	481	1			T47	1		T76	1		T24	2
valid_sources[0x56]	738	1			T3	1		T71	1		T28	5
valid_sources[0x57]	746	1			T3	2		T9	1		T11	1
valid_sources[0x58]	778	1			T13	3		T5	2		T67	4
valid_sources[0x59]	533	1			T24	5		T7	1		T28	4
valid_sources[0x5a]	583	1			T13	5		T5	1		T54	1
valid_sources[0x5b]	532	1			T71	5		T7	1		T29	14
valid_sources[0x5c]	757	1			T5	3		T30	1		T76	4
valid_sources[0x5d]	600	1			T24	7		T28	4		T29	20
valid_sources[0x5e]	936	1			T9	1		T24	3		T28	1
valid_sources[0x5f]	615	1			T3	3		T24	3		T72	2
valid_sources[0x60]	701	1			T67	1		T24	34		T160	2
valid_sources[0x61]	528	1			T67	1		T24	2		T165	6
valid_sources[0x62]	725	1			T67	1		T47	1		T71	1
valid_sources[0x63]	676	1			T11	1		T13	2		T5	1
valid_sources[0x64]	626	1			T10	2		T24	6		T7	1
valid_sources[0x65]	681	1			T142	2		T94	4		T24	11
valid_sources[0x66]	720	1			T3	3		T13	1		T24	11
valid_sources[0x67]	601	1			T5	6		T67	5		T55	1
valid_sources[0x68]	858	1			T5	1		T47	1		T71	2
valid_sources[0x69]	550	1			T5	1		T24	9		T7	1
valid_sources[0x6a]	879	1			T67	2		T24	10		T6	2
valid_sources[0x6b]	798	1			T5	2		T67	1		T24	7
valid_sources[0x6c]	591	1			T24	14		T28	1		T100	1
valid_sources[0x6d]	572	1			T72	1		T28	1		T100	1
valid_sources[0x6e]	628	1			T67	3		T24	7		T160	1
valid_sources[0x6f]	983	1			T13	2		T67	1		T24	5
valid_sources[0x70]	884	1			T71	1		T24	5		T7	3
valid_sources[0x71]	607	1			T3	1		T24	8		T7	2
valid_sources[0x72]	603	1			T3	2		T5	1		T24	11
valid_sources[0x73]	597	1			T67	1		T24	10		T7	1
valid_sources[0x74]	959	1			T47	2		T24	5		T28	1
valid_sources[0x75]	693	1			T67	1		T24	2		T28	8
valid_sources[0x76]	572	1			T76	7		T24	14		T28	4
valid_sources[0x77]	1101	1			T5	1		T24	5		T6	2
valid_sources[0x78]	761	1			T5	2		T24	7		T7	1
valid_sources[0x79]	622	1			T55	1		T28	1		T100	2
valid_sources[0x7a]	472	1			T24	7		T29	21		T166	4
valid_sources[0x7b]	577	1			T67	1		T47	1		T24	3
valid_sources[0x7c]	952	1			T44	1		T75	2		T24	4
valid_sources[0x7d]	573	1			T3	1		T24	8		T28	6
valid_sources[0x7e]	647	1			T3	3		T5	2		T76	4
valid_sources[0x7f]	564	1			T13	4		T46	3		T75	1
valid_sources[0x80]	561	1			T5	1		T28	7		T21	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37932

1

T3

15

T13

8

T5

17

values[0x0]

all_enables

biggest_size

51773

1

T1

2

T2

1

T3

15

values[0x1]

all_enables

biggest_size

49725

1

T3

18

T4

1

T11

1