Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13871558

1

T2

838

T3

12924

T8

176

full_word

54098997

1

T1

3071

T2

4046

T3

130319

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67970235	1			T1	3071		T2	4884		T3	143243
auto[TlIntgErrCmd]	89	1			T69	7		T70	4		T143	6
auto[TlIntgErrData]	130	1			T68	6		T69	7		T70	3
auto[TlIntgErrBoth]	101	1			T68	4		T69	6		T70	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30996569

1

T1

1024

T2

2405

T3

53455

auto[1]

36973986

1

T1

2047

T2

2479

T3

89788

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6617548	1			T2	420		T3	4871		T8	99
auto[TlIntgErrNone]	partial	auto[1]	7253716	1			T2	418		T3	8053		T8	77
auto[TlIntgErrNone]	full_word	auto[0]	24378867	1			T1	1024		T2	1985		T3	48584
auto[TlIntgErrNone]	full_word	auto[1]	29720104	1			T1	2047		T2	2061		T3	81735
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T69	4		T70	3		T143	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T69	3		T70	1		T143	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T149	1		T147	1		T153	3
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T154	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T68	2		T69	4		T143	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T68	4		T69	2		T70	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T69	1		T150	1		T152	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T143	1		T152	2		T144	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T68	1		T69	1		T70	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T68	3		T69	4		T70	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T150	1		T154	2		T145	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T69	1		T147	1		-	-