Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	694950	1			T3	19		T13	23		T5	2504
auto[1]	10008734	1			T2	2404		T3	414		T4	624
auto[2]	591114	1			T3	30		T13	26		T5	2309
auto[3]	9915620	1			T2	2478		T3	409		T4	635

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13918773	1			T2	3399		T3	599		T4	1259
auto[1]	1990073	1			T2	645		T3	97		T9	6503
auto[2]	2026145	1			T2	704		T3	155		T9	6604
auto[3]	3275427	1			T2	134		T3	21		T9	661

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8506388

1

T2

4876

T3

870

T4

1258

auto[1]

12704030

1

T2

6

T3

2

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	254205	1			T3	15		T13	18		T5	2077
auto[0]	auto[0]	auto[1]	26763	1			T13	3		T5	208		T66	53
auto[0]	auto[0]	auto[2]	26788	1			T3	3		T13	2		T5	197
auto[0]	auto[0]	auto[3]	9472	1			T3	1		T5	21		T66	7
auto[0]	auto[1]	auto[0]	3244624	1			T2	1676		T3	313		T4	624
auto[0]	auto[1]	auto[1]	336113	1			T2	304		T3	66		T10	120
auto[0]	auto[1]	auto[2]	326518	1			T2	362		T3	29		T10	111
auto[0]	auto[1]	auto[3]	68864	1			T2	58		T3	5		T10	24
auto[0]	auto[2]	auto[0]	217175	1			T5	1939		T66	380		T71	374
auto[0]	auto[2]	auto[1]	22743	1			T5	193		T66	42		T71	38
auto[0]	auto[2]	auto[2]	26254	1			T3	27		T13	22		T5	160
auto[0]	auto[2]	auto[3]	7978	1			T3	3		T13	4		T5	15
auto[0]	auto[3]	auto[0]	3210477	1			T2	1718		T3	269		T4	634
auto[0]	auto[3]	auto[1]	323164	1			T2	341		T3	31		T10	119
auto[0]	auto[3]	auto[2]	335994	1			T2	341		T3	96		T10	119
auto[0]	auto[3]	auto[3]	69256	1			T2	76		T3	12		T10	29
auto[1]	auto[0]	auto[0]	12607	1			T5	1		T66	1		T159	5
auto[1]	auto[0]	auto[1]	55827	1			T160	1		T20	2		T161	2
auto[1]	auto[0]	auto[2]	55953	1			T20	2		T161	1		T36	1700
auto[1]	auto[0]	auto[3]	253335	1			T99	1		T36	7256		T158	18080
auto[1]	auto[1]	auto[0]	3487090	1			T2	4		T3	1		T9	33245
auto[1]	auto[1]	auto[1]	613971	1			T9	3303		T54	7179		T65	16297
auto[1]	auto[1]	auto[2]	595684	1			T9	3321		T26	1		T54	7213
auto[1]	auto[1]	auto[3]	1335870	1			T9	335		T54	713		T65	72947
auto[1]	auto[2]	auto[0]	8339	1			T5	1		T159	1		T20	5
auto[1]	auto[2]	auto[1]	36901	1			T5	1		T159	2		T20	1
auto[1]	auto[2]	auto[2]	49363	1			T160	1		T159	1		T20	1
auto[1]	auto[2]	auto[3]	222361	1			T36	8110		T158	15321		T162	1869
auto[1]	auto[3]	auto[0]	3484256	1			T2	1		T3	1		T4	1
auto[1]	auto[3]	auto[1]	574591	1			T9	3200		T26	1		T54	7164
auto[1]	auto[3]	auto[2]	609591	1			T2	1		T9	3283		T5	1
auto[1]	auto[3]	auto[3]	1308291	1			T9	326		T54	721		T65	72602