Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	323167003	200986	0	0
ctrl_regwen_rd_A	323167003	4082	0	0
exec_rd_A	323167003	3587	0	0
exec_regwen_rd_A	323167003	4134	0	0
readback_rd_A	323167003	2743	0	0
readback_regwen_rd_A	323167003	2356	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323167003	200986	0	0
T6	65199	0	0	0
T24	92457	2978	0	0
T28	0	1286	0	0
T29	0	4934	0	0
T48	0	3253	0	0
T59	0	5550	0	0
T61	0	6098	0	0
T62	0	3980	0	0
T63	0	1088	0	0
T72	313592	0	0	0
T77	408919	0	0	0
T78	0	10314	0	0
T79	0	3982	0	0
T80	4798	0	0	0
T81	12995	0	0	0
T82	56752	0	0	0
T83	15465	0	0	0
T84	206181	0	0	0
T85	12113	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323167003	4082	0	0
T49	0	91	0	0
T63	17778	94	0	0
T79	0	210	0	0
T126	0	256	0	0
T127	0	247	0	0
T128	0	260	0	0
T129	0	111	0	0
T130	0	119	0	0
T131	0	169	0	0
T132	0	231	0	0
T133	8797	0	0	0
T134	2312	0	0	0
T135	1818	0	0	0
T136	82886	0	0	0
T137	524176	0	0	0
T138	216477	0	0	0
T139	231562	0	0	0
T140	134495	0	0	0
T141	217194	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323167003	3587	0	0
T49	0	96	0	0
T63	17778	79	0	0
T79	0	204	0	0
T126	0	152	0	0
T127	0	158	0	0
T128	0	194	0	0
T129	0	106	0	0
T130	0	104	0	0
T131	0	157	0	0
T132	0	176	0	0
T133	8797	0	0	0
T134	2312	0	0	0
T135	1818	0	0	0
T136	82886	0	0	0
T137	524176	0	0	0
T138	216477	0	0	0
T139	231562	0	0	0
T140	134495	0	0	0
T141	217194	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323167003	4134	0	0
T49	0	123	0	0
T63	17778	92	0	0
T79	0	200	0	0
T126	0	241	0	0
T127	0	248	0	0
T128	0	212	0	0
T129	0	98	0	0
T130	0	85	0	0
T131	0	198	0	0
T132	0	285	0	0
T133	8797	0	0	0
T134	2312	0	0	0
T135	1818	0	0	0
T136	82886	0	0	0
T137	524176	0	0	0
T138	216477	0	0	0
T139	231562	0	0	0
T140	134495	0	0	0
T141	217194	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323167003	2743	0	0
T49	0	83	0	0
T63	17778	83	0	0
T79	0	226	0	0
T126	0	250	0	0
T127	0	164	0	0
T128	0	200	0	0
T129	0	107	0	0
T130	0	133	0	0
T131	0	106	0	0
T132	0	280	0	0
T133	8797	0	0	0
T134	2312	0	0	0
T135	1818	0	0	0
T136	82886	0	0	0
T137	524176	0	0	0
T138	216477	0	0	0
T139	231562	0	0	0
T140	134495	0	0	0
T141	217194	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323167003	2356	0	0
T49	0	120	0	0
T63	17778	45	0	0
T79	0	163	0	0
T126	0	116	0	0
T127	0	182	0	0
T128	0	110	0	0
T129	0	91	0	0
T130	0	51	0	0
T131	0	111	0	0
T132	0	271	0	0
T133	8797	0	0	0
T134	2312	0	0	0
T135	1818	0	0	0
T136	82886	0	0	0
T137	524176	0	0	0
T138	216477	0	0	0
T139	231562	0	0	0
T140	134495	0	0	0
T141	217194	0	0	0