| T800 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1288384261 |
|
|
Jul 14 04:57:07 PM PDT 24 |
Jul 14 05:13:20 PM PDT 24 |
30485286443 ps |
| T801 |
/workspace/coverage/default/36.sram_ctrl_bijection.2856639636 |
|
|
Jul 14 05:00:03 PM PDT 24 |
Jul 14 05:01:16 PM PDT 24 |
4506295809 ps |
| T802 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3924495798 |
|
|
Jul 14 04:58:33 PM PDT 24 |
Jul 14 05:02:36 PM PDT 24 |
4882393386 ps |
| T803 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3710849832 |
|
|
Jul 14 04:56:21 PM PDT 24 |
Jul 14 05:13:35 PM PDT 24 |
251443277106 ps |
| T804 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4105504290 |
|
|
Jul 14 04:59:34 PM PDT 24 |
Jul 14 05:04:26 PM PDT 24 |
3833917703 ps |
| T805 |
/workspace/coverage/default/37.sram_ctrl_alert_test.4160875915 |
|
|
Jul 14 05:00:31 PM PDT 24 |
Jul 14 05:00:32 PM PDT 24 |
48070047 ps |
| T806 |
/workspace/coverage/default/27.sram_ctrl_regwen.3270426801 |
|
|
Jul 14 04:57:42 PM PDT 24 |
Jul 14 05:22:24 PM PDT 24 |
10289478038 ps |
| T807 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.3772475141 |
|
|
Jul 14 04:58:38 PM PDT 24 |
Jul 14 04:58:50 PM PDT 24 |
1519300267 ps |
| T808 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1207024674 |
|
|
Jul 14 04:56:30 PM PDT 24 |
Jul 14 04:56:31 PM PDT 24 |
17184964 ps |
| T809 |
/workspace/coverage/default/48.sram_ctrl_bijection.2591983484 |
|
|
Jul 14 05:03:37 PM PDT 24 |
Jul 14 05:03:59 PM PDT 24 |
1991333836 ps |
| T810 |
/workspace/coverage/default/26.sram_ctrl_alert_test.802881565 |
|
|
Jul 14 04:57:37 PM PDT 24 |
Jul 14 04:57:39 PM PDT 24 |
34679822 ps |
| T811 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1668391276 |
|
|
Jul 14 05:01:08 PM PDT 24 |
Jul 14 05:01:10 PM PDT 24 |
147692512 ps |
| T812 |
/workspace/coverage/default/13.sram_ctrl_stress_all.3820198589 |
|
|
Jul 14 04:55:15 PM PDT 24 |
Jul 14 05:31:29 PM PDT 24 |
35233205359 ps |
| T813 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3637618551 |
|
|
Jul 14 04:54:37 PM PDT 24 |
Jul 14 04:55:40 PM PDT 24 |
158561174 ps |
| T132 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.942364313 |
|
|
Jul 14 04:58:02 PM PDT 24 |
Jul 14 04:58:37 PM PDT 24 |
2259460294 ps |
| T814 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1746300482 |
|
|
Jul 14 04:58:26 PM PDT 24 |
Jul 14 05:06:19 PM PDT 24 |
6250047333 ps |
| T815 |
/workspace/coverage/default/7.sram_ctrl_executable.2274865641 |
|
|
Jul 14 04:54:22 PM PDT 24 |
Jul 14 05:11:37 PM PDT 24 |
30216969290 ps |
| T816 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.379971596 |
|
|
Jul 14 04:56:39 PM PDT 24 |
Jul 14 04:56:45 PM PDT 24 |
815655478 ps |
| T50 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2490435289 |
|
|
Jul 14 05:03:31 PM PDT 24 |
Jul 14 05:04:09 PM PDT 24 |
2339925612 ps |
| T817 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.451636199 |
|
|
Jul 14 04:54:38 PM PDT 24 |
Jul 14 04:54:47 PM PDT 24 |
2675378098 ps |
| T818 |
/workspace/coverage/default/17.sram_ctrl_smoke.896331100 |
|
|
Jul 14 04:55:39 PM PDT 24 |
Jul 14 04:56:46 PM PDT 24 |
7840894875 ps |
| T819 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3706158447 |
|
|
Jul 14 04:54:50 PM PDT 24 |
Jul 14 05:02:04 PM PDT 24 |
23256605871 ps |
| T820 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.4091308664 |
|
|
Jul 14 04:57:18 PM PDT 24 |
Jul 14 04:57:23 PM PDT 24 |
461930686 ps |
| T821 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2768597451 |
|
|
Jul 14 04:54:33 PM PDT 24 |
Jul 14 05:22:47 PM PDT 24 |
8202892734 ps |
| T822 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1149624332 |
|
|
Jul 14 05:03:58 PM PDT 24 |
Jul 14 05:11:15 PM PDT 24 |
117936577195 ps |
| T823 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1666233980 |
|
|
Jul 14 04:55:24 PM PDT 24 |
Jul 14 04:56:02 PM PDT 24 |
162670638 ps |
| T824 |
/workspace/coverage/default/45.sram_ctrl_bijection.2920044184 |
|
|
Jul 14 05:02:40 PM PDT 24 |
Jul 14 05:03:30 PM PDT 24 |
3153509259 ps |
| T825 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2892697148 |
|
|
Jul 14 04:56:51 PM PDT 24 |
Jul 14 04:56:58 PM PDT 24 |
2589435869 ps |
| T826 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.3906553966 |
|
|
Jul 14 04:55:34 PM PDT 24 |
Jul 14 05:03:48 PM PDT 24 |
2922038764 ps |
| T827 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1438235467 |
|
|
Jul 14 05:01:33 PM PDT 24 |
Jul 14 05:01:42 PM PDT 24 |
247452186 ps |
| T32 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2911486343 |
|
|
Jul 14 04:54:02 PM PDT 24 |
Jul 14 04:54:05 PM PDT 24 |
199883615 ps |
| T828 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2015405996 |
|
|
Jul 14 04:58:09 PM PDT 24 |
Jul 14 05:00:18 PM PDT 24 |
512017987 ps |
| T829 |
/workspace/coverage/default/5.sram_ctrl_executable.1509401612 |
|
|
Jul 14 04:54:14 PM PDT 24 |
Jul 14 05:14:35 PM PDT 24 |
4317466425 ps |
| T830 |
/workspace/coverage/default/22.sram_ctrl_smoke.2035938865 |
|
|
Jul 14 04:56:30 PM PDT 24 |
Jul 14 04:56:36 PM PDT 24 |
270576533 ps |
| T106 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.662425278 |
|
|
Jul 14 05:01:24 PM PDT 24 |
Jul 14 05:01:31 PM PDT 24 |
732611945 ps |
| T831 |
/workspace/coverage/default/12.sram_ctrl_bijection.3976324253 |
|
|
Jul 14 04:55:00 PM PDT 24 |
Jul 14 04:55:44 PM PDT 24 |
2385769143 ps |
| T33 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2332501403 |
|
|
Jul 14 04:53:53 PM PDT 24 |
Jul 14 04:53:56 PM PDT 24 |
346685943 ps |
| T832 |
/workspace/coverage/default/1.sram_ctrl_bijection.3539459033 |
|
|
Jul 14 04:53:53 PM PDT 24 |
Jul 14 04:54:54 PM PDT 24 |
16530327866 ps |
| T833 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.475446841 |
|
|
Jul 14 05:02:29 PM PDT 24 |
Jul 14 05:02:33 PM PDT 24 |
514099799 ps |
| T834 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2293502204 |
|
|
Jul 14 04:54:20 PM PDT 24 |
Jul 14 04:54:45 PM PDT 24 |
780125123 ps |
| T835 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3221592694 |
|
|
Jul 14 04:59:13 PM PDT 24 |
Jul 14 04:59:15 PM PDT 24 |
78320045 ps |
| T836 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1601950763 |
|
|
Jul 14 04:54:31 PM PDT 24 |
Jul 14 04:54:32 PM PDT 24 |
30174569 ps |
| T837 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3466695849 |
|
|
Jul 14 05:03:44 PM PDT 24 |
Jul 14 05:04:14 PM PDT 24 |
83715793 ps |
| T838 |
/workspace/coverage/default/45.sram_ctrl_smoke.4271835602 |
|
|
Jul 14 05:02:40 PM PDT 24 |
Jul 14 05:02:41 PM PDT 24 |
48294694 ps |
| T839 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1044889116 |
|
|
Jul 14 04:53:54 PM PDT 24 |
Jul 14 04:53:56 PM PDT 24 |
79601337 ps |
| T840 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.705813962 |
|
|
Jul 14 04:55:01 PM PDT 24 |
Jul 14 04:59:41 PM PDT 24 |
3659961731 ps |
| T841 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4190886667 |
|
|
Jul 14 05:01:03 PM PDT 24 |
Jul 14 05:16:54 PM PDT 24 |
2109526252 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.85737317 |
|
|
Jul 14 04:55:27 PM PDT 24 |
Jul 14 05:02:26 PM PDT 24 |
5693824811 ps |
| T843 |
/workspace/coverage/default/32.sram_ctrl_partial_access.236846885 |
|
|
Jul 14 04:58:46 PM PDT 24 |
Jul 14 04:58:52 PM PDT 24 |
318277671 ps |
| T844 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.4179623179 |
|
|
Jul 14 05:00:04 PM PDT 24 |
Jul 14 05:05:38 PM PDT 24 |
35976258537 ps |
| T845 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3434608417 |
|
|
Jul 14 04:58:09 PM PDT 24 |
Jul 14 05:13:21 PM PDT 24 |
43765833278 ps |
| T846 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1497386410 |
|
|
Jul 14 05:01:42 PM PDT 24 |
Jul 14 05:06:14 PM PDT 24 |
4532812993 ps |
| T847 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3336234441 |
|
|
Jul 14 04:54:21 PM PDT 24 |
Jul 14 04:54:40 PM PDT 24 |
85846812 ps |
| T848 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3579560036 |
|
|
Jul 14 04:55:49 PM PDT 24 |
Jul 14 06:15:53 PM PDT 24 |
84459517538 ps |
| T849 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2363935963 |
|
|
Jul 14 04:59:19 PM PDT 24 |
Jul 14 04:59:50 PM PDT 24 |
4416410283 ps |
| T850 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2301894942 |
|
|
Jul 14 04:59:20 PM PDT 24 |
Jul 14 04:59:49 PM PDT 24 |
410170900 ps |
| T851 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3586623869 |
|
|
Jul 14 04:57:07 PM PDT 24 |
Jul 14 04:59:42 PM PDT 24 |
477717195 ps |
| T852 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2300681420 |
|
|
Jul 14 04:53:49 PM PDT 24 |
Jul 14 04:53:58 PM PDT 24 |
687345029 ps |
| T853 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.4213561392 |
|
|
Jul 14 04:56:06 PM PDT 24 |
Jul 14 04:56:12 PM PDT 24 |
910373421 ps |
| T854 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3135969158 |
|
|
Jul 14 05:01:43 PM PDT 24 |
Jul 14 06:24:19 PM PDT 24 |
222828613851 ps |
| T855 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2835131663 |
|
|
Jul 14 04:53:47 PM PDT 24 |
Jul 14 05:01:59 PM PDT 24 |
6578305891 ps |
| T856 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3938619992 |
|
|
Jul 14 04:54:16 PM PDT 24 |
Jul 14 04:54:23 PM PDT 24 |
344175140 ps |
| T857 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3547427836 |
|
|
Jul 14 04:54:39 PM PDT 24 |
Jul 14 04:54:45 PM PDT 24 |
1118927827 ps |
| T858 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2477345632 |
|
|
Jul 14 04:58:38 PM PDT 24 |
Jul 14 04:58:39 PM PDT 24 |
13588792 ps |
| T859 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3254450954 |
|
|
Jul 14 04:54:01 PM PDT 24 |
Jul 14 05:16:42 PM PDT 24 |
3240891952 ps |
| T860 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3800710392 |
|
|
Jul 14 04:58:20 PM PDT 24 |
Jul 14 04:58:26 PM PDT 24 |
493513482 ps |
| T861 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1440408300 |
|
|
Jul 14 05:01:42 PM PDT 24 |
Jul 14 05:01:45 PM PDT 24 |
236092073 ps |
| T862 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2622808501 |
|
|
Jul 14 05:01:55 PM PDT 24 |
Jul 14 05:01:59 PM PDT 24 |
383387203 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.245258887 |
|
|
Jul 14 04:59:14 PM PDT 24 |
Jul 14 05:00:33 PM PDT 24 |
115332722 ps |
| T864 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3820598657 |
|
|
Jul 14 05:02:55 PM PDT 24 |
Jul 14 05:03:05 PM PDT 24 |
186448542 ps |
| T865 |
/workspace/coverage/default/43.sram_ctrl_smoke.4147783785 |
|
|
Jul 14 05:02:08 PM PDT 24 |
Jul 14 05:02:26 PM PDT 24 |
766655268 ps |
| T866 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2656855022 |
|
|
Jul 14 04:56:13 PM PDT 24 |
Jul 14 05:10:08 PM PDT 24 |
5130602956 ps |
| T867 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2222995372 |
|
|
Jul 14 04:54:56 PM PDT 24 |
Jul 14 05:00:19 PM PDT 24 |
3457825341 ps |
| T868 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3846873867 |
|
|
Jul 14 04:55:33 PM PDT 24 |
Jul 14 04:58:59 PM PDT 24 |
8492524551 ps |
| T869 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.4080947318 |
|
|
Jul 14 05:01:57 PM PDT 24 |
Jul 14 05:01:58 PM PDT 24 |
28066895 ps |
| T870 |
/workspace/coverage/default/40.sram_ctrl_bijection.3898886998 |
|
|
Jul 14 05:01:03 PM PDT 24 |
Jul 14 05:01:23 PM PDT 24 |
874055544 ps |
| T871 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3104278389 |
|
|
Jul 14 04:53:45 PM PDT 24 |
Jul 14 04:53:51 PM PDT 24 |
748519029 ps |
| T872 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.119568518 |
|
|
Jul 14 05:00:53 PM PDT 24 |
Jul 14 05:03:41 PM PDT 24 |
811154139 ps |
| T873 |
/workspace/coverage/default/0.sram_ctrl_bijection.2071816846 |
|
|
Jul 14 04:53:45 PM PDT 24 |
Jul 14 04:54:33 PM PDT 24 |
20690033416 ps |
| T874 |
/workspace/coverage/default/3.sram_ctrl_bijection.259773749 |
|
|
Jul 14 04:54:00 PM PDT 24 |
Jul 14 04:54:18 PM PDT 24 |
780234589 ps |
| T875 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2314928570 |
|
|
Jul 14 05:00:54 PM PDT 24 |
Jul 14 05:27:53 PM PDT 24 |
18836260210 ps |
| T876 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1310081561 |
|
|
Jul 14 04:54:13 PM PDT 24 |
Jul 14 04:54:16 PM PDT 24 |
623074380 ps |
| T877 |
/workspace/coverage/default/40.sram_ctrl_executable.1889085197 |
|
|
Jul 14 05:01:10 PM PDT 24 |
Jul 14 05:17:48 PM PDT 24 |
33671857627 ps |
| T878 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1624684796 |
|
|
Jul 14 04:55:09 PM PDT 24 |
Jul 14 05:10:14 PM PDT 24 |
2466492203 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3556679750 |
|
|
Jul 14 04:59:56 PM PDT 24 |
Jul 14 05:04:11 PM PDT 24 |
4224663713 ps |
| T880 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.173601735 |
|
|
Jul 14 04:58:35 PM PDT 24 |
Jul 14 04:58:39 PM PDT 24 |
354667559 ps |
| T881 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.588485014 |
|
|
Jul 14 04:56:32 PM PDT 24 |
Jul 14 04:56:35 PM PDT 24 |
266387511 ps |
| T882 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3704174074 |
|
|
Jul 14 04:58:18 PM PDT 24 |
Jul 14 05:08:21 PM PDT 24 |
2304409973 ps |
| T883 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2361643236 |
|
|
Jul 14 04:56:01 PM PDT 24 |
Jul 14 04:56:35 PM PDT 24 |
229512737 ps |
| T884 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2890954297 |
|
|
Jul 14 05:03:04 PM PDT 24 |
Jul 14 05:06:02 PM PDT 24 |
1850287068 ps |
| T885 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2548653089 |
|
|
Jul 14 05:04:05 PM PDT 24 |
Jul 14 05:04:13 PM PDT 24 |
480532664 ps |
| T886 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3099612444 |
|
|
Jul 14 04:54:17 PM PDT 24 |
Jul 14 05:56:38 PM PDT 24 |
27182170102 ps |
| T887 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1820226751 |
|
|
Jul 14 05:02:22 PM PDT 24 |
Jul 14 05:05:44 PM PDT 24 |
29746936247 ps |
| T888 |
/workspace/coverage/default/44.sram_ctrl_alert_test.989993895 |
|
|
Jul 14 05:02:34 PM PDT 24 |
Jul 14 05:02:35 PM PDT 24 |
17448585 ps |
| T889 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4250610715 |
|
|
Jul 14 05:02:33 PM PDT 24 |
Jul 14 05:05:11 PM PDT 24 |
1140566804 ps |
| T890 |
/workspace/coverage/default/33.sram_ctrl_smoke.1470022637 |
|
|
Jul 14 04:59:07 PM PDT 24 |
Jul 14 04:59:15 PM PDT 24 |
584178682 ps |
| T891 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2671932152 |
|
|
Jul 14 04:53:47 PM PDT 24 |
Jul 14 05:15:18 PM PDT 24 |
5568602514 ps |
| T892 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2150518729 |
|
|
Jul 14 04:57:33 PM PDT 24 |
Jul 14 05:21:32 PM PDT 24 |
17038582572 ps |
| T893 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3174807254 |
|
|
Jul 14 04:56:39 PM PDT 24 |
Jul 14 05:03:36 PM PDT 24 |
4470774775 ps |
| T894 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2069090572 |
|
|
Jul 14 05:03:02 PM PDT 24 |
Jul 14 05:03:05 PM PDT 24 |
163215237 ps |
| T895 |
/workspace/coverage/default/3.sram_ctrl_regwen.864142176 |
|
|
Jul 14 04:54:02 PM PDT 24 |
Jul 14 05:14:17 PM PDT 24 |
25067006060 ps |
| T896 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1233020871 |
|
|
Jul 14 04:54:15 PM PDT 24 |
Jul 14 04:59:02 PM PDT 24 |
7691455304 ps |
| T897 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1723770551 |
|
|
Jul 14 05:00:32 PM PDT 24 |
Jul 14 05:00:54 PM PDT 24 |
254360834 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1199600081 |
|
|
Jul 14 04:54:50 PM PDT 24 |
Jul 14 04:58:43 PM PDT 24 |
17631189785 ps |
| T899 |
/workspace/coverage/default/6.sram_ctrl_regwen.1889794662 |
|
|
Jul 14 04:54:22 PM PDT 24 |
Jul 14 05:08:38 PM PDT 24 |
14191256448 ps |
| T900 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3650660437 |
|
|
Jul 14 04:53:45 PM PDT 24 |
Jul 14 04:54:50 PM PDT 24 |
123437084 ps |
| T901 |
/workspace/coverage/default/35.sram_ctrl_stress_all.2382992445 |
|
|
Jul 14 04:59:54 PM PDT 24 |
Jul 14 05:34:04 PM PDT 24 |
4741369057 ps |
| T902 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1930375286 |
|
|
Jul 14 04:57:43 PM PDT 24 |
Jul 14 04:57:45 PM PDT 24 |
338709081 ps |
| T903 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.776363722 |
|
|
Jul 14 04:54:25 PM PDT 24 |
Jul 14 05:08:11 PM PDT 24 |
16389615101 ps |
| T904 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2067089384 |
|
|
Jul 14 04:53:54 PM PDT 24 |
Jul 14 05:14:15 PM PDT 24 |
114223981455 ps |
| T905 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.116392170 |
|
|
Jul 14 04:57:37 PM PDT 24 |
Jul 14 04:57:49 PM PDT 24 |
659362862 ps |
| T906 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3997340057 |
|
|
Jul 14 04:53:55 PM PDT 24 |
Jul 14 04:53:58 PM PDT 24 |
565227907 ps |
| T907 |
/workspace/coverage/default/23.sram_ctrl_smoke.1428507596 |
|
|
Jul 14 04:56:44 PM PDT 24 |
Jul 14 04:57:42 PM PDT 24 |
385956598 ps |
| T908 |
/workspace/coverage/default/4.sram_ctrl_regwen.3936849633 |
|
|
Jul 14 04:54:15 PM PDT 24 |
Jul 14 05:21:56 PM PDT 24 |
10022899799 ps |
| T909 |
/workspace/coverage/default/48.sram_ctrl_alert_test.756367248 |
|
|
Jul 14 05:03:52 PM PDT 24 |
Jul 14 05:03:53 PM PDT 24 |
12792334 ps |
| T910 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.675484671 |
|
|
Jul 14 05:00:43 PM PDT 24 |
Jul 14 05:00:48 PM PDT 24 |
606905330 ps |
| T911 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2291490120 |
|
|
Jul 14 04:54:50 PM PDT 24 |
Jul 14 05:17:46 PM PDT 24 |
27472219596 ps |
| T912 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1857500703 |
|
|
Jul 14 04:58:45 PM PDT 24 |
Jul 14 04:59:25 PM PDT 24 |
844759096 ps |
| T913 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3477851579 |
|
|
Jul 14 04:57:18 PM PDT 24 |
Jul 14 04:59:50 PM PDT 24 |
134398238 ps |
| T914 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.104681547 |
|
|
Jul 14 05:00:54 PM PDT 24 |
Jul 14 05:06:04 PM PDT 24 |
103845032304 ps |
| T915 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.4202752919 |
|
|
Jul 14 05:00:18 PM PDT 24 |
Jul 14 05:02:01 PM PDT 24 |
472196293 ps |
| T916 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.604253342 |
|
|
Jul 14 04:56:26 PM PDT 24 |
Jul 14 04:57:22 PM PDT 24 |
1024723105 ps |
| T917 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1194187654 |
|
|
Jul 14 05:00:38 PM PDT 24 |
Jul 14 05:00:39 PM PDT 24 |
88752675 ps |
| T918 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3984307711 |
|
|
Jul 14 05:01:49 PM PDT 24 |
Jul 14 05:01:54 PM PDT 24 |
287076332 ps |
| T919 |
/workspace/coverage/default/37.sram_ctrl_executable.362263172 |
|
|
Jul 14 05:00:22 PM PDT 24 |
Jul 14 05:07:13 PM PDT 24 |
6541085237 ps |
| T920 |
/workspace/coverage/default/21.sram_ctrl_smoke.1202104333 |
|
|
Jul 14 04:56:19 PM PDT 24 |
Jul 14 04:56:32 PM PDT 24 |
217030259 ps |
| T921 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2115938334 |
|
|
Jul 14 04:59:41 PM PDT 24 |
Jul 14 04:59:47 PM PDT 24 |
469488958 ps |
| T922 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1154248033 |
|
|
Jul 14 04:57:17 PM PDT 24 |
Jul 14 04:59:47 PM PDT 24 |
3305838935 ps |
| T923 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3447874582 |
|
|
Jul 14 05:03:19 PM PDT 24 |
Jul 14 05:47:24 PM PDT 24 |
8612222029 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.2421752877 |
|
|
Jul 14 04:58:35 PM PDT 24 |
Jul 14 04:59:58 PM PDT 24 |
127435131 ps |
| T925 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.344956315 |
|
|
Jul 14 04:56:03 PM PDT 24 |
Jul 14 04:58:25 PM PDT 24 |
3146263986 ps |
| T926 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2380748001 |
|
|
Jul 14 04:54:17 PM PDT 24 |
Jul 14 04:54:21 PM PDT 24 |
346676190 ps |
| T927 |
/workspace/coverage/default/18.sram_ctrl_executable.2850464231 |
|
|
Jul 14 04:55:59 PM PDT 24 |
Jul 14 05:26:30 PM PDT 24 |
165901672487 ps |
| T928 |
/workspace/coverage/default/5.sram_ctrl_smoke.4169736177 |
|
|
Jul 14 04:54:16 PM PDT 24 |
Jul 14 04:55:19 PM PDT 24 |
397391434 ps |
| T929 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2999830058 |
|
|
Jul 14 04:56:16 PM PDT 24 |
Jul 14 05:04:31 PM PDT 24 |
43827072809 ps |
| T930 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2642419643 |
|
|
Jul 14 04:57:25 PM PDT 24 |
Jul 14 05:49:27 PM PDT 24 |
17742633362 ps |
| T931 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1213772833 |
|
|
Jul 14 05:01:12 PM PDT 24 |
Jul 14 05:06:48 PM PDT 24 |
29344144142 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2842127679 |
|
|
Jul 14 05:03:54 PM PDT 24 |
Jul 14 05:03:55 PM PDT 24 |
278273766 ps |
| T933 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1041936194 |
|
|
Jul 14 04:54:14 PM PDT 24 |
Jul 14 04:54:20 PM PDT 24 |
53612765 ps |
| T934 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2749007788 |
|
|
Jul 14 04:55:07 PM PDT 24 |
Jul 14 04:55:22 PM PDT 24 |
70714148 ps |
| T935 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2080605256 |
|
|
Jul 14 04:55:27 PM PDT 24 |
Jul 14 04:58:00 PM PDT 24 |
250797273 ps |
| T936 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2934233232 |
|
|
Jul 14 04:58:18 PM PDT 24 |
Jul 14 05:00:14 PM PDT 24 |
192138837 ps |
| T937 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3141503643 |
|
|
Jul 14 04:51:42 PM PDT 24 |
Jul 14 04:51:47 PM PDT 24 |
507125006 ps |
| T938 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3142117356 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:31 PM PDT 24 |
134814778 ps |
| T939 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.636146726 |
|
|
Jul 14 04:52:37 PM PDT 24 |
Jul 14 04:52:40 PM PDT 24 |
200156340 ps |
| T940 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4197451057 |
|
|
Jul 14 04:52:38 PM PDT 24 |
Jul 14 04:52:41 PM PDT 24 |
73960937 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1660970779 |
|
|
Jul 14 04:51:48 PM PDT 24 |
Jul 14 04:51:51 PM PDT 24 |
433103120 ps |
| T941 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2579772171 |
|
|
Jul 14 04:52:48 PM PDT 24 |
Jul 14 04:52:51 PM PDT 24 |
410164705 ps |
| T73 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3074492268 |
|
|
Jul 14 04:52:35 PM PDT 24 |
Jul 14 04:52:36 PM PDT 24 |
20013685 ps |
| T74 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.924986181 |
|
|
Jul 14 04:52:30 PM PDT 24 |
Jul 14 04:52:33 PM PDT 24 |
233624091 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2424529056 |
|
|
Jul 14 04:51:49 PM PDT 24 |
Jul 14 04:51:51 PM PDT 24 |
41589905 ps |
| T118 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1509754581 |
|
|
Jul 14 04:52:38 PM PDT 24 |
Jul 14 04:52:39 PM PDT 24 |
40304827 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.554633499 |
|
|
Jul 14 04:51:43 PM PDT 24 |
Jul 14 04:51:44 PM PDT 24 |
41401202 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3046943743 |
|
|
Jul 14 04:52:36 PM PDT 24 |
Jul 14 04:52:39 PM PDT 24 |
269705434 ps |
| T70 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3561470373 |
|
|
Jul 14 04:52:02 PM PDT 24 |
Jul 14 04:52:03 PM PDT 24 |
97986095 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3016054786 |
|
|
Jul 14 04:51:48 PM PDT 24 |
Jul 14 04:51:51 PM PDT 24 |
352907335 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2289132937 |
|
|
Jul 14 04:52:17 PM PDT 24 |
Jul 14 04:52:20 PM PDT 24 |
52698783 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3052722416 |
|
|
Jul 14 04:52:01 PM PDT 24 |
Jul 14 04:52:03 PM PDT 24 |
236432066 ps |
| T88 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.22381411 |
|
|
Jul 14 04:52:35 PM PDT 24 |
Jul 14 04:52:36 PM PDT 24 |
13034698 ps |
| T119 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.653139184 |
|
|
Jul 14 04:52:27 PM PDT 24 |
Jul 14 04:52:28 PM PDT 24 |
16312235 ps |
| T944 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3393532943 |
|
|
Jul 14 04:51:47 PM PDT 24 |
Jul 14 04:51:49 PM PDT 24 |
183636817 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2213592797 |
|
|
Jul 14 04:52:49 PM PDT 24 |
Jul 14 04:52:50 PM PDT 24 |
13076040 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1852429053 |
|
|
Jul 14 04:51:40 PM PDT 24 |
Jul 14 04:51:41 PM PDT 24 |
24528247 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3111566865 |
|
|
Jul 14 04:52:16 PM PDT 24 |
Jul 14 04:52:20 PM PDT 24 |
409248498 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.526745750 |
|
|
Jul 14 04:52:30 PM PDT 24 |
Jul 14 04:52:32 PM PDT 24 |
39641741 ps |
| T945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1443251417 |
|
|
Jul 14 04:52:35 PM PDT 24 |
Jul 14 04:52:37 PM PDT 24 |
80619909 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2072756800 |
|
|
Jul 14 04:51:56 PM PDT 24 |
Jul 14 04:51:57 PM PDT 24 |
12589377 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2769895746 |
|
|
Jul 14 04:52:30 PM PDT 24 |
Jul 14 04:52:33 PM PDT 24 |
240015443 ps |
| T92 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3577656614 |
|
|
Jul 14 04:52:08 PM PDT 24 |
Jul 14 04:52:09 PM PDT 24 |
11252993 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4196766317 |
|
|
Jul 14 04:52:38 PM PDT 24 |
Jul 14 04:52:39 PM PDT 24 |
10767859 ps |
| T143 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3660085572 |
|
|
Jul 14 04:52:24 PM PDT 24 |
Jul 14 04:52:27 PM PDT 24 |
1262884868 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3398884582 |
|
|
Jul 14 04:52:51 PM PDT 24 |
Jul 14 04:52:53 PM PDT 24 |
19922866 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2801514570 |
|
|
Jul 14 04:51:54 PM PDT 24 |
Jul 14 04:51:55 PM PDT 24 |
21785108 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1578976270 |
|
|
Jul 14 04:52:30 PM PDT 24 |
Jul 14 04:52:35 PM PDT 24 |
63867064 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.28637026 |
|
|
Jul 14 04:52:09 PM PDT 24 |
Jul 14 04:52:10 PM PDT 24 |
20436322 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1696522420 |
|
|
Jul 14 04:51:47 PM PDT 24 |
Jul 14 04:51:48 PM PDT 24 |
32979830 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.849143441 |
|
|
Jul 14 04:51:55 PM PDT 24 |
Jul 14 04:51:57 PM PDT 24 |
34876126 ps |
| T97 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1117313071 |
|
|
Jul 14 04:52:28 PM PDT 24 |
Jul 14 04:52:30 PM PDT 24 |
11835057 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3799338305 |
|
|
Jul 14 04:52:16 PM PDT 24 |
Jul 14 04:52:19 PM PDT 24 |
163232464 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3416430469 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:27 PM PDT 24 |
62455176 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1926854488 |
|
|
Jul 14 04:52:43 PM PDT 24 |
Jul 14 04:52:45 PM PDT 24 |
58907826 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.740335095 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:27 PM PDT 24 |
16360342 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1378175243 |
|
|
Jul 14 04:52:49 PM PDT 24 |
Jul 14 04:52:51 PM PDT 24 |
136468898 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.383833460 |
|
|
Jul 14 04:51:48 PM PDT 24 |
Jul 14 04:51:51 PM PDT 24 |
464614215 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1631390584 |
|
|
Jul 14 04:52:17 PM PDT 24 |
Jul 14 04:52:18 PM PDT 24 |
29247030 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2077824258 |
|
|
Jul 14 04:52:39 PM PDT 24 |
Jul 14 04:52:42 PM PDT 24 |
776745665 ps |
| T150 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1819365761 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:28 PM PDT 24 |
683723986 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2221426643 |
|
|
Jul 14 04:52:10 PM PDT 24 |
Jul 14 04:52:11 PM PDT 24 |
38655150 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.741679078 |
|
|
Jul 14 04:51:59 PM PDT 24 |
Jul 14 04:52:01 PM PDT 24 |
14969625 ps |
| T113 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1445058771 |
|
|
Jul 14 04:52:16 PM PDT 24 |
Jul 14 04:52:18 PM PDT 24 |
15765425 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.872148360 |
|
|
Jul 14 04:51:52 PM PDT 24 |
Jul 14 04:51:55 PM PDT 24 |
2111985865 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1657379567 |
|
|
Jul 14 04:52:01 PM PDT 24 |
Jul 14 04:52:02 PM PDT 24 |
15984124 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.603701897 |
|
|
Jul 14 04:52:35 PM PDT 24 |
Jul 14 04:52:36 PM PDT 24 |
36629984 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1108460580 |
|
|
Jul 14 04:52:35 PM PDT 24 |
Jul 14 04:52:36 PM PDT 24 |
44039819 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4294730970 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:28 PM PDT 24 |
46514416 ps |
| T114 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2369058335 |
|
|
Jul 14 04:52:45 PM PDT 24 |
Jul 14 04:52:49 PM PDT 24 |
1720256960 ps |
| T149 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1207988315 |
|
|
Jul 14 04:52:44 PM PDT 24 |
Jul 14 04:52:48 PM PDT 24 |
818771336 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.255524878 |
|
|
Jul 14 04:52:08 PM PDT 24 |
Jul 14 04:52:09 PM PDT 24 |
23783179 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3021170895 |
|
|
Jul 14 04:52:46 PM PDT 24 |
Jul 14 04:52:48 PM PDT 24 |
15901030 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1975219346 |
|
|
Jul 14 04:51:52 PM PDT 24 |
Jul 14 04:51:54 PM PDT 24 |
83571151 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3508735325 |
|
|
Jul 14 04:52:17 PM PDT 24 |
Jul 14 04:52:19 PM PDT 24 |
51711437 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2503701384 |
|
|
Jul 14 04:52:29 PM PDT 24 |
Jul 14 04:52:33 PM PDT 24 |
277872487 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2785409465 |
|
|
Jul 14 04:52:08 PM PDT 24 |
Jul 14 04:52:10 PM PDT 24 |
38201025 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1257589633 |
|
|
Jul 14 04:52:30 PM PDT 24 |
Jul 14 04:52:32 PM PDT 24 |
22826574 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1069830211 |
|
|
Jul 14 04:52:48 PM PDT 24 |
Jul 14 04:52:53 PM PDT 24 |
425947329 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4151492399 |
|
|
Jul 14 04:51:57 PM PDT 24 |
Jul 14 04:51:59 PM PDT 24 |
160281545 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.353390265 |
|
|
Jul 14 04:52:25 PM PDT 24 |
Jul 14 04:52:27 PM PDT 24 |
34373226 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4222598984 |
|
|
Jul 14 04:52:47 PM PDT 24 |
Jul 14 04:52:51 PM PDT 24 |
497928085 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4074786149 |
|
|
Jul 14 04:52:14 PM PDT 24 |
Jul 14 04:52:15 PM PDT 24 |
54610764 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3116823368 |
|
|
Jul 14 04:52:48 PM PDT 24 |
Jul 14 04:52:52 PM PDT 24 |
120754716 ps |
| T976 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1095927217 |
|
|
Jul 14 04:52:17 PM PDT 24 |
Jul 14 04:52:19 PM PDT 24 |
19573228 ps |
| T977 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.810889982 |
|
|
Jul 14 04:52:08 PM PDT 24 |
Jul 14 04:52:13 PM PDT 24 |
195778773 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4109039176 |
|
|
Jul 14 04:52:29 PM PDT 24 |
Jul 14 04:52:34 PM PDT 24 |
114401185 ps |
| T152 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.729275100 |
|
|
Jul 14 04:52:37 PM PDT 24 |
Jul 14 04:52:40 PM PDT 24 |
253964784 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3863970184 |
|
|
Jul 14 04:52:15 PM PDT 24 |
Jul 14 04:52:19 PM PDT 24 |
1594493750 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2333556798 |
|
|
Jul 14 04:52:29 PM PDT 24 |
Jul 14 04:52:31 PM PDT 24 |
30212435 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3982095513 |
|
|
Jul 14 04:52:03 PM PDT 24 |
Jul 14 04:52:05 PM PDT 24 |
124631645 ps |
| T111 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3850735274 |
|
|
Jul 14 04:52:09 PM PDT 24 |
Jul 14 04:52:13 PM PDT 24 |
1562862966 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.562360946 |
|
|
Jul 14 04:52:44 PM PDT 24 |
Jul 14 04:52:46 PM PDT 24 |
121442557 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.208482227 |
|
|
Jul 14 04:52:02 PM PDT 24 |
Jul 14 04:52:04 PM PDT 24 |
42757493 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2626551150 |
|
|
Jul 14 04:51:54 PM PDT 24 |
Jul 14 04:51:59 PM PDT 24 |
453824687 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1065440073 |
|
|
Jul 14 04:51:47 PM PDT 24 |
Jul 14 04:51:49 PM PDT 24 |
36329533 ps |
| T146 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2975284138 |
|
|
Jul 14 04:52:07 PM PDT 24 |
Jul 14 04:52:09 PM PDT 24 |
370905836 ps |
| T144 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1510647457 |
|
|
Jul 14 04:51:44 PM PDT 24 |
Jul 14 04:51:46 PM PDT 24 |
250843120 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.835393331 |
|
|
Jul 14 04:52:10 PM PDT 24 |
Jul 14 04:52:13 PM PDT 24 |
1625365829 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2989295650 |
|
|
Jul 14 04:52:38 PM PDT 24 |
Jul 14 04:52:39 PM PDT 24 |
80603948 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.826511011 |
|
|
Jul 14 04:52:45 PM PDT 24 |
Jul 14 04:52:47 PM PDT 24 |
218339965 ps |
| T151 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3491245937 |
|
|
Jul 14 04:52:36 PM PDT 24 |
Jul 14 04:52:39 PM PDT 24 |
553317223 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2998600451 |
|
|
Jul 14 04:52:10 PM PDT 24 |
Jul 14 04:52:13 PM PDT 24 |
474599359 ps |
| T154 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4018957432 |
|
|
Jul 14 04:52:01 PM PDT 24 |
Jul 14 04:52:03 PM PDT 24 |
306994166 ps |
| T145 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4289045499 |
|
|
Jul 14 04:52:45 PM PDT 24 |
Jul 14 04:52:48 PM PDT 24 |
161720362 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3736474941 |
|
|
Jul 14 04:52:00 PM PDT 24 |
Jul 14 04:52:01 PM PDT 24 |
23006268 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2078439271 |
|
|
Jul 14 04:52:16 PM PDT 24 |
Jul 14 04:52:18 PM PDT 24 |
329969160 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2558366379 |
|
|
Jul 14 04:52:16 PM PDT 24 |
Jul 14 04:52:18 PM PDT 24 |
73501002 ps |
| T991 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.518616642 |
|
|
Jul 14 04:52:09 PM PDT 24 |
Jul 14 04:52:10 PM PDT 24 |
20644582 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4101223945 |
|
|
Jul 14 04:52:14 PM PDT 24 |
Jul 14 04:52:17 PM PDT 24 |
602006980 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1309276410 |
|
|
Jul 14 04:51:55 PM PDT 24 |
Jul 14 04:51:56 PM PDT 24 |
15379962 ps |
| T112 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3874429355 |
|
|
Jul 14 04:52:39 PM PDT 24 |
Jul 14 04:52:43 PM PDT 24 |
825344619 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4128673683 |
|
|
Jul 14 04:52:32 PM PDT 24 |
Jul 14 04:52:34 PM PDT 24 |
818962506 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.935215660 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:27 PM PDT 24 |
22223882 ps |
| T116 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4171438806 |
|
|
Jul 14 04:52:00 PM PDT 24 |
Jul 14 04:52:01 PM PDT 24 |
32480346 ps |
| T147 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1670007044 |
|
|
Jul 14 04:52:25 PM PDT 24 |
Jul 14 04:52:28 PM PDT 24 |
190402893 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1912660542 |
|
|
Jul 14 04:51:48 PM PDT 24 |
Jul 14 04:51:49 PM PDT 24 |
31446672 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2011535269 |
|
|
Jul 14 04:52:00 PM PDT 24 |
Jul 14 04:52:04 PM PDT 24 |
452062568 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1470023541 |
|
|
Jul 14 04:52:30 PM PDT 24 |
Jul 14 04:52:34 PM PDT 24 |
781611852 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.522731848 |
|
|
Jul 14 04:51:59 PM PDT 24 |
Jul 14 04:52:03 PM PDT 24 |
823838039 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1685785399 |
|
|
Jul 14 04:52:45 PM PDT 24 |
Jul 14 04:52:47 PM PDT 24 |
23064620 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.301608330 |
|
|
Jul 14 04:51:57 PM PDT 24 |
Jul 14 04:51:58 PM PDT 24 |
45690070 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.862467758 |
|
|
Jul 14 04:52:26 PM PDT 24 |
Jul 14 04:52:31 PM PDT 24 |
498304175 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2680348715 |
|
|
Jul 14 04:51:41 PM PDT 24 |
Jul 14 04:51:45 PM PDT 24 |
4875385240 ps |