SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
T1003 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2432953524 | Jul 14 04:52:45 PM PDT 24 | Jul 14 04:52:46 PM PDT 24 | 73968604 ps | ||
T1004 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1176671238 | Jul 14 04:52:45 PM PDT 24 | Jul 14 04:52:47 PM PDT 24 | 40034714 ps | ||
T1005 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2558296928 | Jul 14 04:52:10 PM PDT 24 | Jul 14 04:52:11 PM PDT 24 | 85965589 ps | ||
T1006 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.279435650 | Jul 14 04:52:45 PM PDT 24 | Jul 14 04:52:47 PM PDT 24 | 39704120 ps | ||
T1007 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3225330466 | Jul 14 04:51:41 PM PDT 24 | Jul 14 04:51:42 PM PDT 24 | 41977750 ps | ||
T1008 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2385804094 | Jul 14 04:51:47 PM PDT 24 | Jul 14 04:51:51 PM PDT 24 | 84883264 ps | ||
T1009 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3451084599 | Jul 14 04:52:29 PM PDT 24 | Jul 14 04:52:33 PM PDT 24 | 427637032 ps | ||
T1010 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1822714472 | Jul 14 04:52:21 PM PDT 24 | Jul 14 04:52:22 PM PDT 24 | 37814444 ps | ||
T1011 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3387309789 | Jul 14 04:52:24 PM PDT 24 | Jul 14 04:52:29 PM PDT 24 | 117548536 ps | ||
T1012 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2143273559 | Jul 14 04:52:25 PM PDT 24 | Jul 14 04:52:27 PM PDT 24 | 140704963 ps | ||
T148 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.985851345 | Jul 14 04:52:45 PM PDT 24 | Jul 14 04:52:49 PM PDT 24 | 300039158 ps | ||
T1013 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1419539482 | Jul 14 04:52:31 PM PDT 24 | Jul 14 04:52:34 PM PDT 24 | 139092166 ps | ||
T1014 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3907476142 | Jul 14 04:51:44 PM PDT 24 | Jul 14 04:51:45 PM PDT 24 | 17607304 ps | ||
T1015 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3486888548 | Jul 14 04:52:38 PM PDT 24 | Jul 14 04:52:41 PM PDT 24 | 24300627 ps | ||
T1016 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4010608876 | Jul 14 04:52:21 PM PDT 24 | Jul 14 04:52:24 PM PDT 24 | 469139081 ps | ||
T1017 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1306721897 | Jul 14 04:52:49 PM PDT 24 | Jul 14 04:52:51 PM PDT 24 | 12488080 ps | ||
T1018 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.412030250 | Jul 14 04:52:51 PM PDT 24 | Jul 14 04:52:54 PM PDT 24 | 161684404 ps | ||
T1019 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3505854083 | Jul 14 04:51:39 PM PDT 24 | Jul 14 04:51:41 PM PDT 24 | 68674670 ps | ||
T153 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2061291885 | Jul 14 04:52:30 PM PDT 24 | Jul 14 04:52:34 PM PDT 24 | 1653786178 ps | ||
T1020 | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3529291451 | Jul 14 04:52:25 PM PDT 24 | Jul 14 04:52:28 PM PDT 24 | 1013037112 ps | ||
T1021 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.696272680 | Jul 14 04:52:07 PM PDT 24 | Jul 14 04:52:08 PM PDT 24 | 84546347 ps | ||
T1022 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3212354501 | Jul 14 04:51:48 PM PDT 24 | Jul 14 04:51:51 PM PDT 24 | 329438217 ps | ||
T1023 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3068737988 | Jul 14 04:52:24 PM PDT 24 | Jul 14 04:52:28 PM PDT 24 | 405861507 ps |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.1956198260 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 12339965794 ps |
CPU time | 1162.91 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 05:13:16 PM PDT 24 |
Peak memory | 368460 kb |
Host | smart-08f4353a-cb90-466f-9c05-c86460687534 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956198260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1956198260 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.435437726 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 1849171063 ps |
CPU time | 87.24 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 04:59:17 PM PDT 24 |
Peak memory | 310804 kb |
Host | smart-3ec76693-a23a-4b60-b0ea-78f820155a62 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=435437726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.435437726 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3412844251 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 119935540 ps |
CPU time | 3.71 seconds |
Started | Jul 14 05:01:03 PM PDT 24 |
Finished | Jul 14 05:01:07 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-0aa20a6e-3d79-45be-8e02-d3e3dcdfc7c6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412844251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.3412844251 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.418287693 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 36030277511 ps |
CPU time | 1517.29 seconds |
Started | Jul 14 05:02:14 PM PDT 24 |
Finished | Jul 14 05:27:32 PM PDT 24 |
Peak memory | 383572 kb |
Host | smart-b6b155ce-1aaf-46fb-a03e-48a34d46335e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418287693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_stress_all.418287693 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3046943743 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 269705434 ps |
CPU time | 2.62 seconds |
Started | Jul 14 04:52:36 PM PDT 24 |
Finished | Jul 14 04:52:39 PM PDT 24 |
Peak memory | 210180 kb |
Host | smart-870ae3eb-9b68-4f0a-926a-219fe0b0cad9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046943743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.3046943743 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.1989491680 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 908491027 ps |
CPU time | 3.19 seconds |
Started | Jul 14 04:54:11 PM PDT 24 |
Finished | Jul 14 04:54:14 PM PDT 24 |
Peak memory | 232636 kb |
Host | smart-d4597603-4ef0-411a-aae6-fe18a1a57ad8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989491680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1989491680 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3492465723 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 4289689725 ps |
CPU time | 1279 seconds |
Started | Jul 14 04:54:02 PM PDT 24 |
Finished | Jul 14 05:15:22 PM PDT 24 |
Peak memory | 354164 kb |
Host | smart-b1101389-1fbc-417e-a827-83428c3ff663 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492465723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3492465723 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2951145927 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 16443583302 ps |
CPU time | 331.59 seconds |
Started | Jul 14 04:58:45 PM PDT 24 |
Finished | Jul 14 05:04:18 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-6dc6b2d4-1d79-4021-bfe3-ecc46df5e753 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951145927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2951145927 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.4086930236 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 21762254382 ps |
CPU time | 2731.04 seconds |
Started | Jul 14 05:00:32 PM PDT 24 |
Finished | Jul 14 05:46:04 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-99385165-a459-47b5-bcea-350465586ae5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086930236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.4086930236 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3016054786 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 352907335 ps |
CPU time | 2.06 seconds |
Started | Jul 14 04:51:48 PM PDT 24 |
Finished | Jul 14 04:51:51 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-ae5c41fa-463c-4670-8584-0c3841e8f28c |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016054786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3016054786 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1420413149 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1469639009 ps |
CPU time | 115.28 seconds |
Started | Jul 14 04:58:26 PM PDT 24 |
Finished | Jul 14 05:00:22 PM PDT 24 |
Peak memory | 298996 kb |
Host | smart-e3ab2028-f366-47f8-b3ec-7c000a71a1af |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1420413149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1420413149 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2704001586 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 6223897176 ps |
CPU time | 531.54 seconds |
Started | Jul 14 04:55:51 PM PDT 24 |
Finished | Jul 14 05:04:43 PM PDT 24 |
Peak memory | 375248 kb |
Host | smart-ab8eed2b-3161-4ee8-a40a-5fe443ec88fa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2704001586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2704001586 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.561184409 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 81067679 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:54:37 PM PDT 24 |
Finished | Jul 14 04:54:39 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-74f8b7fc-a580-46a5-801d-1d7c841497ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561184409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.561184409 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.1515126333 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 18471941373 ps |
CPU time | 8279.65 seconds |
Started | Jul 14 05:00:16 PM PDT 24 |
Finished | Jul 14 07:18:17 PM PDT 24 |
Peak memory | 382484 kb |
Host | smart-d95ac326-926e-40e9-8850-51622d129e1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515126333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.1515126333 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.380107216 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 50671349 ps |
CPU time | 0.64 seconds |
Started | Jul 14 05:01:43 PM PDT 24 |
Finished | Jul 14 05:01:44 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-9e1f1a44-15dc-42e9-95c3-200e8cb22496 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380107216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.380107216 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4018957432 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 306994166 ps |
CPU time | 2.51 seconds |
Started | Jul 14 04:52:01 PM PDT 24 |
Finished | Jul 14 04:52:03 PM PDT 24 |
Peak memory | 210256 kb |
Host | smart-88457dbd-8e14-4ab0-bd3e-6a8e6286dae5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018957432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.4018957432 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3660085572 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1262884868 ps |
CPU time | 2.21 seconds |
Started | Jul 14 04:52:24 PM PDT 24 |
Finished | Jul 14 04:52:27 PM PDT 24 |
Peak memory | 210284 kb |
Host | smart-842a0e9e-f939-460c-8948-edb5924f924e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660085572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3660085572 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1670007044 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 190402893 ps |
CPU time | 2.53 seconds |
Started | Jul 14 04:52:25 PM PDT 24 |
Finished | Jul 14 04:52:28 PM PDT 24 |
Peak memory | 210272 kb |
Host | smart-cb43ca12-57fa-43b7-84ba-4a37efc6cd2c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670007044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1670007044 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.4175508747 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 18014453996 ps |
CPU time | 1489.03 seconds |
Started | Jul 14 04:57:30 PM PDT 24 |
Finished | Jul 14 05:22:19 PM PDT 24 |
Peak memory | 374500 kb |
Host | smart-127bcd56-5d92-41fe-b75b-e21794db2611 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175508747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.4175508747 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3907476142 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 17607304 ps |
CPU time | 0.71 seconds |
Started | Jul 14 04:51:44 PM PDT 24 |
Finished | Jul 14 04:51:45 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-9e97d6b8-ec2a-453c-850a-9c407aeb70a8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907476142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3907476142 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3505854083 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 68674670 ps |
CPU time | 1.36 seconds |
Started | Jul 14 04:51:39 PM PDT 24 |
Finished | Jul 14 04:51:41 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-c042c51f-182f-4afc-89a8-34ebc1305bd5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505854083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.3505854083 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.554633499 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 41401202 ps |
CPU time | 0.63 seconds |
Started | Jul 14 04:51:43 PM PDT 24 |
Finished | Jul 14 04:51:44 PM PDT 24 |
Peak memory | 201712 kb |
Host | smart-ee195cfa-1c89-4897-846f-0096fef5abab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554633499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.554633499 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3393532943 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 183636817 ps |
CPU time | 1.25 seconds |
Started | Jul 14 04:51:47 PM PDT 24 |
Finished | Jul 14 04:51:49 PM PDT 24 |
Peak memory | 210116 kb |
Host | smart-b64673a2-e210-42d7-8d04-5e005c6cc126 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393532943 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3393532943 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3225330466 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 41977750 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:51:41 PM PDT 24 |
Finished | Jul 14 04:51:42 PM PDT 24 |
Peak memory | 201812 kb |
Host | smart-8a2d8ca3-9792-4620-a808-5eafa39ca35b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225330466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3225330466 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2680348715 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 4875385240 ps |
CPU time | 3.76 seconds |
Started | Jul 14 04:51:41 PM PDT 24 |
Finished | Jul 14 04:51:45 PM PDT 24 |
Peak memory | 202192 kb |
Host | smart-86ce2fd2-415c-4e2a-b25a-3d3b6bf1c14e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680348715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2680348715 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1852429053 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 24528247 ps |
CPU time | 0.72 seconds |
Started | Jul 14 04:51:40 PM PDT 24 |
Finished | Jul 14 04:51:41 PM PDT 24 |
Peak memory | 201852 kb |
Host | smart-f84beed7-8602-4fcb-981d-7df44988b7e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852429053 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1852429053 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3141503643 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 507125006 ps |
CPU time | 4.71 seconds |
Started | Jul 14 04:51:42 PM PDT 24 |
Finished | Jul 14 04:51:47 PM PDT 24 |
Peak memory | 211244 kb |
Host | smart-c56a51c4-1654-4e05-bb15-50d139bbd227 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141503643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3141503643 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1510647457 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 250843120 ps |
CPU time | 1.39 seconds |
Started | Jul 14 04:51:44 PM PDT 24 |
Finished | Jul 14 04:51:46 PM PDT 24 |
Peak memory | 210192 kb |
Host | smart-a836b372-7d34-467b-9b6d-5e3ea54b438b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510647457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.1510647457 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1065440073 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 36329533 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:51:47 PM PDT 24 |
Finished | Jul 14 04:51:49 PM PDT 24 |
Peak memory | 201228 kb |
Host | smart-3a024a4c-9444-4141-a740-ecaef90bb7b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065440073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.1065440073 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2424529056 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 41589905 ps |
CPU time | 1.78 seconds |
Started | Jul 14 04:51:49 PM PDT 24 |
Finished | Jul 14 04:51:51 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-b05f6fbb-ff77-428e-aa18-ba3f7a40bd6f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424529056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.2424529056 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1912660542 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 31446672 ps |
CPU time | 0.76 seconds |
Started | Jul 14 04:51:48 PM PDT 24 |
Finished | Jul 14 04:51:49 PM PDT 24 |
Peak memory | 201444 kb |
Host | smart-d5d65e70-c666-4c0e-8664-58a1f28f7e6a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912660542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.1912660542 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2072756800 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 12589377 ps |
CPU time | 0.63 seconds |
Started | Jul 14 04:51:56 PM PDT 24 |
Finished | Jul 14 04:51:57 PM PDT 24 |
Peak memory | 201748 kb |
Host | smart-efe6e373-6d45-4018-aa8f-2a015cfbd55e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072756800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2072756800 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1975219346 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 83571151 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:51:52 PM PDT 24 |
Finished | Jul 14 04:51:54 PM PDT 24 |
Peak memory | 201812 kb |
Host | smart-e2948dbf-07cc-4b10-9f08-86898f634663 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975219346 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1975219346 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2385804094 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 84883264 ps |
CPU time | 2.51 seconds |
Started | Jul 14 04:51:47 PM PDT 24 |
Finished | Jul 14 04:51:51 PM PDT 24 |
Peak memory | 210256 kb |
Host | smart-6f3d502b-54f5-4dfc-a06c-7246dfeb4461 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385804094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2385804094 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1660970779 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 433103120 ps |
CPU time | 1.61 seconds |
Started | Jul 14 04:51:48 PM PDT 24 |
Finished | Jul 14 04:51:51 PM PDT 24 |
Peak memory | 210360 kb |
Host | smart-8c4c0ce8-a3f1-46f1-b486-45066cfa0dd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660970779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1660970779 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2143273559 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 140704963 ps |
CPU time | 1.53 seconds |
Started | Jul 14 04:52:25 PM PDT 24 |
Finished | Jul 14 04:52:27 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-bb1f3d65-b49e-456d-b6e7-8c7bc961c48b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143273559 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2143273559 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.935215660 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 22223882 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:27 PM PDT 24 |
Peak memory | 201732 kb |
Host | smart-c1202cc6-aa00-4161-b078-c37ccab1ad56 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935215660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_csr_rw.935215660 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3529291451 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 1013037112 ps |
CPU time | 3.29 seconds |
Started | Jul 14 04:52:25 PM PDT 24 |
Finished | Jul 14 04:52:28 PM PDT 24 |
Peak memory | 202200 kb |
Host | smart-f1bb2128-8e7a-4aa3-b7cb-f64b4138be14 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529291451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3529291451 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.653139184 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 16312235 ps |
CPU time | 0.74 seconds |
Started | Jul 14 04:52:27 PM PDT 24 |
Finished | Jul 14 04:52:28 PM PDT 24 |
Peak memory | 201816 kb |
Host | smart-79c66fa6-c802-4b28-b1fa-83ce85536a6f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653139184 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.653139184 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3387309789 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 117548536 ps |
CPU time | 4.39 seconds |
Started | Jul 14 04:52:24 PM PDT 24 |
Finished | Jul 14 04:52:29 PM PDT 24 |
Peak memory | 210276 kb |
Host | smart-6e82c132-3027-4ea9-a282-d466e2e79309 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387309789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3387309789 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2769895746 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 240015443 ps |
CPU time | 1.4 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:33 PM PDT 24 |
Peak memory | 210136 kb |
Host | smart-0e7b3f05-5176-4155-8d7a-6fb706346729 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769895746 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2769895746 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1117313071 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 11835057 ps |
CPU time | 0.6 seconds |
Started | Jul 14 04:52:28 PM PDT 24 |
Finished | Jul 14 04:52:30 PM PDT 24 |
Peak memory | 201676 kb |
Host | smart-c57502b9-7a84-4fa3-b5b9-ad1c54e7fad1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117313071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.1117313071 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3451084599 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 427637032 ps |
CPU time | 3.1 seconds |
Started | Jul 14 04:52:29 PM PDT 24 |
Finished | Jul 14 04:52:33 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-fc1ac8ef-0e32-4ccc-a85a-2a1e48b4a53f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451084599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.3451084599 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1108460580 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 44039819 ps |
CPU time | 0.81 seconds |
Started | Jul 14 04:52:35 PM PDT 24 |
Finished | Jul 14 04:52:36 PM PDT 24 |
Peak memory | 201836 kb |
Host | smart-a58d6202-c995-47dd-8440-928bc899af53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108460580 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1108460580 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3142117356 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 134814778 ps |
CPU time | 4.2 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:31 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-13c1963c-27e5-46a4-a124-5db2bb5f11ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142117356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.3142117356 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1443251417 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 80619909 ps |
CPU time | 1.23 seconds |
Started | Jul 14 04:52:35 PM PDT 24 |
Finished | Jul 14 04:52:37 PM PDT 24 |
Peak memory | 210108 kb |
Host | smart-3683a3c6-e172-46c6-84d1-3375a6e87d88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443251417 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1443251417 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.526745750 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 39641741 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:32 PM PDT 24 |
Peak memory | 201804 kb |
Host | smart-9afffbef-5b06-4c9f-a2e7-95ec3afb2067 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526745750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.526745750 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.924986181 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 233624091 ps |
CPU time | 2.02 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:33 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-1084baaf-f3d7-4abb-a940-ff4a921c5a44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924986181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.924986181 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.603701897 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 36629984 ps |
CPU time | 0.81 seconds |
Started | Jul 14 04:52:35 PM PDT 24 |
Finished | Jul 14 04:52:36 PM PDT 24 |
Peak memory | 201520 kb |
Host | smart-43016162-954e-4c96-aa62-367df6724eb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603701897 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.603701897 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4109039176 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 114401185 ps |
CPU time | 4.2 seconds |
Started | Jul 14 04:52:29 PM PDT 24 |
Finished | Jul 14 04:52:34 PM PDT 24 |
Peak memory | 210384 kb |
Host | smart-f2995c13-ea78-48aa-b104-0bdd99401c7f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109039176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.4109039176 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1419539482 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 139092166 ps |
CPU time | 2.25 seconds |
Started | Jul 14 04:52:31 PM PDT 24 |
Finished | Jul 14 04:52:34 PM PDT 24 |
Peak memory | 210364 kb |
Host | smart-aec9e9af-e3fb-4ad3-83b0-bb818cd42ddc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419539482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.1419539482 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.22381411 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 13034698 ps |
CPU time | 0.72 seconds |
Started | Jul 14 04:52:35 PM PDT 24 |
Finished | Jul 14 04:52:36 PM PDT 24 |
Peak memory | 201468 kb |
Host | smart-34f78e1d-0ea6-431e-9c06-de6e57c3b3b5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 13.sram_ctrl_csr_rw.22381411 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4128673683 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 818962506 ps |
CPU time | 2.1 seconds |
Started | Jul 14 04:52:32 PM PDT 24 |
Finished | Jul 14 04:52:34 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-ae9fee53-6c79-4e8a-881c-3d01b48cc1ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128673683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.4128673683 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1257589633 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 22826574 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:32 PM PDT 24 |
Peak memory | 201832 kb |
Host | smart-a0ace802-c51e-4cf2-9e9b-19fa04b3cc1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257589633 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1257589633 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1578976270 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 63867064 ps |
CPU time | 4.07 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:35 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-633ec906-ac39-416b-af77-de208882b89a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578976270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.1578976270 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2061291885 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 1653786178 ps |
CPU time | 2.37 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:34 PM PDT 24 |
Peak memory | 210272 kb |
Host | smart-d5476eb2-38b0-49e1-8e52-3566a9a597cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061291885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.2061291885 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4197451057 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 73960937 ps |
CPU time | 2.26 seconds |
Started | Jul 14 04:52:38 PM PDT 24 |
Finished | Jul 14 04:52:41 PM PDT 24 |
Peak memory | 210352 kb |
Host | smart-450c44af-395e-4315-9e7e-bf4029e2633a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197451057 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.4197451057 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4196766317 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 10767859 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:52:38 PM PDT 24 |
Finished | Jul 14 04:52:39 PM PDT 24 |
Peak memory | 201764 kb |
Host | smart-a6a22abb-c41f-4c09-86a0-ffee210512ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196766317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.4196766317 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1470023541 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 781611852 ps |
CPU time | 1.91 seconds |
Started | Jul 14 04:52:30 PM PDT 24 |
Finished | Jul 14 04:52:34 PM PDT 24 |
Peak memory | 201912 kb |
Host | smart-483fc834-08da-490d-8c9c-a127d5f85995 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470023541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1470023541 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2989295650 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 80603948 ps |
CPU time | 0.83 seconds |
Started | Jul 14 04:52:38 PM PDT 24 |
Finished | Jul 14 04:52:39 PM PDT 24 |
Peak memory | 201836 kb |
Host | smart-11d0660a-9d94-4246-bf62-89f7beec14a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989295650 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2989295650 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2503701384 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 277872487 ps |
CPU time | 2.66 seconds |
Started | Jul 14 04:52:29 PM PDT 24 |
Finished | Jul 14 04:52:33 PM PDT 24 |
Peak memory | 202108 kb |
Host | smart-c76208f2-b6eb-4592-8dd8-5260cc419dc8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503701384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.2503701384 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.729275100 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 253964784 ps |
CPU time | 2.25 seconds |
Started | Jul 14 04:52:37 PM PDT 24 |
Finished | Jul 14 04:52:40 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-883ac213-1ac8-467a-9694-d00371db1eff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729275100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.sram_ctrl_tl_intg_err.729275100 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3074492268 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 20013685 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:52:35 PM PDT 24 |
Finished | Jul 14 04:52:36 PM PDT 24 |
Peak memory | 201768 kb |
Host | smart-2276535e-c7a8-4f79-8ee8-3945eae2c4df |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074492268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3074492268 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3874429355 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 825344619 ps |
CPU time | 3.31 seconds |
Started | Jul 14 04:52:39 PM PDT 24 |
Finished | Jul 14 04:52:43 PM PDT 24 |
Peak memory | 202168 kb |
Host | smart-b798396e-f023-4deb-a85a-5630527ae867 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874429355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3874429355 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1509754581 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 40304827 ps |
CPU time | 0.75 seconds |
Started | Jul 14 04:52:38 PM PDT 24 |
Finished | Jul 14 04:52:39 PM PDT 24 |
Peak memory | 201852 kb |
Host | smart-8ec680a9-35bd-44a8-a66e-a5415ed45fc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509754581 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1509754581 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.636146726 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 200156340 ps |
CPU time | 2.47 seconds |
Started | Jul 14 04:52:37 PM PDT 24 |
Finished | Jul 14 04:52:40 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-3f2e1e5b-200e-4f29-83d1-ca7a644f278c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636146726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.636146726 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3491245937 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 553317223 ps |
CPU time | 2.24 seconds |
Started | Jul 14 04:52:36 PM PDT 24 |
Finished | Jul 14 04:52:39 PM PDT 24 |
Peak memory | 210200 kb |
Host | smart-e1e1038f-8b9a-4cbd-bbb1-c40d98cce081 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491245937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.3491245937 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.562360946 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 121442557 ps |
CPU time | 1.11 seconds |
Started | Jul 14 04:52:44 PM PDT 24 |
Finished | Jul 14 04:52:46 PM PDT 24 |
Peak memory | 210108 kb |
Host | smart-6359e800-cc8d-42cb-81d6-4646d588dbfb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562360946 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.562360946 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1685785399 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 23064620 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:47 PM PDT 24 |
Peak memory | 201744 kb |
Host | smart-7c7c9080-e429-4164-ae81-95f2ab1ebed3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685785399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1685785399 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2077824258 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 776745665 ps |
CPU time | 1.98 seconds |
Started | Jul 14 04:52:39 PM PDT 24 |
Finished | Jul 14 04:52:42 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-fe202ac8-60a9-4259-9db5-b0180ec47e31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077824258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2077824258 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2432953524 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 73968604 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:46 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-1f5c3f04-d9b4-4afe-aa1f-607aef0dd954 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432953524 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2432953524 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3486888548 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 24300627 ps |
CPU time | 2.14 seconds |
Started | Jul 14 04:52:38 PM PDT 24 |
Finished | Jul 14 04:52:41 PM PDT 24 |
Peak memory | 210252 kb |
Host | smart-e7644bfc-29ac-4cd4-92f6-3c38cf34ad3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486888548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.3486888548 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1176671238 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 40034714 ps |
CPU time | 1.33 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:47 PM PDT 24 |
Peak memory | 210416 kb |
Host | smart-44788521-2f1b-4646-9868-981a06cc338d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176671238 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1176671238 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3021170895 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 15901030 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:52:46 PM PDT 24 |
Finished | Jul 14 04:52:48 PM PDT 24 |
Peak memory | 201732 kb |
Host | smart-363df19f-13f6-413d-a9eb-f25db7b937cc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021170895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.3021170895 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.826511011 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 218339965 ps |
CPU time | 1.94 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:47 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-1f40b037-269f-4a40-abc2-447d29e18362 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826511011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.826511011 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2213592797 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 13076040 ps |
CPU time | 0.68 seconds |
Started | Jul 14 04:52:49 PM PDT 24 |
Finished | Jul 14 04:52:50 PM PDT 24 |
Peak memory | 201840 kb |
Host | smart-867b1435-abf2-4111-a439-bca77b338204 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213592797 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2213592797 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3116823368 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 120754716 ps |
CPU time | 2.91 seconds |
Started | Jul 14 04:52:48 PM PDT 24 |
Finished | Jul 14 04:52:52 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-6bed5eb7-cdcc-4ecd-9b36-07ec647c5dd3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116823368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.3116823368 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1207988315 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 818771336 ps |
CPU time | 2.38 seconds |
Started | Jul 14 04:52:44 PM PDT 24 |
Finished | Jul 14 04:52:48 PM PDT 24 |
Peak memory | 210288 kb |
Host | smart-e463b882-5e66-4378-a4a5-1901cb0822b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207988315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.1207988315 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1378175243 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 136468898 ps |
CPU time | 1.4 seconds |
Started | Jul 14 04:52:49 PM PDT 24 |
Finished | Jul 14 04:52:51 PM PDT 24 |
Peak memory | 210132 kb |
Host | smart-928d09ca-ab05-4c4f-bf8a-41828c20dd93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378175243 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1378175243 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.279435650 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 39704120 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:47 PM PDT 24 |
Peak memory | 201748 kb |
Host | smart-3f2725b4-74ee-44bb-a2ba-fb698e7955a3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279435650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_csr_rw.279435650 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4222598984 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 497928085 ps |
CPU time | 3.59 seconds |
Started | Jul 14 04:52:47 PM PDT 24 |
Finished | Jul 14 04:52:51 PM PDT 24 |
Peak memory | 202264 kb |
Host | smart-e2686212-0f9a-4380-b30b-4e0ef20f37b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222598984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.4222598984 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1926854488 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 58907826 ps |
CPU time | 0.68 seconds |
Started | Jul 14 04:52:43 PM PDT 24 |
Finished | Jul 14 04:52:45 PM PDT 24 |
Peak memory | 201812 kb |
Host | smart-0e9d4b06-6ecd-4bfb-82c4-9e370ed02704 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926854488 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1926854488 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2579772171 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 410164705 ps |
CPU time | 2.4 seconds |
Started | Jul 14 04:52:48 PM PDT 24 |
Finished | Jul 14 04:52:51 PM PDT 24 |
Peak memory | 210404 kb |
Host | smart-59a1feda-24ef-4662-a753-aa216561c3a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579772171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.2579772171 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4289045499 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 161720362 ps |
CPU time | 1.65 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:48 PM PDT 24 |
Peak memory | 210240 kb |
Host | smart-652fffb5-0756-4003-b830-08125fc2e8fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289045499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.4289045499 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.412030250 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 161684404 ps |
CPU time | 1.71 seconds |
Started | Jul 14 04:52:51 PM PDT 24 |
Finished | Jul 14 04:52:54 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-ef45fe4d-2d23-475f-81f7-505296260b6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412030250 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.412030250 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1306721897 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 12488080 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:52:49 PM PDT 24 |
Finished | Jul 14 04:52:51 PM PDT 24 |
Peak memory | 201256 kb |
Host | smart-e665fde9-1aa4-4fac-94a9-900af132b132 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306721897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.1306721897 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2369058335 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1720256960 ps |
CPU time | 3.29 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:49 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-d27f40d6-186d-44a0-8df6-3209548430ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369058335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2369058335 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3398884582 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 19922866 ps |
CPU time | 0.7 seconds |
Started | Jul 14 04:52:51 PM PDT 24 |
Finished | Jul 14 04:52:53 PM PDT 24 |
Peak memory | 201884 kb |
Host | smart-10034c9d-faaf-43ab-8367-437738b18712 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398884582 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3398884582 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1069830211 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 425947329 ps |
CPU time | 4.66 seconds |
Started | Jul 14 04:52:48 PM PDT 24 |
Finished | Jul 14 04:52:53 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-2e27b359-3323-4c4d-991f-010514697e34 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069830211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1069830211 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.985851345 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 300039158 ps |
CPU time | 2.63 seconds |
Started | Jul 14 04:52:45 PM PDT 24 |
Finished | Jul 14 04:52:49 PM PDT 24 |
Peak memory | 210284 kb |
Host | smart-0d54993c-0e7d-4ddc-b3b3-81991bec4643 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985851345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.sram_ctrl_tl_intg_err.985851345 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2801514570 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 21785108 ps |
CPU time | 0.71 seconds |
Started | Jul 14 04:51:54 PM PDT 24 |
Finished | Jul 14 04:51:55 PM PDT 24 |
Peak memory | 201740 kb |
Host | smart-5a5bf1f1-3ab7-4461-8e0b-8a1916366e4b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801514570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2801514570 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4151492399 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 160281545 ps |
CPU time | 1.88 seconds |
Started | Jul 14 04:51:57 PM PDT 24 |
Finished | Jul 14 04:51:59 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-267b774d-ba17-46f9-b037-ad177180b693 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151492399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.4151492399 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1696522420 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 32979830 ps |
CPU time | 0.64 seconds |
Started | Jul 14 04:51:47 PM PDT 24 |
Finished | Jul 14 04:51:48 PM PDT 24 |
Peak memory | 201688 kb |
Host | smart-ec4dadf3-86e2-4216-96da-1a4373a6cafc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696522420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.1696522420 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.849143441 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 34876126 ps |
CPU time | 1.52 seconds |
Started | Jul 14 04:51:55 PM PDT 24 |
Finished | Jul 14 04:51:57 PM PDT 24 |
Peak memory | 210260 kb |
Host | smart-e37a77a2-e689-4cb3-b6bc-20f7e52e68c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849143441 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.849143441 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1309276410 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 15379962 ps |
CPU time | 0.64 seconds |
Started | Jul 14 04:51:55 PM PDT 24 |
Finished | Jul 14 04:51:56 PM PDT 24 |
Peak memory | 201464 kb |
Host | smart-89da07e3-181a-42b6-a11c-343e5d9d371f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309276410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.1309276410 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.872148360 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 2111985865 ps |
CPU time | 2.3 seconds |
Started | Jul 14 04:51:52 PM PDT 24 |
Finished | Jul 14 04:51:55 PM PDT 24 |
Peak memory | 201168 kb |
Host | smart-a3c21825-0292-4c2c-bddc-8e5d8736afc8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872148360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.872148360 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.301608330 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 45690070 ps |
CPU time | 0.86 seconds |
Started | Jul 14 04:51:57 PM PDT 24 |
Finished | Jul 14 04:51:58 PM PDT 24 |
Peak memory | 201840 kb |
Host | smart-8b65d7c9-cb1c-4d17-b296-6b328fc006bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301608330 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.301608330 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.383833460 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 464614215 ps |
CPU time | 2.54 seconds |
Started | Jul 14 04:51:48 PM PDT 24 |
Finished | Jul 14 04:51:51 PM PDT 24 |
Peak memory | 210288 kb |
Host | smart-815782a3-6bd7-459c-addd-d97bfc9b1572 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383833460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.383833460 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3212354501 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 329438217 ps |
CPU time | 2.69 seconds |
Started | Jul 14 04:51:48 PM PDT 24 |
Finished | Jul 14 04:51:51 PM PDT 24 |
Peak memory | 210260 kb |
Host | smart-ded774d5-f210-4695-88e4-cc3661f20d0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212354501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3212354501 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.741679078 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 14969625 ps |
CPU time | 0.71 seconds |
Started | Jul 14 04:51:59 PM PDT 24 |
Finished | Jul 14 04:52:01 PM PDT 24 |
Peak memory | 201768 kb |
Host | smart-24603ec0-ab33-4390-a8bd-bd2fbbffc921 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741679078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.741679078 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3052722416 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 236432066 ps |
CPU time | 1.5 seconds |
Started | Jul 14 04:52:01 PM PDT 24 |
Finished | Jul 14 04:52:03 PM PDT 24 |
Peak memory | 201896 kb |
Host | smart-7ee0df66-4786-4196-8165-2a339c9d6e33 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052722416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3052722416 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.255524878 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 23783179 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:52:08 PM PDT 24 |
Finished | Jul 14 04:52:09 PM PDT 24 |
Peak memory | 201300 kb |
Host | smart-fb9e8828-9b56-4cdc-a9ab-fc0c23862895 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255524878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.255524878 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3982095513 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 124631645 ps |
CPU time | 1.93 seconds |
Started | Jul 14 04:52:03 PM PDT 24 |
Finished | Jul 14 04:52:05 PM PDT 24 |
Peak memory | 210292 kb |
Host | smart-33d1c9ef-2698-4cea-b004-81c5190eaf40 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982095513 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3982095513 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4171438806 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 32480346 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:52:00 PM PDT 24 |
Finished | Jul 14 04:52:01 PM PDT 24 |
Peak memory | 201724 kb |
Host | smart-12fc4636-6126-48bf-949f-605681e0a255 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171438806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.4171438806 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.522731848 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 823838039 ps |
CPU time | 3.34 seconds |
Started | Jul 14 04:51:59 PM PDT 24 |
Finished | Jul 14 04:52:03 PM PDT 24 |
Peak memory | 202116 kb |
Host | smart-11eeb8fc-f077-4241-958e-a03997a3067c |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522731848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.522731848 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3736474941 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 23006268 ps |
CPU time | 0.8 seconds |
Started | Jul 14 04:52:00 PM PDT 24 |
Finished | Jul 14 04:52:01 PM PDT 24 |
Peak memory | 201836 kb |
Host | smart-2cfba4ab-cd7a-43e3-a5f9-c277f324a69b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736474941 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3736474941 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2626551150 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 453824687 ps |
CPU time | 4.55 seconds |
Started | Jul 14 04:51:54 PM PDT 24 |
Finished | Jul 14 04:51:59 PM PDT 24 |
Peak memory | 210256 kb |
Host | smart-11dd845f-b704-45de-9dc8-249343d22db8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626551150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2626551150 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.28637026 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 20436322 ps |
CPU time | 0.72 seconds |
Started | Jul 14 04:52:09 PM PDT 24 |
Finished | Jul 14 04:52:10 PM PDT 24 |
Peak memory | 201780 kb |
Host | smart-05f9eedb-5889-44af-8cd3-f4b2f77b8bf2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28637026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.28637026 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2998600451 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 474599359 ps |
CPU time | 2.23 seconds |
Started | Jul 14 04:52:10 PM PDT 24 |
Finished | Jul 14 04:52:13 PM PDT 24 |
Peak memory | 201980 kb |
Host | smart-c2ac00c7-e47c-40e7-a92b-5eda5bcd2b43 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998600451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.2998600451 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.696272680 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 84546347 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:52:07 PM PDT 24 |
Finished | Jul 14 04:52:08 PM PDT 24 |
Peak memory | 201568 kb |
Host | smart-52d9d192-5835-4522-bf06-4a1f13b5ec3e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696272680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.696272680 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1657379567 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 15984124 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:52:01 PM PDT 24 |
Finished | Jul 14 04:52:02 PM PDT 24 |
Peak memory | 201836 kb |
Host | smart-601ff47f-7270-4373-875a-cc05946387ff |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657379567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.1657379567 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2011535269 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 452062568 ps |
CPU time | 3.01 seconds |
Started | Jul 14 04:52:00 PM PDT 24 |
Finished | Jul 14 04:52:04 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-61234f5f-c693-4466-8068-905e3d5cb7c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011535269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2011535269 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4074786149 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 54610764 ps |
CPU time | 0.75 seconds |
Started | Jul 14 04:52:14 PM PDT 24 |
Finished | Jul 14 04:52:15 PM PDT 24 |
Peak memory | 201840 kb |
Host | smart-d13548c6-8ad4-467e-93c7-f4b5fed7c8f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074786149 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.4074786149 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.208482227 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 42757493 ps |
CPU time | 1.67 seconds |
Started | Jul 14 04:52:02 PM PDT 24 |
Finished | Jul 14 04:52:04 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-f1922663-2183-41fd-846d-0251e893f353 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208482227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.208482227 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3561470373 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 97986095 ps |
CPU time | 1.54 seconds |
Started | Jul 14 04:52:02 PM PDT 24 |
Finished | Jul 14 04:52:03 PM PDT 24 |
Peak memory | 210228 kb |
Host | smart-c5d2a5b6-80e5-4a54-94f6-ead5f107f021 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561470373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3561470373 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2221426643 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 38655150 ps |
CPU time | 1.19 seconds |
Started | Jul 14 04:52:10 PM PDT 24 |
Finished | Jul 14 04:52:11 PM PDT 24 |
Peak memory | 210184 kb |
Host | smart-d0c69e7e-2450-4a10-81c2-d833ae4b2356 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221426643 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2221426643 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3577656614 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 11252993 ps |
CPU time | 0.64 seconds |
Started | Jul 14 04:52:08 PM PDT 24 |
Finished | Jul 14 04:52:09 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-5abf21cc-742c-4074-8dcc-6d624e298c24 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577656614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3577656614 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.835393331 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 1625365829 ps |
CPU time | 3.43 seconds |
Started | Jul 14 04:52:10 PM PDT 24 |
Finished | Jul 14 04:52:13 PM PDT 24 |
Peak memory | 202184 kb |
Host | smart-9991653b-546f-4e3e-9d35-ebb6372d25d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835393331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.835393331 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2558296928 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 85965589 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:52:10 PM PDT 24 |
Finished | Jul 14 04:52:11 PM PDT 24 |
Peak memory | 201824 kb |
Host | smart-82ba0452-3f13-42c2-bbfe-f68ebe564e2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558296928 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2558296928 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.810889982 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 195778773 ps |
CPU time | 4.63 seconds |
Started | Jul 14 04:52:08 PM PDT 24 |
Finished | Jul 14 04:52:13 PM PDT 24 |
Peak memory | 210260 kb |
Host | smart-769bbb56-5f18-4a4e-ad26-5249c1a1c9bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810889982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.810889982 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4101223945 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 602006980 ps |
CPU time | 2.05 seconds |
Started | Jul 14 04:52:14 PM PDT 24 |
Finished | Jul 14 04:52:17 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-64885833-90ba-4693-848f-803f47b27b3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101223945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.4101223945 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3508735325 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 51711437 ps |
CPU time | 1.1 seconds |
Started | Jul 14 04:52:17 PM PDT 24 |
Finished | Jul 14 04:52:19 PM PDT 24 |
Peak memory | 210108 kb |
Host | smart-e0e5e8ee-8bbf-4b46-ac55-22eacf5d43c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508735325 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3508735325 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.518616642 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 20644582 ps |
CPU time | 0.68 seconds |
Started | Jul 14 04:52:09 PM PDT 24 |
Finished | Jul 14 04:52:10 PM PDT 24 |
Peak memory | 201744 kb |
Host | smart-86c56249-ee55-43f8-9e05-a931607e8b87 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518616642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_csr_rw.518616642 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3850735274 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 1562862966 ps |
CPU time | 3.52 seconds |
Started | Jul 14 04:52:09 PM PDT 24 |
Finished | Jul 14 04:52:13 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-cca9a4ce-ef04-4a89-8dce-f60eb7afa778 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850735274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3850735274 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1822714472 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 37814444 ps |
CPU time | 0.75 seconds |
Started | Jul 14 04:52:21 PM PDT 24 |
Finished | Jul 14 04:52:22 PM PDT 24 |
Peak memory | 201816 kb |
Host | smart-a0648926-24d7-4b13-86af-d6f2c56b14f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822714472 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1822714472 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2785409465 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 38201025 ps |
CPU time | 2.08 seconds |
Started | Jul 14 04:52:08 PM PDT 24 |
Finished | Jul 14 04:52:10 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-12c76934-3c9b-4009-9f34-43092c0d812a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785409465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2785409465 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2975284138 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 370905836 ps |
CPU time | 1.45 seconds |
Started | Jul 14 04:52:07 PM PDT 24 |
Finished | Jul 14 04:52:09 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-6db89483-9588-423d-abd0-83ef25291c7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975284138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2975284138 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2558366379 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 73501002 ps |
CPU time | 1.38 seconds |
Started | Jul 14 04:52:16 PM PDT 24 |
Finished | Jul 14 04:52:18 PM PDT 24 |
Peak memory | 211564 kb |
Host | smart-a6ea928e-fb14-471d-a413-af379b4897b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558366379 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2558366379 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1095927217 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 19573228 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:52:17 PM PDT 24 |
Finished | Jul 14 04:52:19 PM PDT 24 |
Peak memory | 201292 kb |
Host | smart-9ef93e4f-15f7-4c88-9afe-ec3bbf7f781f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095927217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.1095927217 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3863970184 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 1594493750 ps |
CPU time | 3.47 seconds |
Started | Jul 14 04:52:15 PM PDT 24 |
Finished | Jul 14 04:52:19 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-c24e9dbe-aca4-4faa-bb5a-234330e61c6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863970184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3863970184 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1631390584 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 29247030 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:52:17 PM PDT 24 |
Finished | Jul 14 04:52:18 PM PDT 24 |
Peak memory | 201836 kb |
Host | smart-14cd19dc-e804-4efd-bae8-5dfe209f19ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631390584 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1631390584 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2289132937 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 52698783 ps |
CPU time | 2.56 seconds |
Started | Jul 14 04:52:17 PM PDT 24 |
Finished | Jul 14 04:52:20 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-36171ee5-7284-489c-b854-b1ea822de02c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289132937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2289132937 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2078439271 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 329969160 ps |
CPU time | 1.48 seconds |
Started | Jul 14 04:52:16 PM PDT 24 |
Finished | Jul 14 04:52:18 PM PDT 24 |
Peak memory | 210200 kb |
Host | smart-8265cd1b-ea21-40ab-a035-c3e64bfea581 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078439271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2078439271 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.353390265 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 34373226 ps |
CPU time | 2 seconds |
Started | Jul 14 04:52:25 PM PDT 24 |
Finished | Jul 14 04:52:27 PM PDT 24 |
Peak memory | 210312 kb |
Host | smart-a255a7af-415f-4dd5-a253-be0d943b7ce5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353390265 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.353390265 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1445058771 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 15765425 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:52:16 PM PDT 24 |
Finished | Jul 14 04:52:18 PM PDT 24 |
Peak memory | 201780 kb |
Host | smart-c00d8c1f-9836-41ef-9e5e-3b9b169cdd87 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445058771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.1445058771 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3111566865 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 409248498 ps |
CPU time | 3.36 seconds |
Started | Jul 14 04:52:16 PM PDT 24 |
Finished | Jul 14 04:52:20 PM PDT 24 |
Peak memory | 202192 kb |
Host | smart-e423710a-9708-43c5-b0b7-b02e17df1ab3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111566865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3111566865 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4294730970 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 46514416 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:28 PM PDT 24 |
Peak memory | 201856 kb |
Host | smart-0e0fcca1-47c6-44d0-b6b9-e4dfb632ad4d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294730970 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.4294730970 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3799338305 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 163232464 ps |
CPU time | 2.77 seconds |
Started | Jul 14 04:52:16 PM PDT 24 |
Finished | Jul 14 04:52:19 PM PDT 24 |
Peak memory | 210340 kb |
Host | smart-cd11682d-f5c9-4a19-a56e-700ad97d8c49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799338305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.3799338305 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4010608876 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 469139081 ps |
CPU time | 1.95 seconds |
Started | Jul 14 04:52:21 PM PDT 24 |
Finished | Jul 14 04:52:24 PM PDT 24 |
Peak memory | 210224 kb |
Host | smart-cfc76540-019e-40ce-adf3-1223293c0bec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010608876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.4010608876 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3416430469 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 62455176 ps |
CPU time | 1.16 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:27 PM PDT 24 |
Peak memory | 210144 kb |
Host | smart-7f261746-0c05-486d-aea3-aa1a72f55c4d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416430469 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3416430469 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2333556798 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 30212435 ps |
CPU time | 0.63 seconds |
Started | Jul 14 04:52:29 PM PDT 24 |
Finished | Jul 14 04:52:31 PM PDT 24 |
Peak memory | 201724 kb |
Host | smart-2284e595-20bd-4bad-8f88-ed7b919c9b79 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333556798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2333556798 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3068737988 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 405861507 ps |
CPU time | 3.33 seconds |
Started | Jul 14 04:52:24 PM PDT 24 |
Finished | Jul 14 04:52:28 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-8a488196-7249-438a-9189-01c7929aa9e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068737988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3068737988 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.740335095 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 16360342 ps |
CPU time | 0.74 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:27 PM PDT 24 |
Peak memory | 201808 kb |
Host | smart-eab50319-e7e4-4a8c-ba53-64dc28294f6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740335095 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.740335095 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.862467758 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 498304175 ps |
CPU time | 4.92 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:31 PM PDT 24 |
Peak memory | 211616 kb |
Host | smart-3c920858-b3ad-4a2d-913e-5b59668709cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862467758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.862467758 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1819365761 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 683723986 ps |
CPU time | 1.47 seconds |
Started | Jul 14 04:52:26 PM PDT 24 |
Finished | Jul 14 04:52:28 PM PDT 24 |
Peak memory | 210236 kb |
Host | smart-f0686136-b6d6-4145-b090-8d6a1317c49a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819365761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1819365761 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2671932152 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 5568602514 ps |
CPU time | 1290.96 seconds |
Started | Jul 14 04:53:47 PM PDT 24 |
Finished | Jul 14 05:15:18 PM PDT 24 |
Peak memory | 370540 kb |
Host | smart-9a9042c2-c5de-4723-b8b0-2546ef8bd5de |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671932152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.2671932152 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.1071465034 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 13001325 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:53:49 PM PDT 24 |
Finished | Jul 14 04:53:50 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-86724295-fce6-4051-8592-be2e5a2a8399 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071465034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1071465034 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.2071816846 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 20690033416 ps |
CPU time | 47.64 seconds |
Started | Jul 14 04:53:45 PM PDT 24 |
Finished | Jul 14 04:54:33 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-5f7fce8b-4bef-4c11-9414-e65163eb280c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071816846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 2071816846 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.3471046919 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 44714024236 ps |
CPU time | 459.82 seconds |
Started | Jul 14 04:53:49 PM PDT 24 |
Finished | Jul 14 05:01:30 PM PDT 24 |
Peak memory | 359260 kb |
Host | smart-60dd175a-ff3d-430a-959f-31eb7a6f0e56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471046919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3471046919 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.2300681420 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 687345029 ps |
CPU time | 7.97 seconds |
Started | Jul 14 04:53:49 PM PDT 24 |
Finished | Jul 14 04:53:58 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-146ac1b1-91fc-4bda-b0c1-4902f663f0fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300681420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.2300681420 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.3650660437 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 123437084 ps |
CPU time | 63.92 seconds |
Started | Jul 14 04:53:45 PM PDT 24 |
Finished | Jul 14 04:54:50 PM PDT 24 |
Peak memory | 310028 kb |
Host | smart-e09efcb5-8d30-4ef3-9d89-667efd518e19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650660437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.3650660437 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3104278389 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 748519029 ps |
CPU time | 6.18 seconds |
Started | Jul 14 04:53:45 PM PDT 24 |
Finished | Jul 14 04:53:51 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-652e8268-96b3-4e35-804f-bcc4b60221d6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104278389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.3104278389 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.853600010 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1320517524 ps |
CPU time | 6.23 seconds |
Started | Jul 14 04:53:49 PM PDT 24 |
Finished | Jul 14 04:53:56 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-15e67695-48df-4c5f-a5f1-ab6ded4db91c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853600010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ mem_walk.853600010 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.2623769649 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 45630658180 ps |
CPU time | 1106.79 seconds |
Started | Jul 14 04:53:46 PM PDT 24 |
Finished | Jul 14 05:12:13 PM PDT 24 |
Peak memory | 373616 kb |
Host | smart-79e1dcc2-62fe-4d95-aec1-7d3878c3b2ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623769649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.2623769649 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.1851731871 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 553374863 ps |
CPU time | 76.18 seconds |
Started | Jul 14 04:53:47 PM PDT 24 |
Finished | Jul 14 04:55:04 PM PDT 24 |
Peak memory | 313896 kb |
Host | smart-83bc9bd6-56e5-4837-b44d-be4a27b4f277 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851731871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1851731871 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2835131663 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 6578305891 ps |
CPU time | 491 seconds |
Started | Jul 14 04:53:47 PM PDT 24 |
Finished | Jul 14 05:01:59 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-7be2ccf8-8cc6-465d-b2c0-ea22b9b7b102 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835131663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.2835131663 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.439876511 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 29240612 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:53:47 PM PDT 24 |
Finished | Jul 14 04:53:48 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-39d6fb1d-7a20-4aa8-890a-240fb8a53365 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439876511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.439876511 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.2607539141 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 4938606668 ps |
CPU time | 603.39 seconds |
Started | Jul 14 04:53:46 PM PDT 24 |
Finished | Jul 14 05:03:50 PM PDT 24 |
Peak memory | 365472 kb |
Host | smart-7df6c3fc-2adf-4cbf-91ab-63f94ac05efb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607539141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2607539141 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3387371499 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 402532082 ps |
CPU time | 2 seconds |
Started | Jul 14 04:53:46 PM PDT 24 |
Finished | Jul 14 04:53:48 PM PDT 24 |
Peak memory | 221792 kb |
Host | smart-edec0cee-3ac5-4e0a-9fc0-3ba5ab8ad98f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387371499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3387371499 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.3465765518 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 775260785 ps |
CPU time | 27.58 seconds |
Started | Jul 14 04:53:47 PM PDT 24 |
Finished | Jul 14 04:54:15 PM PDT 24 |
Peak memory | 278412 kb |
Host | smart-43832770-eb00-46fe-b371-9365150c0fd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465765518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3465765518 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.2864630375 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 9909906647 ps |
CPU time | 2435.26 seconds |
Started | Jul 14 04:53:45 PM PDT 24 |
Finished | Jul 14 05:34:21 PM PDT 24 |
Peak memory | 374996 kb |
Host | smart-95ea5753-e496-48d9-8faa-1a19c913532e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864630375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.2864630375 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.239908217 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 12589280228 ps |
CPU time | 244.55 seconds |
Started | Jul 14 04:53:47 PM PDT 24 |
Finished | Jul 14 04:57:52 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-23fe4861-3386-4431-af5c-0e1fc9013529 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239908217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_stress_pipeline.239908217 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3131826281 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 141208785 ps |
CPU time | 105.68 seconds |
Started | Jul 14 04:53:46 PM PDT 24 |
Finished | Jul 14 04:55:33 PM PDT 24 |
Peak memory | 348096 kb |
Host | smart-b76089ae-e824-43ff-9af4-a3d830a392b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131826281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3131826281 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.591462745 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 6149464353 ps |
CPU time | 1364.45 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 05:16:40 PM PDT 24 |
Peak memory | 375624 kb |
Host | smart-bf020740-40c3-45b9-ade4-2507e7a62a4f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591462745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.sram_ctrl_access_during_key_req.591462745 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.1044889116 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 79601337 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 04:53:56 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-eec8848c-7744-4640-8fab-900f23e88608 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044889116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1044889116 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.3539459033 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 16530327866 ps |
CPU time | 60.33 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 04:54:54 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-b2f1b39b-acef-4149-b00c-3d1e45428446 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539459033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3539459033 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.3754335593 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 5319362321 ps |
CPU time | 298.66 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 04:58:53 PM PDT 24 |
Peak memory | 353540 kb |
Host | smart-c4fd8491-7db6-45ce-b39b-00abc8b8ecc8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754335593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3754335593 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.3997340057 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 565227907 ps |
CPU time | 2.13 seconds |
Started | Jul 14 04:53:55 PM PDT 24 |
Finished | Jul 14 04:53:58 PM PDT 24 |
Peak memory | 214000 kb |
Host | smart-36637bc1-098b-4f56-a0ef-53c8320d5bb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997340057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.3997340057 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.4070298511 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 261851321 ps |
CPU time | 124.38 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 04:55:58 PM PDT 24 |
Peak memory | 365264 kb |
Host | smart-f94f9146-66e6-46c8-a431-58fd88d96fb8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070298511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.4070298511 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.953690270 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 1971211641 ps |
CPU time | 4.1 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 04:54:00 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-7c4e244e-fb58-4582-acf2-9fda6196cb5b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953690270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_mem_partial_access.953690270 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.2561902558 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 4369641009 ps |
CPU time | 14.63 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 04:54:09 PM PDT 24 |
Peak memory | 211188 kb |
Host | smart-b8e02856-69cd-4e2e-853f-b843e4512977 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561902558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.2561902558 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.571388745 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 97037112175 ps |
CPU time | 1742.51 seconds |
Started | Jul 14 04:53:57 PM PDT 24 |
Finished | Jul 14 05:23:00 PM PDT 24 |
Peak memory | 375624 kb |
Host | smart-fc040756-f38b-44a6-9641-f11597a7644d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571388745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl e_keys.571388745 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.3144376355 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 637905727 ps |
CPU time | 13.24 seconds |
Started | Jul 14 04:53:55 PM PDT 24 |
Finished | Jul 14 04:54:09 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-a2bfeb3d-0e8d-44a1-a482-dc1e8b8d0cf3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144376355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3144376355 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3774811000 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 11587706721 ps |
CPU time | 279.51 seconds |
Started | Jul 14 04:53:57 PM PDT 24 |
Finished | Jul 14 04:58:37 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-fdcab9ae-2588-40df-9604-e16cff2bcccb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774811000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.3774811000 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.1544561992 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 29392022 ps |
CPU time | 0.83 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 04:53:56 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-ced7204b-b44d-4088-b877-f87fb0842649 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544561992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1544561992 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.2332501403 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 346685943 ps |
CPU time | 1.88 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 04:53:56 PM PDT 24 |
Peak memory | 232540 kb |
Host | smart-1724366e-0233-493d-bc93-5624e6301a98 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332501403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2332501403 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.1494018020 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 214775144 ps |
CPU time | 4.72 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 04:54:00 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-4f87120a-57c4-4847-aeec-db701ab12f2c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494018020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1494018020 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.2067089384 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 114223981455 ps |
CPU time | 1220.35 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 05:14:15 PM PDT 24 |
Peak memory | 375748 kb |
Host | smart-5554c2d9-cddb-4af8-9889-ad74ff0ec83c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067089384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.2067089384 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1697136381 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1712525920 ps |
CPU time | 526.62 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 05:02:41 PM PDT 24 |
Peak memory | 366188 kb |
Host | smart-3cf197de-c9db-4322-8232-044eb37b779c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1697136381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1697136381 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.566331394 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 3057670495 ps |
CPU time | 290.61 seconds |
Started | Jul 14 04:53:55 PM PDT 24 |
Finished | Jul 14 04:58:47 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-52e20b88-4a41-4574-9417-7149040d16d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566331394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_stress_pipeline.566331394 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.587488321 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 699146867 ps |
CPU time | 31.27 seconds |
Started | Jul 14 04:53:56 PM PDT 24 |
Finished | Jul 14 04:54:28 PM PDT 24 |
Peak memory | 287536 kb |
Host | smart-95748474-86a0-48eb-989b-0f50f220e687 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587488321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.587488321 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2523801212 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 3924761334 ps |
CPU time | 942.02 seconds |
Started | Jul 14 04:54:46 PM PDT 24 |
Finished | Jul 14 05:10:29 PM PDT 24 |
Peak memory | 360752 kb |
Host | smart-d6903f96-ae7a-46b6-a111-dd8ee577c02a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523801212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.2523801212 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.636344013 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 16834373 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:54:50 PM PDT 24 |
Finished | Jul 14 04:54:51 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-4edd99e8-dbcb-424e-b594-7833ff345b53 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636344013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.636344013 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.533637246 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1000613204 ps |
CPU time | 56.42 seconds |
Started | Jul 14 04:54:45 PM PDT 24 |
Finished | Jul 14 04:55:43 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-74559ccb-c200-4cd3-b82a-ded5befd87cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533637246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection. 533637246 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.397391194 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 11692128498 ps |
CPU time | 1256.42 seconds |
Started | Jul 14 04:54:44 PM PDT 24 |
Finished | Jul 14 05:15:41 PM PDT 24 |
Peak memory | 374704 kb |
Host | smart-6ffe2b0e-1eed-4a95-8109-34be423fc209 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397391194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl e.397391194 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.3126445369 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 641637209 ps |
CPU time | 6.45 seconds |
Started | Jul 14 04:54:47 PM PDT 24 |
Finished | Jul 14 04:54:54 PM PDT 24 |
Peak memory | 214196 kb |
Host | smart-971fe422-ee79-465d-a6e0-974c650056fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126445369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.3126445369 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.316689887 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 491672816 ps |
CPU time | 3.7 seconds |
Started | Jul 14 04:54:44 PM PDT 24 |
Finished | Jul 14 04:54:48 PM PDT 24 |
Peak memory | 219128 kb |
Host | smart-be7abba1-c613-493f-b9c1-2314addf07a1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316689887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_max_throughput.316689887 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2514643370 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 791258864 ps |
CPU time | 6.69 seconds |
Started | Jul 14 04:54:44 PM PDT 24 |
Finished | Jul 14 04:54:51 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-e3d14ca3-01db-404f-a24f-57efaa026a8b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514643370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.2514643370 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.4033316003 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1508983476 ps |
CPU time | 5.68 seconds |
Started | Jul 14 04:54:45 PM PDT 24 |
Finished | Jul 14 04:54:52 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-e4fbc185-67aa-4107-af92-afadc438ed74 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033316003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.4033316003 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.3773228160 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 3428964986 ps |
CPU time | 781.55 seconds |
Started | Jul 14 04:54:37 PM PDT 24 |
Finished | Jul 14 05:07:39 PM PDT 24 |
Peak memory | 375708 kb |
Host | smart-a8e5d50c-d6f7-4cd4-8944-dec53f62d818 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773228160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.3773228160 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3913544463 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 3192936095 ps |
CPU time | 15.96 seconds |
Started | Jul 14 04:54:45 PM PDT 24 |
Finished | Jul 14 04:55:02 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-5bb56709-78c2-4738-97e2-35e711347475 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913544463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3913544463 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.543322767 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 38830229023 ps |
CPU time | 551.32 seconds |
Started | Jul 14 04:54:47 PM PDT 24 |
Finished | Jul 14 05:03:59 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-3851d728-0ebe-4b12-8f4d-273c91ee49fb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543322767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.sram_ctrl_partial_access_b2b.543322767 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.1025336432 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 28475628 ps |
CPU time | 0.79 seconds |
Started | Jul 14 04:54:46 PM PDT 24 |
Finished | Jul 14 04:54:47 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-36b7229a-b34f-4aab-bca1-bdbc0f855dac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025336432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1025336432 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.535920996 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 6700986271 ps |
CPU time | 1010.51 seconds |
Started | Jul 14 04:54:43 PM PDT 24 |
Finished | Jul 14 05:11:35 PM PDT 24 |
Peak memory | 368036 kb |
Host | smart-f1208f6e-042c-4abf-9612-92de5b1e15e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535920996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.535920996 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.20669280 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 253980227 ps |
CPU time | 10.98 seconds |
Started | Jul 14 04:54:36 PM PDT 24 |
Finished | Jul 14 04:54:48 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-d33be48d-0a5a-449f-9d4d-4f7744e0d3ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20669280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.20669280 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.2291490120 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 27472219596 ps |
CPU time | 1375.19 seconds |
Started | Jul 14 04:54:50 PM PDT 24 |
Finished | Jul 14 05:17:46 PM PDT 24 |
Peak memory | 374656 kb |
Host | smart-37dfd822-96a7-42c3-b698-3cf9543afc69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291490120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.2291490120 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3470358721 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 4116426535 ps |
CPU time | 384.02 seconds |
Started | Jul 14 04:54:45 PM PDT 24 |
Finished | Jul 14 05:01:09 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-73066f21-2118-4d7d-ae35-e845f6a6bd7f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470358721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.3470358721 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2929489805 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 213369868 ps |
CPU time | 65.32 seconds |
Started | Jul 14 04:54:45 PM PDT 24 |
Finished | Jul 14 04:55:51 PM PDT 24 |
Peak memory | 309684 kb |
Host | smart-183b9640-151e-4e0c-abd6-8fa1483c2a28 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929489805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2929489805 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1383726614 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 3362479732 ps |
CPU time | 585.68 seconds |
Started | Jul 14 04:54:52 PM PDT 24 |
Finished | Jul 14 05:04:39 PM PDT 24 |
Peak memory | 363472 kb |
Host | smart-88b739cb-8717-4b41-a802-f066763bc396 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383726614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.1383726614 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.2922986890 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 28307175 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:54:56 PM PDT 24 |
Finished | Jul 14 04:54:57 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-289efc74-7f96-4190-9341-41c42f0a7231 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922986890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2922986890 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.2087480594 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 4560686015 ps |
CPU time | 32.7 seconds |
Started | Jul 14 04:54:50 PM PDT 24 |
Finished | Jul 14 04:55:24 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-cf094399-f459-4e6e-a45e-d114f9d3c5a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087480594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .2087480594 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.4015553181 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 4202348551 ps |
CPU time | 856.27 seconds |
Started | Jul 14 04:54:51 PM PDT 24 |
Finished | Jul 14 05:09:08 PM PDT 24 |
Peak memory | 372600 kb |
Host | smart-40dce32e-a7c6-41be-9129-79854a64b16e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015553181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.4015553181 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.386860477 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 315678920 ps |
CPU time | 3.49 seconds |
Started | Jul 14 04:54:51 PM PDT 24 |
Finished | Jul 14 04:54:55 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-7a6dae54-d21c-427b-a125-312a8ac21a83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386860477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_esc alation.386860477 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.1383296753 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 296278952 ps |
CPU time | 143.42 seconds |
Started | Jul 14 04:54:52 PM PDT 24 |
Finished | Jul 14 04:57:16 PM PDT 24 |
Peak memory | 368156 kb |
Host | smart-b3e2713b-d3e8-4d18-9910-9c94012abc3f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383296753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.1383296753 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3498265128 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 275049116 ps |
CPU time | 4.98 seconds |
Started | Jul 14 04:54:56 PM PDT 24 |
Finished | Jul 14 04:55:01 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-e2c15b5c-5bd6-4e65-9354-54bbf5da4e55 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498265128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3498265128 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.4074300411 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 448691493 ps |
CPU time | 10.47 seconds |
Started | Jul 14 04:54:56 PM PDT 24 |
Finished | Jul 14 04:55:06 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-e337e277-78af-4841-b04d-8243411354e1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074300411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.4074300411 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.4211153379 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 5519395583 ps |
CPU time | 1252.03 seconds |
Started | Jul 14 04:54:52 PM PDT 24 |
Finished | Jul 14 05:15:44 PM PDT 24 |
Peak memory | 373652 kb |
Host | smart-b6abd9f0-c910-488e-b69a-65df64f36acc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211153379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.4211153379 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.2358008245 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 2988757497 ps |
CPU time | 85.34 seconds |
Started | Jul 14 04:54:51 PM PDT 24 |
Finished | Jul 14 04:56:17 PM PDT 24 |
Peak memory | 339404 kb |
Host | smart-7b03c929-451d-4b43-ba7c-24f4788ee8c6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358008245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.2358008245 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3706158447 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 23256605871 ps |
CPU time | 433.19 seconds |
Started | Jul 14 04:54:50 PM PDT 24 |
Finished | Jul 14 05:02:04 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-79b7d9b8-10e0-4351-bc76-79754390e675 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706158447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3706158447 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.1911526859 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 32541274 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:54:57 PM PDT 24 |
Finished | Jul 14 04:54:58 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-d9c7b13f-8300-4a6e-9474-741f5742acee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911526859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1911526859 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.3873540424 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 4280200235 ps |
CPU time | 562.69 seconds |
Started | Jul 14 04:54:52 PM PDT 24 |
Finished | Jul 14 05:04:16 PM PDT 24 |
Peak memory | 361124 kb |
Host | smart-c2905e10-139f-4f9b-8de6-587dd332b4a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873540424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3873540424 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.3762450810 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 150798313 ps |
CPU time | 9.23 seconds |
Started | Jul 14 04:54:54 PM PDT 24 |
Finished | Jul 14 04:55:03 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-44addd5c-89a7-4467-9b68-8ce1d9dca1ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762450810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3762450810 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.3761632677 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 409030079546 ps |
CPU time | 2403.88 seconds |
Started | Jul 14 04:54:56 PM PDT 24 |
Finished | Jul 14 05:35:00 PM PDT 24 |
Peak memory | 383500 kb |
Host | smart-4869b3e1-4156-498c-8fbd-99bbfafa8e4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761632677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.3761632677 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1199600081 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 17631189785 ps |
CPU time | 233.02 seconds |
Started | Jul 14 04:54:50 PM PDT 24 |
Finished | Jul 14 04:58:43 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-a96e696b-f7d3-429b-8f75-0832c7c3bf19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199600081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1199600081 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.334202647 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 1595620841 ps |
CPU time | 159.58 seconds |
Started | Jul 14 04:54:52 PM PDT 24 |
Finished | Jul 14 04:57:32 PM PDT 24 |
Peak memory | 368236 kb |
Host | smart-a9cfa5b6-4c61-49d5-8a86-bec9e6c94194 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334202647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.334202647 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2494278860 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 3034605692 ps |
CPU time | 811.11 seconds |
Started | Jul 14 04:55:00 PM PDT 24 |
Finished | Jul 14 05:08:32 PM PDT 24 |
Peak memory | 373160 kb |
Host | smart-37e0b4be-bf42-4bc2-b02b-4fd2d2138886 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494278860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.2494278860 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.2965541120 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 22190791 ps |
CPU time | 0.68 seconds |
Started | Jul 14 04:55:01 PM PDT 24 |
Finished | Jul 14 04:55:03 PM PDT 24 |
Peak memory | 202516 kb |
Host | smart-f43fc1bd-a8bc-4293-8848-9c1de775ce1f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965541120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2965541120 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.3976324253 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 2385769143 ps |
CPU time | 43.5 seconds |
Started | Jul 14 04:55:00 PM PDT 24 |
Finished | Jul 14 04:55:44 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-81b0385d-e3c0-499a-88be-21d54c5dda3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976324253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .3976324253 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.4184637889 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 10554131931 ps |
CPU time | 845.24 seconds |
Started | Jul 14 04:55:03 PM PDT 24 |
Finished | Jul 14 05:09:09 PM PDT 24 |
Peak memory | 374684 kb |
Host | smart-961c12ad-28e1-481d-9f58-7ce180ce7d45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184637889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.4184637889 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.1104612234 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 527687071 ps |
CPU time | 5.6 seconds |
Started | Jul 14 04:55:01 PM PDT 24 |
Finished | Jul 14 04:55:08 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-e14dbe8a-eecb-4c06-b1cb-21e79bd61722 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104612234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1104612234 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.2598965133 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 923133962 ps |
CPU time | 150.72 seconds |
Started | Jul 14 04:55:04 PM PDT 24 |
Finished | Jul 14 04:57:35 PM PDT 24 |
Peak memory | 369244 kb |
Host | smart-8a3e133a-a404-40f7-9f41-aec9517b9cc4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598965133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.2598965133 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.4116819106 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 95379854 ps |
CPU time | 5.19 seconds |
Started | Jul 14 04:55:02 PM PDT 24 |
Finished | Jul 14 04:55:08 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-e960a741-58db-4449-9cc4-453caacc3a69 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116819106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.4116819106 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.1515545634 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 694426155 ps |
CPU time | 6.63 seconds |
Started | Jul 14 04:55:04 PM PDT 24 |
Finished | Jul 14 04:55:12 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-567c496e-d018-45df-9883-e9b5d3097aad |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515545634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1515545634 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.1745457964 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 8687831427 ps |
CPU time | 350.71 seconds |
Started | Jul 14 04:54:57 PM PDT 24 |
Finished | Jul 14 05:00:49 PM PDT 24 |
Peak memory | 371508 kb |
Host | smart-a922aa42-2937-46a0-b6a9-df91091a165d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745457964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.1745457964 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.1487787414 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 41615249 ps |
CPU time | 2.15 seconds |
Started | Jul 14 04:54:56 PM PDT 24 |
Finished | Jul 14 04:54:59 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-7bda250e-c0cd-4c45-a50e-114ff4644e8a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487787414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.1487787414 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.705813962 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 3659961731 ps |
CPU time | 279.05 seconds |
Started | Jul 14 04:55:01 PM PDT 24 |
Finished | Jul 14 04:59:41 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-0d4caaca-c556-4d9c-85e0-f0ee82783958 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705813962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.sram_ctrl_partial_access_b2b.705813962 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.3198067581 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 35293887 ps |
CPU time | 0.79 seconds |
Started | Jul 14 04:55:01 PM PDT 24 |
Finished | Jul 14 04:55:02 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-7e2ec281-4a5d-427f-9a7d-325292998455 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198067581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3198067581 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.3629207962 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 11097352558 ps |
CPU time | 641.72 seconds |
Started | Jul 14 04:55:02 PM PDT 24 |
Finished | Jul 14 05:05:45 PM PDT 24 |
Peak memory | 375512 kb |
Host | smart-0759f46b-0629-4626-8464-15c5808a3706 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629207962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3629207962 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.379843746 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 176525281 ps |
CPU time | 3.58 seconds |
Started | Jul 14 04:54:58 PM PDT 24 |
Finished | Jul 14 04:55:02 PM PDT 24 |
Peak memory | 216584 kb |
Host | smart-c69dea04-0633-49ae-b63e-ecab577aad5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379843746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.379843746 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.2758483704 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 60224390461 ps |
CPU time | 3146.8 seconds |
Started | Jul 14 04:55:02 PM PDT 24 |
Finished | Jul 14 05:47:30 PM PDT 24 |
Peak memory | 376656 kb |
Host | smart-763bc7d9-20fb-4548-b618-865efeaf1347 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758483704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.2758483704 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1705225100 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 2316188708 ps |
CPU time | 11.82 seconds |
Started | Jul 14 04:55:02 PM PDT 24 |
Finished | Jul 14 04:55:14 PM PDT 24 |
Peak memory | 211256 kb |
Host | smart-4acefb4c-427f-48aa-88d2-75bdb98d0df6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1705225100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1705225100 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2222995372 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 3457825341 ps |
CPU time | 322.29 seconds |
Started | Jul 14 04:54:56 PM PDT 24 |
Finished | Jul 14 05:00:19 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d23aad40-d5ad-4953-9bec-865734ab0bc6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222995372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2222995372 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1684527066 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 38783969 ps |
CPU time | 1.18 seconds |
Started | Jul 14 04:55:01 PM PDT 24 |
Finished | Jul 14 04:55:03 PM PDT 24 |
Peak memory | 210748 kb |
Host | smart-30ba61bb-7ea2-424b-b0eb-3292fd7dc7d4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684527066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1684527066 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1624684796 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 2466492203 ps |
CPU time | 905.25 seconds |
Started | Jul 14 04:55:09 PM PDT 24 |
Finished | Jul 14 05:10:14 PM PDT 24 |
Peak memory | 367444 kb |
Host | smart-a4b758c6-c10c-4e7e-999f-1305bbbd54d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624684796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1624684796 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.2425784977 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 42077997 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:55:16 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-76a91942-b323-4a73-970c-925843ca155b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425784977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2425784977 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.537268694 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 1665079882 ps |
CPU time | 35.97 seconds |
Started | Jul 14 04:55:02 PM PDT 24 |
Finished | Jul 14 04:55:39 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-6a505e6a-982c-494c-82d6-ad7456afa62d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537268694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection. 537268694 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.135625392 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 71019969637 ps |
CPU time | 1468.49 seconds |
Started | Jul 14 04:55:07 PM PDT 24 |
Finished | Jul 14 05:19:37 PM PDT 24 |
Peak memory | 374084 kb |
Host | smart-994dc0ef-45be-4913-8a21-34cd53306aca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135625392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executabl e.135625392 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.4179739537 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 317924853 ps |
CPU time | 4.45 seconds |
Started | Jul 14 04:55:09 PM PDT 24 |
Finished | Jul 14 04:55:14 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-e9fe6638-713b-4a9e-819f-e443202eff51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179739537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.4179739537 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.2749007788 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 70714148 ps |
CPU time | 14.02 seconds |
Started | Jul 14 04:55:07 PM PDT 24 |
Finished | Jul 14 04:55:22 PM PDT 24 |
Peak memory | 251760 kb |
Host | smart-3782754b-12ba-4a37-b244-f009ed4069ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749007788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2749007788 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3614851928 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 474351520 ps |
CPU time | 3.1 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:55:18 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-bc1dc078-3d1b-4280-a8d9-dd80394e8285 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614851928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.3614851928 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.3051560700 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 909359333 ps |
CPU time | 6.44 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:55:21 PM PDT 24 |
Peak memory | 210948 kb |
Host | smart-a13c7dba-0cf5-458c-9066-a458a52db16e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051560700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.3051560700 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.705040190 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 18962754023 ps |
CPU time | 1284 seconds |
Started | Jul 14 04:55:02 PM PDT 24 |
Finished | Jul 14 05:16:27 PM PDT 24 |
Peak memory | 372412 kb |
Host | smart-11504dae-2f4f-42cb-8816-b53dceb52048 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705040190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.705040190 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2406888030 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 195432703 ps |
CPU time | 1.83 seconds |
Started | Jul 14 04:55:07 PM PDT 24 |
Finished | Jul 14 04:55:10 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-22823b15-e3e2-4e5b-9f52-a01e64fb8da3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406888030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2406888030 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1420712975 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 6480193766 ps |
CPU time | 266.89 seconds |
Started | Jul 14 04:55:09 PM PDT 24 |
Finished | Jul 14 04:59:36 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-9fcfd4de-7508-4476-9fa1-ecc047770436 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420712975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.1420712975 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.1841996891 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 232228377 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:55:16 PM PDT 24 |
Finished | Jul 14 04:55:17 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-be6867c9-3f35-48d4-8cf0-34b41ff02208 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841996891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1841996891 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.63063164 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 28138861529 ps |
CPU time | 1210.27 seconds |
Started | Jul 14 04:55:13 PM PDT 24 |
Finished | Jul 14 05:15:24 PM PDT 24 |
Peak memory | 374616 kb |
Host | smart-07278928-f860-485f-8806-e286dc939275 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63063164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.63063164 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.1964446966 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 150852877 ps |
CPU time | 8.61 seconds |
Started | Jul 14 04:55:01 PM PDT 24 |
Finished | Jul 14 04:55:10 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-0a3b87e6-e210-478a-b3cd-bc9c37549db3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964446966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1964446966 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.3820198589 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 35233205359 ps |
CPU time | 2173.33 seconds |
Started | Jul 14 04:55:15 PM PDT 24 |
Finished | Jul 14 05:31:29 PM PDT 24 |
Peak memory | 376056 kb |
Host | smart-751124af-4e26-4903-967b-8008dbeb753d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820198589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.3820198589 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.932942991 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 4176963552 ps |
CPU time | 305.84 seconds |
Started | Jul 14 04:55:09 PM PDT 24 |
Finished | Jul 14 05:00:15 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-8c101a20-db71-4359-b456-c6a47fec191b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932942991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .sram_ctrl_stress_pipeline.932942991 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2148259984 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 162402388 ps |
CPU time | 170.06 seconds |
Started | Jul 14 04:55:08 PM PDT 24 |
Finished | Jul 14 04:57:59 PM PDT 24 |
Peak memory | 369192 kb |
Host | smart-f5077369-a768-4e0b-acab-66cef9c895fb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148259984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2148259984 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2376871410 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 6940775366 ps |
CPU time | 396.72 seconds |
Started | Jul 14 04:55:23 PM PDT 24 |
Finished | Jul 14 05:02:00 PM PDT 24 |
Peak memory | 368816 kb |
Host | smart-197fdb63-fdf1-4b7a-ba74-1cefe27fd9fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376871410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.2376871410 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.3253571326 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 16828074 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:55:21 PM PDT 24 |
Finished | Jul 14 04:55:22 PM PDT 24 |
Peak memory | 202464 kb |
Host | smart-8631b79e-08a4-4d25-a4c6-9c0c45aa4b26 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253571326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3253571326 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.2779600228 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 16417795967 ps |
CPU time | 56.11 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:56:11 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-5a17ad7d-7cd7-42c4-aa82-825e013e36a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779600228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .2779600228 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.1663389626 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 8416623594 ps |
CPU time | 800.65 seconds |
Started | Jul 14 04:55:20 PM PDT 24 |
Finished | Jul 14 05:08:41 PM PDT 24 |
Peak memory | 375228 kb |
Host | smart-b954cb05-b255-4b79-a11b-9bd52182855a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663389626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.1663389626 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.3808975316 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 251792744 ps |
CPU time | 2.82 seconds |
Started | Jul 14 04:55:20 PM PDT 24 |
Finished | Jul 14 04:55:23 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-408b1cc5-9564-4009-9881-5a774d1700b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808975316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.3808975316 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.2899814956 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 246482058 ps |
CPU time | 71.06 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:56:26 PM PDT 24 |
Peak memory | 312504 kb |
Host | smart-a7bb3932-43a4-47e3-a672-8d5daa229636 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899814956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.2899814956 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3475646106 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 302574641 ps |
CPU time | 5.15 seconds |
Started | Jul 14 04:55:24 PM PDT 24 |
Finished | Jul 14 04:55:30 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-d56faf11-3fb7-4829-8afd-af8871bf8a77 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475646106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3475646106 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.4163858748 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 85498190 ps |
CPU time | 5.11 seconds |
Started | Jul 14 04:55:19 PM PDT 24 |
Finished | Jul 14 04:55:25 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-1636cca7-6567-484b-8548-37059ea00d6e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163858748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.4163858748 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3903749634 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 12981426742 ps |
CPU time | 822.9 seconds |
Started | Jul 14 04:55:15 PM PDT 24 |
Finished | Jul 14 05:08:59 PM PDT 24 |
Peak memory | 359328 kb |
Host | smart-a2792358-5a2b-4d5c-b655-d9c795bbb7ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903749634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3903749634 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.2876494442 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 904003923 ps |
CPU time | 13.32 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:55:28 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-f2032e01-f252-48fc-b279-fcf03d83a434 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876494442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.2876494442 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.575681991 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 171339971543 ps |
CPU time | 299.24 seconds |
Started | Jul 14 04:55:13 PM PDT 24 |
Finished | Jul 14 05:00:13 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-f48d25f4-5a06-43b1-b9ba-59302a6f8856 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575681991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.sram_ctrl_partial_access_b2b.575681991 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.3007639916 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 83144553 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:55:19 PM PDT 24 |
Finished | Jul 14 04:55:21 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-3f5e669e-b141-412c-aaf0-4723df60e590 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007639916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3007639916 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.761932626 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 7683579700 ps |
CPU time | 774.57 seconds |
Started | Jul 14 04:55:20 PM PDT 24 |
Finished | Jul 14 05:08:15 PM PDT 24 |
Peak memory | 367436 kb |
Host | smart-773e38b7-fb54-42ae-baa2-d59acc156c54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761932626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.761932626 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.1628026521 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 819124554 ps |
CPU time | 9.42 seconds |
Started | Jul 14 04:55:16 PM PDT 24 |
Finished | Jul 14 04:55:26 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-2816dcb6-f364-4957-b2c1-03a87c56b507 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628026521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1628026521 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.298504428 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 50289298837 ps |
CPU time | 931.32 seconds |
Started | Jul 14 04:55:19 PM PDT 24 |
Finished | Jul 14 05:10:51 PM PDT 24 |
Peak memory | 382796 kb |
Host | smart-c75e1b4e-a1dd-4206-b8a2-92d834c1cc12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298504428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.298504428 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.359037401 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 7057565915 ps |
CPU time | 592.57 seconds |
Started | Jul 14 04:55:23 PM PDT 24 |
Finished | Jul 14 05:05:16 PM PDT 24 |
Peak memory | 377856 kb |
Host | smart-1ce45ac4-3e49-4cd3-8f63-e54afff715a7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=359037401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.359037401 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2524801365 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 10660561833 ps |
CPU time | 264.31 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:59:39 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-dd0cf2f6-7ccf-4a3e-a760-f7be2693bc62 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524801365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2524801365 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2872744672 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 676392997 ps |
CPU time | 130.66 seconds |
Started | Jul 14 04:55:14 PM PDT 24 |
Finished | Jul 14 04:57:26 PM PDT 24 |
Peak memory | 362196 kb |
Host | smart-c14f536e-00eb-4978-ba90-8ff3683ecbb9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872744672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2872744672 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2569240242 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 4144134197 ps |
CPU time | 1355.53 seconds |
Started | Jul 14 04:55:26 PM PDT 24 |
Finished | Jul 14 05:18:02 PM PDT 24 |
Peak memory | 374592 kb |
Host | smart-d41c2d1a-f608-4cda-96cc-c1c9ae39a120 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569240242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2569240242 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.2428484390 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 13581388 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:55:33 PM PDT 24 |
Finished | Jul 14 04:55:34 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-7c3d07bd-b74a-4161-816b-3ed2993b65b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428484390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2428484390 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.1130479382 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 1787273136 ps |
CPU time | 31.09 seconds |
Started | Jul 14 04:55:27 PM PDT 24 |
Finished | Jul 14 04:55:58 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-9bd6a8ec-15e2-4449-9ffa-5d64902ade3f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130479382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .1130479382 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.3502330682 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 11223853786 ps |
CPU time | 524.08 seconds |
Started | Jul 14 04:55:25 PM PDT 24 |
Finished | Jul 14 05:04:10 PM PDT 24 |
Peak memory | 348204 kb |
Host | smart-7919861a-5454-4318-b8e6-a65cbae818a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502330682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.3502330682 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.803774948 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 872362329 ps |
CPU time | 6.79 seconds |
Started | Jul 14 04:55:27 PM PDT 24 |
Finished | Jul 14 04:55:34 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-cfaa01c5-c9df-4cbc-909d-f6b59b9c27e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803774948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc alation.803774948 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.1666233980 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 162670638 ps |
CPU time | 37.07 seconds |
Started | Jul 14 04:55:24 PM PDT 24 |
Finished | Jul 14 04:56:02 PM PDT 24 |
Peak memory | 279132 kb |
Host | smart-725e875b-6765-42bb-91ce-112d18d16872 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666233980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.1666233980 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.838227396 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 399659567 ps |
CPU time | 5.38 seconds |
Started | Jul 14 04:55:31 PM PDT 24 |
Finished | Jul 14 04:55:37 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-00ea0c05-ca55-4c7d-81fc-520d56acd899 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838227396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.838227396 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.3418204738 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 96673305 ps |
CPU time | 5.28 seconds |
Started | Jul 14 04:55:27 PM PDT 24 |
Finished | Jul 14 04:55:33 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-f3ad3194-ea75-4999-838f-17cdc2dc0a05 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418204738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3418204738 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.1296486904 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 7173605124 ps |
CPU time | 1647.14 seconds |
Started | Jul 14 04:55:24 PM PDT 24 |
Finished | Jul 14 05:22:52 PM PDT 24 |
Peak memory | 375176 kb |
Host | smart-0502dcd4-c2b4-43ed-bcdb-33b6a6a41703 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296486904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.1296486904 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.918600989 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 868114574 ps |
CPU time | 6.11 seconds |
Started | Jul 14 04:55:26 PM PDT 24 |
Finished | Jul 14 04:55:33 PM PDT 24 |
Peak memory | 219684 kb |
Host | smart-24a3783d-f33b-4615-8f0e-44010b2ec4c2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918600989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.918600989 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.85737317 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 5693824811 ps |
CPU time | 418.41 seconds |
Started | Jul 14 04:55:27 PM PDT 24 |
Finished | Jul 14 05:02:26 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-3cbe4d6a-6208-467a-848f-c18106d75b69 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85737317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_partial_access_b2b.85737317 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.3481640694 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 42241902 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:55:26 PM PDT 24 |
Finished | Jul 14 04:55:27 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-78a3253d-aa6c-4936-9615-395c1053494f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481640694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3481640694 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.1374353493 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 103529057789 ps |
CPU time | 891.42 seconds |
Started | Jul 14 04:55:27 PM PDT 24 |
Finished | Jul 14 05:10:19 PM PDT 24 |
Peak memory | 374656 kb |
Host | smart-e88af4ac-0fa7-4ac9-ba7d-f42a1e8d10a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374353493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1374353493 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.4042000725 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 136175952 ps |
CPU time | 158.61 seconds |
Started | Jul 14 04:55:20 PM PDT 24 |
Finished | Jul 14 04:57:59 PM PDT 24 |
Peak memory | 368344 kb |
Host | smart-dfb14d5f-adf4-47d3-93a4-f9a3d0e06c91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042000725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.4042000725 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.381751247 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 19103243510 ps |
CPU time | 2021.6 seconds |
Started | Jul 14 04:55:33 PM PDT 24 |
Finished | Jul 14 05:29:16 PM PDT 24 |
Peak memory | 373624 kb |
Host | smart-cc1e22c7-e457-4387-882a-ae86daf7c209 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381751247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_stress_all.381751247 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.770851790 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 2988552018 ps |
CPU time | 603.69 seconds |
Started | Jul 14 04:55:32 PM PDT 24 |
Finished | Jul 14 05:05:37 PM PDT 24 |
Peak memory | 368652 kb |
Host | smart-a9b16a77-af58-4f7f-8e79-0071db5db45f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=770851790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.770851790 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2935027861 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 8226021041 ps |
CPU time | 206.22 seconds |
Started | Jul 14 04:55:25 PM PDT 24 |
Finished | Jul 14 04:58:51 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-1a1f1463-665d-4d7f-8a2c-662dfc24dfe6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935027861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2935027861 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2080605256 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 250797273 ps |
CPU time | 151.83 seconds |
Started | Jul 14 04:55:27 PM PDT 24 |
Finished | Jul 14 04:58:00 PM PDT 24 |
Peak memory | 363252 kb |
Host | smart-fa983ebf-818e-43e9-9b31-d3b2cf8270f4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080605256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2080605256 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.637192862 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 14460958731 ps |
CPU time | 1276.03 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 05:16:54 PM PDT 24 |
Peak memory | 375684 kb |
Host | smart-663dd366-0612-4f58-a060-f92a6b6280c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637192862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.637192862 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.35428478 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 34494136 ps |
CPU time | 0.68 seconds |
Started | Jul 14 04:55:39 PM PDT 24 |
Finished | Jul 14 04:55:41 PM PDT 24 |
Peak memory | 202164 kb |
Host | smart-d55517f1-0879-4679-821b-1a91724e1bd9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_alert_test.35428478 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.3402081110 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 4178640418 ps |
CPU time | 74.39 seconds |
Started | Jul 14 04:55:32 PM PDT 24 |
Finished | Jul 14 04:56:47 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-0539bc47-b141-4c5e-a42a-242f4835d526 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402081110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3402081110 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.2391572900 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 68043516745 ps |
CPU time | 1538.91 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 05:21:19 PM PDT 24 |
Peak memory | 373660 kb |
Host | smart-93e43f6c-d8b5-4c86-a5e6-201808b9388b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391572900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.2391572900 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.3402156785 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 4320455663 ps |
CPU time | 5.88 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 04:55:46 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-26dd3cca-2714-4a13-9604-1eee131e17d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402156785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.3402156785 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.2299240145 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 154188156 ps |
CPU time | 29.05 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 04:56:08 PM PDT 24 |
Peak memory | 278292 kb |
Host | smart-6e40e1d4-9fd4-46b4-9dea-c53b3ee8be3e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299240145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.2299240145 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2061838572 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 105953267 ps |
CPU time | 3.43 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 04:55:43 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-3f824b0a-583f-49b3-85cc-3473a1bcd272 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061838572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.2061838572 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.3096592842 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 1838139865 ps |
CPU time | 11.31 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 04:55:50 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-745d42c7-c2ec-4295-9083-95bf4162e45e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096592842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.3096592842 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.3906553966 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 2922038764 ps |
CPU time | 493.33 seconds |
Started | Jul 14 04:55:34 PM PDT 24 |
Finished | Jul 14 05:03:48 PM PDT 24 |
Peak memory | 365904 kb |
Host | smart-febbbde5-cc8d-4595-b4f9-a9764ff8f98d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906553966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3906553966 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.335428109 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 2552753857 ps |
CPU time | 114.74 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 04:57:33 PM PDT 24 |
Peak memory | 345348 kb |
Host | smart-5e21c469-ffd8-45aa-85e5-efadc7baf6a2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335428109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.335428109 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.833730331 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 15554336066 ps |
CPU time | 456.56 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 05:03:16 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-bebc6aec-e291-406e-a12d-7dc1b19306c2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833730331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.sram_ctrl_partial_access_b2b.833730331 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.1176727975 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 57358786 ps |
CPU time | 0.87 seconds |
Started | Jul 14 04:55:39 PM PDT 24 |
Finished | Jul 14 04:55:41 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-230026b9-8281-42f5-9060-adfefa75c83a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176727975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1176727975 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.631114821 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1807025573 ps |
CPU time | 544.94 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 05:04:45 PM PDT 24 |
Peak memory | 365556 kb |
Host | smart-45f9814f-a2a0-4817-b660-e1992b5fb98d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631114821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.631114821 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.2205338918 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 261361048 ps |
CPU time | 5.06 seconds |
Started | Jul 14 04:55:33 PM PDT 24 |
Finished | Jul 14 04:55:39 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-ae36cfbc-d42f-4a37-9e8f-3abc0b5c44ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205338918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2205338918 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.1345035529 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 146694827359 ps |
CPU time | 1711.53 seconds |
Started | Jul 14 04:55:39 PM PDT 24 |
Finished | Jul 14 05:24:12 PM PDT 24 |
Peak memory | 375160 kb |
Host | smart-05f62b59-17f8-4b93-b7c6-04d661645fbe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345035529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.1345035529 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2440680933 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 13718114990 ps |
CPU time | 45.96 seconds |
Started | Jul 14 04:55:38 PM PDT 24 |
Finished | Jul 14 04:56:26 PM PDT 24 |
Peak memory | 271892 kb |
Host | smart-fb639e26-3800-458f-8773-c185a1bc2eb2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2440680933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2440680933 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3846873867 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 8492524551 ps |
CPU time | 205.32 seconds |
Started | Jul 14 04:55:33 PM PDT 24 |
Finished | Jul 14 04:58:59 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-55cdc193-c34c-430a-a254-8bccface97ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846873867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3846873867 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.870748741 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 143740623 ps |
CPU time | 101.12 seconds |
Started | Jul 14 04:55:39 PM PDT 24 |
Finished | Jul 14 04:57:21 PM PDT 24 |
Peak memory | 340788 kb |
Host | smart-3532b58c-9963-4e4a-ba7b-884eb7550480 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870748741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.870748741 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1414998270 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 14487383118 ps |
CPU time | 615.36 seconds |
Started | Jul 14 04:55:45 PM PDT 24 |
Finished | Jul 14 05:06:01 PM PDT 24 |
Peak memory | 374588 kb |
Host | smart-6083f029-3245-43c0-8b01-567b8d8a29c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414998270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.1414998270 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.1430349229 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 45068558 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:55:51 PM PDT 24 |
Finished | Jul 14 04:55:52 PM PDT 24 |
Peak memory | 202552 kb |
Host | smart-38942a97-5ded-4e60-879e-488b98d312b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430349229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1430349229 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.1526722472 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 1812349279 ps |
CPU time | 30.21 seconds |
Started | Jul 14 04:55:43 PM PDT 24 |
Finished | Jul 14 04:56:14 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-abdeec2b-85a1-4099-a6d6-ca6430cf5e40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526722472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1526722472 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.471833948 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 5234452248 ps |
CPU time | 333.63 seconds |
Started | Jul 14 04:55:46 PM PDT 24 |
Finished | Jul 14 05:01:20 PM PDT 24 |
Peak memory | 374404 kb |
Host | smart-628fb42f-04d4-4259-a26a-35fee20e91a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471833948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.471833948 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.3760326803 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 814437235 ps |
CPU time | 4.48 seconds |
Started | Jul 14 04:55:45 PM PDT 24 |
Finished | Jul 14 04:55:50 PM PDT 24 |
Peak memory | 210912 kb |
Host | smart-b9dbc727-a853-484e-b580-3580cf7c9d9a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760326803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.3760326803 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.1675409123 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1925781769 ps |
CPU time | 69.81 seconds |
Started | Jul 14 04:55:44 PM PDT 24 |
Finished | Jul 14 04:56:55 PM PDT 24 |
Peak memory | 313640 kb |
Host | smart-2d0f8578-1d73-479c-8211-b94e8cdceaa1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675409123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1675409123 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3259749777 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 451789570 ps |
CPU time | 5.97 seconds |
Started | Jul 14 04:55:50 PM PDT 24 |
Finished | Jul 14 04:55:56 PM PDT 24 |
Peak memory | 210892 kb |
Host | smart-53f512d8-2892-48d7-a9d8-2c6b7b8d91c2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259749777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3259749777 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.2918937348 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 5049558018 ps |
CPU time | 11.66 seconds |
Started | Jul 14 04:55:44 PM PDT 24 |
Finished | Jul 14 04:55:57 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-2e48d3d0-e3ca-4cf9-8b15-1659dbf040a1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918937348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.2918937348 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.1035745676 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 13161110158 ps |
CPU time | 1385.39 seconds |
Started | Jul 14 04:55:41 PM PDT 24 |
Finished | Jul 14 05:18:47 PM PDT 24 |
Peak memory | 374540 kb |
Host | smart-ace4e200-1d26-4b63-bef8-b9a1135e2cdd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035745676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1035745676 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.4110922330 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 149538028 ps |
CPU time | 2.13 seconds |
Started | Jul 14 04:55:43 PM PDT 24 |
Finished | Jul 14 04:55:46 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-d30533b6-0e90-4e18-a6b3-1971259fd24d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110922330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.4110922330 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.20110442 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 33186586823 ps |
CPU time | 454.55 seconds |
Started | Jul 14 04:55:44 PM PDT 24 |
Finished | Jul 14 05:03:19 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-189df83b-b7de-43a1-858b-d3d3df786c27 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20110442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_partial_access_b2b.20110442 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.3946108206 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 85587531 ps |
CPU time | 0.79 seconds |
Started | Jul 14 04:55:44 PM PDT 24 |
Finished | Jul 14 04:55:46 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-aedf0e39-69f3-447f-9242-35dc646f6da4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946108206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3946108206 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.2135185977 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 6339327433 ps |
CPU time | 429.32 seconds |
Started | Jul 14 04:55:43 PM PDT 24 |
Finished | Jul 14 05:02:54 PM PDT 24 |
Peak memory | 374768 kb |
Host | smart-9618104e-63ac-49ee-bc34-452d382b003e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135185977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2135185977 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.896331100 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 7840894875 ps |
CPU time | 65.43 seconds |
Started | Jul 14 04:55:39 PM PDT 24 |
Finished | Jul 14 04:56:46 PM PDT 24 |
Peak memory | 300208 kb |
Host | smart-169e71b2-557e-4244-af3a-1d47eda460db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896331100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.896331100 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.3579560036 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 84459517538 ps |
CPU time | 4802.29 seconds |
Started | Jul 14 04:55:49 PM PDT 24 |
Finished | Jul 14 06:15:53 PM PDT 24 |
Peak memory | 382888 kb |
Host | smart-982310d5-4c4b-45c9-aeb2-388216ac5704 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579560036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.3579560036 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3538154854 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 10649494078 ps |
CPU time | 266.54 seconds |
Started | Jul 14 04:55:44 PM PDT 24 |
Finished | Jul 14 05:00:12 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-0b010abc-fb38-4cb4-9b98-ab143af3f6ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538154854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3538154854 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3692823479 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 94497065 ps |
CPU time | 23.33 seconds |
Started | Jul 14 04:55:45 PM PDT 24 |
Finished | Jul 14 04:56:09 PM PDT 24 |
Peak memory | 273276 kb |
Host | smart-97a9cf15-11ca-4c67-b228-44858fa703a1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692823479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3692823479 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1088460810 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 3300889599 ps |
CPU time | 1381.42 seconds |
Started | Jul 14 04:55:56 PM PDT 24 |
Finished | Jul 14 05:18:59 PM PDT 24 |
Peak memory | 374592 kb |
Host | smart-679c7ca5-d117-4229-98d5-bcb980ab0203 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088460810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1088460810 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.2305172973 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 74857508 ps |
CPU time | 0.64 seconds |
Started | Jul 14 04:55:56 PM PDT 24 |
Finished | Jul 14 04:55:57 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-aa3ff6e0-698c-4032-b4b3-7a20cce9cf43 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305172973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2305172973 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2830733125 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 5176361922 ps |
CPU time | 79.57 seconds |
Started | Jul 14 04:55:50 PM PDT 24 |
Finished | Jul 14 04:57:10 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-1d68acfe-82cb-415f-9baf-689c5257a419 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830733125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2830733125 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.2850464231 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 165901672487 ps |
CPU time | 1830.45 seconds |
Started | Jul 14 04:55:59 PM PDT 24 |
Finished | Jul 14 05:26:30 PM PDT 24 |
Peak memory | 375024 kb |
Host | smart-0faf58bb-9083-4115-b004-d5710b7e391d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850464231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2850464231 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.1659929230 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 2961548561 ps |
CPU time | 9.22 seconds |
Started | Jul 14 04:55:57 PM PDT 24 |
Finished | Jul 14 04:56:07 PM PDT 24 |
Peak memory | 214920 kb |
Host | smart-22b356dd-e551-4449-9ff4-958844d72148 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659929230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.1659929230 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.2312727698 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 350540472 ps |
CPU time | 53.6 seconds |
Started | Jul 14 04:55:49 PM PDT 24 |
Finished | Jul 14 04:56:43 PM PDT 24 |
Peak memory | 292968 kb |
Host | smart-a76446b3-ab8e-418d-9ff5-66a153ff59d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312727698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.2312727698 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1406655418 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 68081387 ps |
CPU time | 4.48 seconds |
Started | Jul 14 04:55:56 PM PDT 24 |
Finished | Jul 14 04:56:01 PM PDT 24 |
Peak memory | 210904 kb |
Host | smart-2686f4d9-d7c1-4462-aaf6-7e9bc4cb2491 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406655418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1406655418 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.14504769 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 685140968 ps |
CPU time | 10.71 seconds |
Started | Jul 14 04:55:57 PM PDT 24 |
Finished | Jul 14 04:56:08 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-5f030fef-0e2d-4616-b7b5-d1e7cbf3a5f2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14504769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ mem_walk.14504769 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.1749536577 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 6652399297 ps |
CPU time | 1000.08 seconds |
Started | Jul 14 04:55:51 PM PDT 24 |
Finished | Jul 14 05:12:31 PM PDT 24 |
Peak memory | 372568 kb |
Host | smart-41d06410-9e2f-4304-ba56-35fccb421033 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749536577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.1749536577 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.234135037 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 375763845 ps |
CPU time | 3.2 seconds |
Started | Jul 14 04:55:50 PM PDT 24 |
Finished | Jul 14 04:55:54 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-1d4b0eb9-b723-4c79-9d8d-cfeb54cb6a5f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234135037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s ram_ctrl_partial_access.234135037 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1857439773 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 38465892473 ps |
CPU time | 268.89 seconds |
Started | Jul 14 04:55:49 PM PDT 24 |
Finished | Jul 14 05:00:18 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-89da4e27-52c6-4b34-84c6-2572c91cabae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857439773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.1857439773 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.4055319794 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 45990414 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:55:56 PM PDT 24 |
Finished | Jul 14 04:55:57 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-b78563e6-1b64-41b2-95f0-215e902cb213 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055319794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4055319794 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.2341140981 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 49280059594 ps |
CPU time | 1886.96 seconds |
Started | Jul 14 04:56:00 PM PDT 24 |
Finished | Jul 14 05:27:27 PM PDT 24 |
Peak memory | 375412 kb |
Host | smart-d382892e-acf0-4f57-b659-5f640c825a19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341140981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2341140981 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.3853982318 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 366625874 ps |
CPU time | 5.25 seconds |
Started | Jul 14 04:55:50 PM PDT 24 |
Finished | Jul 14 04:55:56 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-e1d80c56-e561-4424-a683-30c50e5dd452 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853982318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3853982318 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.1814415807 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 51888135541 ps |
CPU time | 2246.44 seconds |
Started | Jul 14 04:55:56 PM PDT 24 |
Finished | Jul 14 05:33:23 PM PDT 24 |
Peak memory | 374692 kb |
Host | smart-0e6afd32-d30a-458a-b64b-711fd2a9c72f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814415807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1814415807 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.845797025 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 1588145287 ps |
CPU time | 3.86 seconds |
Started | Jul 14 04:55:59 PM PDT 24 |
Finished | Jul 14 04:56:03 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-86bc8abc-940a-4a91-aeba-515c052a228b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=845797025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.845797025 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.4206706178 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 1993584972 ps |
CPU time | 174.48 seconds |
Started | Jul 14 04:55:50 PM PDT 24 |
Finished | Jul 14 04:58:45 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-b3820e75-e923-4c1e-a288-c262ebc4beac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206706178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.4206706178 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2276128988 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 284127548 ps |
CPU time | 21.94 seconds |
Started | Jul 14 04:55:50 PM PDT 24 |
Finished | Jul 14 04:56:13 PM PDT 24 |
Peak memory | 290640 kb |
Host | smart-e2c44b4b-a7f2-4d8e-af37-deddd5f09c84 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276128988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2276128988 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.620560884 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 16318903749 ps |
CPU time | 757.27 seconds |
Started | Jul 14 04:56:01 PM PDT 24 |
Finished | Jul 14 05:08:39 PM PDT 24 |
Peak memory | 351008 kb |
Host | smart-d8883f59-e750-4b0f-9cdd-71cedbe24001 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620560884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.620560884 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.4263741801 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 15010560 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:56:06 PM PDT 24 |
Finished | Jul 14 04:56:07 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-5fcb3876-4374-4e1e-9577-811709aeccb5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263741801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.4263741801 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.936770835 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 6782978660 ps |
CPU time | 53.89 seconds |
Started | Jul 14 04:56:03 PM PDT 24 |
Finished | Jul 14 04:56:58 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-1cae06e4-eea7-48c0-b629-809f5fa899d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936770835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection. 936770835 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.1908041234 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 6472687540 ps |
CPU time | 638.24 seconds |
Started | Jul 14 04:56:06 PM PDT 24 |
Finished | Jul 14 05:06:45 PM PDT 24 |
Peak memory | 374728 kb |
Host | smart-baa590d9-9b7f-44fd-a682-83468eeafd45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908041234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.1908041234 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.3817240711 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 981967196 ps |
CPU time | 5.8 seconds |
Started | Jul 14 04:56:01 PM PDT 24 |
Finished | Jul 14 04:56:07 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-0de81859-0679-4593-9e3a-9d7ddbf9a40a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817240711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.3817240711 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.2361643236 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 229512737 ps |
CPU time | 33.49 seconds |
Started | Jul 14 04:56:01 PM PDT 24 |
Finished | Jul 14 04:56:35 PM PDT 24 |
Peak memory | 285480 kb |
Host | smart-d6d156cc-238d-40d1-a367-c5b1e086e216 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361643236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.2361643236 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2371820437 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 811899896 ps |
CPU time | 5.54 seconds |
Started | Jul 14 04:56:07 PM PDT 24 |
Finished | Jul 14 04:56:14 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-18f24c9e-8236-4dd6-baef-ce8afa6e340b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371820437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2371820437 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.4213561392 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 910373421 ps |
CPU time | 5.9 seconds |
Started | Jul 14 04:56:06 PM PDT 24 |
Finished | Jul 14 04:56:12 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-17732985-95b0-4ffd-a1d4-cfa3d87fa924 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213561392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.4213561392 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.344956315 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 3146263986 ps |
CPU time | 141.68 seconds |
Started | Jul 14 04:56:03 PM PDT 24 |
Finished | Jul 14 04:58:25 PM PDT 24 |
Peak memory | 297152 kb |
Host | smart-a467cb02-0193-442f-bb5c-49bfb4d7a5bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344956315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip le_keys.344956315 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.893946011 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 309903641 ps |
CPU time | 6.92 seconds |
Started | Jul 14 04:56:03 PM PDT 24 |
Finished | Jul 14 04:56:11 PM PDT 24 |
Peak memory | 225764 kb |
Host | smart-b4961b31-0cef-4852-8409-bdcf9f238b84 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893946011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s ram_ctrl_partial_access.893946011 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.4198008593 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 26163622255 ps |
CPU time | 685.43 seconds |
Started | Jul 14 04:56:02 PM PDT 24 |
Finished | Jul 14 05:07:28 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-dd75cc9e-f2ef-4ca9-a994-ed4409764d1f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198008593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.4198008593 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.2966863835 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 54256121 ps |
CPU time | 0.79 seconds |
Started | Jul 14 04:56:06 PM PDT 24 |
Finished | Jul 14 04:56:08 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-f0fe7ff3-2815-4937-a0e0-32a0fda4077a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966863835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2966863835 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.206593495 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 5283686618 ps |
CPU time | 39.64 seconds |
Started | Jul 14 04:56:07 PM PDT 24 |
Finished | Jul 14 04:56:48 PM PDT 24 |
Peak memory | 270288 kb |
Host | smart-5ab28f47-9885-4790-a990-43e9e17e903a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206593495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.206593495 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.2486293126 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 354989850 ps |
CPU time | 7.64 seconds |
Started | Jul 14 04:55:55 PM PDT 24 |
Finished | Jul 14 04:56:03 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-37b9d3c9-6f4d-4ef3-869b-01253bb237bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486293126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2486293126 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.3806479931 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 121690834155 ps |
CPU time | 3101.32 seconds |
Started | Jul 14 04:56:07 PM PDT 24 |
Finished | Jul 14 05:47:49 PM PDT 24 |
Peak memory | 383532 kb |
Host | smart-fee0462b-b0db-424c-ac28-6851bf99b50e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806479931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.3806479931 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2888638481 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1744536209 ps |
CPU time | 202.21 seconds |
Started | Jul 14 04:56:07 PM PDT 24 |
Finished | Jul 14 04:59:29 PM PDT 24 |
Peak memory | 342092 kb |
Host | smart-536e66dc-a413-48b8-a957-7a95080a895b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2888638481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2888638481 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2209960416 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 31791296289 ps |
CPU time | 198.71 seconds |
Started | Jul 14 04:56:02 PM PDT 24 |
Finished | Jul 14 04:59:21 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-cb5a01b6-81dc-41e4-8ccb-bac94f5a584d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209960416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.2209960416 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2584965787 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 115654648 ps |
CPU time | 76.96 seconds |
Started | Jul 14 04:56:04 PM PDT 24 |
Finished | Jul 14 04:57:21 PM PDT 24 |
Peak memory | 312492 kb |
Host | smart-37a4407e-ae3f-42d8-96dd-6d2dee61add5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584965787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2584965787 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.398387789 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 13870037 ps |
CPU time | 0.72 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 04:54:02 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-c5a43baa-e89d-46fc-94e0-fec548739231 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398387789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.398387789 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.3144276754 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 5515506658 ps |
CPU time | 64.58 seconds |
Started | Jul 14 04:53:55 PM PDT 24 |
Finished | Jul 14 04:55:00 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-0694f2a7-7590-42a8-8639-6b2d7af3e804 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144276754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 3144276754 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.2509822913 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 5435859851 ps |
CPU time | 913.25 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 05:09:15 PM PDT 24 |
Peak memory | 368496 kb |
Host | smart-4b62ffc8-84a8-4e87-ad5f-f782421be549 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509822913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.2509822913 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.2317063168 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 1461083513 ps |
CPU time | 7.91 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 04:54:09 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-64dbf493-f7bd-4664-905a-59635dbb5585 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317063168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2317063168 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.1992272444 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 1159805581 ps |
CPU time | 149.18 seconds |
Started | Jul 14 04:53:57 PM PDT 24 |
Finished | Jul 14 04:56:27 PM PDT 24 |
Peak memory | 368280 kb |
Host | smart-8d81f462-e4f0-4dea-a32b-b7dcddc721f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992272444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.1992272444 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3508731870 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 653122448 ps |
CPU time | 5.93 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 04:54:07 PM PDT 24 |
Peak memory | 210900 kb |
Host | smart-c490afd0-0cfa-4607-8c7a-ee92059551a1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508731870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.3508731870 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2807825530 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 282894260 ps |
CPU time | 4.62 seconds |
Started | Jul 14 04:54:03 PM PDT 24 |
Finished | Jul 14 04:54:08 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-bd3d3eb7-d5d1-4a4a-a159-ea2b1707261d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807825530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2807825530 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.3468869763 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 23548307419 ps |
CPU time | 1619.61 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 05:20:54 PM PDT 24 |
Peak memory | 374504 kb |
Host | smart-8eb0477e-c175-4f62-9295-ca20b40ff915 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468869763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3468869763 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.3538895030 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 221691991 ps |
CPU time | 134.03 seconds |
Started | Jul 14 04:53:56 PM PDT 24 |
Finished | Jul 14 04:56:10 PM PDT 24 |
Peak memory | 358840 kb |
Host | smart-acafb77d-5188-430e-afd2-289f92373c5d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538895030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.3538895030 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2118219665 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 53231371372 ps |
CPU time | 673.26 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 05:05:07 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-4308313c-39df-4ac7-8171-366e7bfbaa11 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118219665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.2118219665 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.4225413337 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 93367871 ps |
CPU time | 0.83 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 04:54:03 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-2ce2cf40-a574-4353-a11f-606893b43758 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225413337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.4225413337 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.46152591 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1875545055 ps |
CPU time | 498.62 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 05:02:21 PM PDT 24 |
Peak memory | 366396 kb |
Host | smart-1b996912-1b83-4a9d-abd9-9b2d844df279 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46152591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.46152591 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.2911486343 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 199883615 ps |
CPU time | 2.24 seconds |
Started | Jul 14 04:54:02 PM PDT 24 |
Finished | Jul 14 04:54:05 PM PDT 24 |
Peak memory | 221904 kb |
Host | smart-ce93edea-8e3c-4831-8372-6ed9647930a3 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911486343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2911486343 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.2925108499 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 97797495 ps |
CPU time | 5.55 seconds |
Started | Jul 14 04:53:53 PM PDT 24 |
Finished | Jul 14 04:53:59 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-b5817814-f5f0-43d0-9505-8dd065f5d29d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925108499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2925108499 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.3590060317 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 126166745390 ps |
CPU time | 1252.41 seconds |
Started | Jul 14 04:54:02 PM PDT 24 |
Finished | Jul 14 05:14:55 PM PDT 24 |
Peak memory | 376688 kb |
Host | smart-02648aad-9367-4030-9efc-2bbffc09ad1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590060317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.3590060317 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.173114919 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 3335934581 ps |
CPU time | 625.65 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 05:04:27 PM PDT 24 |
Peak memory | 380680 kb |
Host | smart-d92cbe3f-fdd4-47aa-8422-5dca3dbff165 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=173114919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.173114919 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2355297639 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 36298612329 ps |
CPU time | 352.61 seconds |
Started | Jul 14 04:53:55 PM PDT 24 |
Finished | Jul 14 04:59:49 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-39191974-84d4-464b-b3fe-2de800b0d0a8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355297639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.2355297639 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.958652426 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 46286016 ps |
CPU time | 1.24 seconds |
Started | Jul 14 04:53:54 PM PDT 24 |
Finished | Jul 14 04:53:56 PM PDT 24 |
Peak memory | 210784 kb |
Host | smart-53949d19-2f3f-4557-8c51-23d016eed807 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958652426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.958652426 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3284577740 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 4377808037 ps |
CPU time | 1900.22 seconds |
Started | Jul 14 04:56:13 PM PDT 24 |
Finished | Jul 14 05:27:54 PM PDT 24 |
Peak memory | 373976 kb |
Host | smart-534e5975-74a2-494c-89e8-078b19dffaab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284577740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.3284577740 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.389780376 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 22027879 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:56:20 PM PDT 24 |
Finished | Jul 14 04:56:21 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-b3a7d809-932c-415d-8b85-dfe1299fa2b2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389780376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.389780376 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.695652021 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 10360839007 ps |
CPU time | 46.1 seconds |
Started | Jul 14 04:56:14 PM PDT 24 |
Finished | Jul 14 04:57:00 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-a0bd2096-242a-42b3-a444-71168c4a279e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695652021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection. 695652021 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.7007217 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 16622810831 ps |
CPU time | 708.84 seconds |
Started | Jul 14 04:56:12 PM PDT 24 |
Finished | Jul 14 05:08:02 PM PDT 24 |
Peak memory | 373568 kb |
Host | smart-77e49aa5-1d4d-4185-922c-6d09c812d544 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7007217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.7007217 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.3916609783 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 456875161 ps |
CPU time | 3.09 seconds |
Started | Jul 14 04:56:17 PM PDT 24 |
Finished | Jul 14 04:56:20 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-bbcdd8ef-e334-4c56-a449-544e0bb633c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916609783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.3916609783 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.3231769109 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 106801009 ps |
CPU time | 70.5 seconds |
Started | Jul 14 04:56:15 PM PDT 24 |
Finished | Jul 14 04:57:26 PM PDT 24 |
Peak memory | 324364 kb |
Host | smart-3131a578-26d3-4e13-913d-50ab3bfe4c15 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231769109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.3231769109 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2840698489 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 95997666 ps |
CPU time | 3.31 seconds |
Started | Jul 14 04:56:19 PM PDT 24 |
Finished | Jul 14 04:56:22 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-58890fd0-8323-4af0-83e1-b592c38f2181 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840698489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2840698489 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3336577305 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 541532042 ps |
CPU time | 9.03 seconds |
Started | Jul 14 04:56:22 PM PDT 24 |
Finished | Jul 14 04:56:31 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-2740059c-9a71-4e6d-be10-aeef56392a81 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336577305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3336577305 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.2656855022 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 5130602956 ps |
CPU time | 833.81 seconds |
Started | Jul 14 04:56:13 PM PDT 24 |
Finished | Jul 14 05:10:08 PM PDT 24 |
Peak memory | 375612 kb |
Host | smart-9f4b4ef6-85c1-4d7c-8111-746065ffcb6f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656855022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.2656855022 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.3959740542 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 199994572 ps |
CPU time | 1.96 seconds |
Started | Jul 14 04:56:15 PM PDT 24 |
Finished | Jul 14 04:56:17 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-a481f779-643f-426a-bb23-da25f6a592e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959740542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3959740542 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2999830058 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 43827072809 ps |
CPU time | 494.84 seconds |
Started | Jul 14 04:56:16 PM PDT 24 |
Finished | Jul 14 05:04:31 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-e40c9cad-825d-4983-ae82-61f60d851276 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999830058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2999830058 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.798598129 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 66129841 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:56:19 PM PDT 24 |
Finished | Jul 14 04:56:20 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-2f794cd3-52a0-4709-8076-8ace753eae44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798598129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.798598129 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.3353174637 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 56796471247 ps |
CPU time | 1365.82 seconds |
Started | Jul 14 04:56:14 PM PDT 24 |
Finished | Jul 14 05:19:00 PM PDT 24 |
Peak memory | 369252 kb |
Host | smart-d3975871-e509-40a3-b651-3d3d9b139714 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353174637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3353174637 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.1075827067 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 541024017 ps |
CPU time | 150 seconds |
Started | Jul 14 04:56:07 PM PDT 24 |
Finished | Jul 14 04:58:38 PM PDT 24 |
Peak memory | 369764 kb |
Host | smart-a99a3b42-ac23-4c34-a5da-8a8d784052dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075827067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1075827067 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.4053064426 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 17605033206 ps |
CPU time | 2105.12 seconds |
Started | Jul 14 04:56:20 PM PDT 24 |
Finished | Jul 14 05:31:26 PM PDT 24 |
Peak memory | 371492 kb |
Host | smart-a2c7251a-f926-4e46-bca0-60fede7d2af9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053064426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.4053064426 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1357519054 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 1099912243 ps |
CPU time | 34.49 seconds |
Started | Jul 14 04:56:21 PM PDT 24 |
Finished | Jul 14 04:56:56 PM PDT 24 |
Peak memory | 212276 kb |
Host | smart-34636cb4-c449-40a4-8468-65d1c9ad5dbe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1357519054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1357519054 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1268415355 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 3211258292 ps |
CPU time | 301.4 seconds |
Started | Jul 14 04:56:14 PM PDT 24 |
Finished | Jul 14 05:01:16 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-b7ff5b4b-9828-494d-a3f0-02fed5d06e48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268415355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1268415355 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3720041707 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 410263073 ps |
CPU time | 2.64 seconds |
Started | Jul 14 04:56:17 PM PDT 24 |
Finished | Jul 14 04:56:20 PM PDT 24 |
Peak memory | 218672 kb |
Host | smart-498ea78e-cf82-4ddb-9593-bcb28d317cd2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720041707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3720041707 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1311764919 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 56433555846 ps |
CPU time | 1165.92 seconds |
Started | Jul 14 04:56:26 PM PDT 24 |
Finished | Jul 14 05:15:52 PM PDT 24 |
Peak memory | 372008 kb |
Host | smart-9aa417c1-c9da-4831-bc75-35184a1ee555 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311764919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.1311764919 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1207024674 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 17184964 ps |
CPU time | 0.63 seconds |
Started | Jul 14 04:56:30 PM PDT 24 |
Finished | Jul 14 04:56:31 PM PDT 24 |
Peak memory | 202452 kb |
Host | smart-e4a86338-ac90-4335-a659-23c307b79961 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207024674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1207024674 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.3344815041 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 1220233853 ps |
CPU time | 27.57 seconds |
Started | Jul 14 04:56:20 PM PDT 24 |
Finished | Jul 14 04:56:48 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-7406f9e1-f0ee-4036-b68d-0211b70c95db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344815041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .3344815041 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.3541933947 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 1700660010 ps |
CPU time | 35.04 seconds |
Started | Jul 14 04:56:25 PM PDT 24 |
Finished | Jul 14 04:57:00 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-9e493b3f-1e03-448a-b506-ff7296e47ddf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541933947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.3541933947 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.1690677659 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 490434090 ps |
CPU time | 6.79 seconds |
Started | Jul 14 04:56:26 PM PDT 24 |
Finished | Jul 14 04:56:33 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-925a8df2-9c1b-44d8-bfc4-9487e0cc87c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690677659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.1690677659 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.1731721653 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 109160968 ps |
CPU time | 85.8 seconds |
Started | Jul 14 04:56:25 PM PDT 24 |
Finished | Jul 14 04:57:51 PM PDT 24 |
Peak memory | 322340 kb |
Host | smart-b778045e-e4c4-44d2-ae5a-e1b3f7d5711e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731721653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1731721653 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.588485014 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 266387511 ps |
CPU time | 2.61 seconds |
Started | Jul 14 04:56:32 PM PDT 24 |
Finished | Jul 14 04:56:35 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-66dc4e89-661b-4903-b150-43fb4fdd077f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588485014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.588485014 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.3234845171 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 452558196 ps |
CPU time | 10.8 seconds |
Started | Jul 14 04:56:30 PM PDT 24 |
Finished | Jul 14 04:56:42 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-8d128598-979b-434c-ad3f-17eeecd8bd01 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234845171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.3234845171 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.3710849832 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 251443277106 ps |
CPU time | 1033.96 seconds |
Started | Jul 14 04:56:21 PM PDT 24 |
Finished | Jul 14 05:13:35 PM PDT 24 |
Peak memory | 366428 kb |
Host | smart-e703ff51-f1ef-4513-89e4-3e93beb66825 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710849832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.3710849832 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1232450734 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 324844455 ps |
CPU time | 16.72 seconds |
Started | Jul 14 04:56:25 PM PDT 24 |
Finished | Jul 14 04:56:43 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-8b1d6d6d-c698-4bf9-8840-9043566eccdd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232450734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1232450734 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.982827640 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 42929818305 ps |
CPU time | 271.81 seconds |
Started | Jul 14 04:56:24 PM PDT 24 |
Finished | Jul 14 05:00:56 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-fefbb1eb-ae57-4474-89a9-800065a7d1ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982827640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.sram_ctrl_partial_access_b2b.982827640 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.1942184435 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 46923209 ps |
CPU time | 0.74 seconds |
Started | Jul 14 04:56:29 PM PDT 24 |
Finished | Jul 14 04:56:30 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-b57c2c30-59de-4313-97c3-9eb8707d49b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942184435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1942184435 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.2407971518 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 15764242806 ps |
CPU time | 1017.77 seconds |
Started | Jul 14 04:56:31 PM PDT 24 |
Finished | Jul 14 05:13:29 PM PDT 24 |
Peak memory | 369284 kb |
Host | smart-20cd0918-dac4-4ac2-8efe-57787fcef52e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407971518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2407971518 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.1202104333 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 217030259 ps |
CPU time | 12.96 seconds |
Started | Jul 14 04:56:19 PM PDT 24 |
Finished | Jul 14 04:56:32 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-c23f3740-ddf8-418d-87b7-6f8089cf194f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202104333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1202104333 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.1260565024 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 36675204045 ps |
CPU time | 3266.62 seconds |
Started | Jul 14 04:56:32 PM PDT 24 |
Finished | Jul 14 05:50:59 PM PDT 24 |
Peak memory | 375560 kb |
Host | smart-f54b7895-817c-4931-9a6c-79a5d8efbf3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260565024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.1260565024 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3174500550 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 13995979945 ps |
CPU time | 527.92 seconds |
Started | Jul 14 04:56:31 PM PDT 24 |
Finished | Jul 14 05:05:19 PM PDT 24 |
Peak memory | 372800 kb |
Host | smart-5341871c-a721-406c-ba54-51f40b1fd236 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3174500550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3174500550 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.33527164 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 3101047810 ps |
CPU time | 238.13 seconds |
Started | Jul 14 04:56:24 PM PDT 24 |
Finished | Jul 14 05:00:22 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-61e6d851-88a5-4128-baf3-3bac4d444f45 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33527164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_stress_pipeline.33527164 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.604253342 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 1024723105 ps |
CPU time | 55.43 seconds |
Started | Jul 14 04:56:26 PM PDT 24 |
Finished | Jul 14 04:57:22 PM PDT 24 |
Peak memory | 318156 kb |
Host | smart-89c756a3-700c-43cc-9523-c26b3daf4c5f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604253342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.604253342 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1556461296 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 2377662040 ps |
CPU time | 301.57 seconds |
Started | Jul 14 04:56:43 PM PDT 24 |
Finished | Jul 14 05:01:45 PM PDT 24 |
Peak memory | 370236 kb |
Host | smart-dac04910-09fe-487f-b08b-5801f64d8161 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556461296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.1556461296 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.1955518843 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 80615005 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:56:43 PM PDT 24 |
Finished | Jul 14 04:56:44 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-d1d6eb0b-35cd-408d-8ed6-3ea56f4b4280 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955518843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1955518843 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.3896952467 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 650182895 ps |
CPU time | 39.06 seconds |
Started | Jul 14 04:56:37 PM PDT 24 |
Finished | Jul 14 04:57:17 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-e3eb2d3f-ad7d-43f3-a91f-3e5f792a472c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896952467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .3896952467 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.2229132023 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 90109584475 ps |
CPU time | 930.09 seconds |
Started | Jul 14 04:56:46 PM PDT 24 |
Finished | Jul 14 05:12:16 PM PDT 24 |
Peak memory | 365528 kb |
Host | smart-cb3b1f45-6c98-4b10-93fd-66b7568c3886 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229132023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.2229132023 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.379971596 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 815655478 ps |
CPU time | 5.17 seconds |
Started | Jul 14 04:56:39 PM PDT 24 |
Finished | Jul 14 04:56:45 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-e3b48d6b-e568-4467-8d0a-48d9f617de0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379971596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc alation.379971596 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2659949162 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 66867073 ps |
CPU time | 11.19 seconds |
Started | Jul 14 04:56:38 PM PDT 24 |
Finished | Jul 14 04:56:49 PM PDT 24 |
Peak memory | 241364 kb |
Host | smart-d66246b7-6ffd-4740-b09e-e6f2b6deec95 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659949162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2659949162 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2486037572 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 240436593 ps |
CPU time | 5.36 seconds |
Started | Jul 14 04:56:43 PM PDT 24 |
Finished | Jul 14 04:56:48 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-5f76bc82-63c4-4728-9a2a-5122b707eae5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486037572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.2486037572 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.3339455196 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 177160752 ps |
CPU time | 10.75 seconds |
Started | Jul 14 04:56:44 PM PDT 24 |
Finished | Jul 14 04:56:55 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-fa20e2f8-521c-4802-879c-5d7d0d3f27f2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339455196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3339455196 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.3174807254 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 4470774775 ps |
CPU time | 416.12 seconds |
Started | Jul 14 04:56:39 PM PDT 24 |
Finished | Jul 14 05:03:36 PM PDT 24 |
Peak memory | 331784 kb |
Host | smart-b542da66-1c8e-4508-83b3-f9a7ced5e04f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174807254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3174807254 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.1036495357 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 801800615 ps |
CPU time | 137.87 seconds |
Started | Jul 14 04:56:39 PM PDT 24 |
Finished | Jul 14 04:58:57 PM PDT 24 |
Peak memory | 355968 kb |
Host | smart-a7c6c367-67ee-4db3-aa02-e30ac1b84e56 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036495357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.1036495357 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.561392317 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 3578976713 ps |
CPU time | 248.87 seconds |
Started | Jul 14 04:56:37 PM PDT 24 |
Finished | Jul 14 05:00:46 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-7f7a313e-e7e4-4a15-b59b-275335a5fcc2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561392317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.561392317 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.2971428620 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 30094122 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:56:44 PM PDT 24 |
Finished | Jul 14 04:56:45 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-6033bcca-4c65-4fc4-b961-adcadf5ee46e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971428620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2971428620 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.1947205370 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 53442929853 ps |
CPU time | 3241.51 seconds |
Started | Jul 14 04:56:47 PM PDT 24 |
Finished | Jul 14 05:50:49 PM PDT 24 |
Peak memory | 374712 kb |
Host | smart-7d36baea-8014-4b80-bdc4-53dc2d8c6f23 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947205370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1947205370 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2035938865 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 270576533 ps |
CPU time | 5.49 seconds |
Started | Jul 14 04:56:30 PM PDT 24 |
Finished | Jul 14 04:56:36 PM PDT 24 |
Peak memory | 223744 kb |
Host | smart-13a58cbf-e624-46b0-9ebc-208f4820276f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035938865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2035938865 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.2881354995 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 66996408539 ps |
CPU time | 2349.02 seconds |
Started | Jul 14 04:56:44 PM PDT 24 |
Finished | Jul 14 05:35:53 PM PDT 24 |
Peak memory | 374512 kb |
Host | smart-93c62996-c5a4-4197-b1dd-d60f00be9fdd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881354995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.2881354995 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2403203298 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 208670089 ps |
CPU time | 7.07 seconds |
Started | Jul 14 04:56:46 PM PDT 24 |
Finished | Jul 14 04:56:53 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-88ad6b4d-e21c-4afe-9dc1-0d58ba4c154c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2403203298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2403203298 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2730085944 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 2509249933 ps |
CPU time | 255.41 seconds |
Started | Jul 14 04:56:38 PM PDT 24 |
Finished | Jul 14 05:00:54 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-e30357ff-4ec1-46a0-81b4-ecf31a164f77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730085944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2730085944 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1855921017 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 161031049 ps |
CPU time | 178.95 seconds |
Started | Jul 14 04:56:39 PM PDT 24 |
Finished | Jul 14 04:59:38 PM PDT 24 |
Peak memory | 370020 kb |
Host | smart-f496c1d1-c243-4618-b29d-cfeb01f69859 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855921017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1855921017 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3499113242 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 3778709080 ps |
CPU time | 1245.09 seconds |
Started | Jul 14 04:56:49 PM PDT 24 |
Finished | Jul 14 05:17:35 PM PDT 24 |
Peak memory | 375696 kb |
Host | smart-d16f2a4d-1999-4ef4-ae3a-a8f8d28e3168 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499113242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.3499113242 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.2050893321 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 14125114 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:56:54 PM PDT 24 |
Finished | Jul 14 04:56:55 PM PDT 24 |
Peak memory | 202464 kb |
Host | smart-cd65be5a-f78b-49fd-a104-c72266dee039 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050893321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2050893321 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.302081486 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 19739103558 ps |
CPU time | 70.57 seconds |
Started | Jul 14 04:56:43 PM PDT 24 |
Finished | Jul 14 04:57:54 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-1d054278-2665-4831-a7c3-478d948fbafc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302081486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection. 302081486 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.1463498283 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 12379432851 ps |
CPU time | 772.85 seconds |
Started | Jul 14 04:56:48 PM PDT 24 |
Finished | Jul 14 05:09:41 PM PDT 24 |
Peak memory | 373576 kb |
Host | smart-f40ea7f6-fb00-44a3-ab87-e4b2ca59dcb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463498283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1463498283 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.2892697148 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 2589435869 ps |
CPU time | 6.72 seconds |
Started | Jul 14 04:56:51 PM PDT 24 |
Finished | Jul 14 04:56:58 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-e538e8aa-e1db-44fb-bdf1-cc2f1b5e6805 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892697148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2892697148 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.1161303538 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 74096844 ps |
CPU time | 14.11 seconds |
Started | Jul 14 04:56:51 PM PDT 24 |
Finished | Jul 14 04:57:05 PM PDT 24 |
Peak memory | 251756 kb |
Host | smart-c576d0ce-b092-481c-8e6e-b1aa12e7a8b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161303538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.1161303538 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.23220333 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 332704600 ps |
CPU time | 3.33 seconds |
Started | Jul 14 04:56:56 PM PDT 24 |
Finished | Jul 14 04:57:00 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-63355aba-5ee9-47f7-bec8-30d1a46f4540 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23220333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_mem_partial_access.23220333 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.3531777512 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 5923496296 ps |
CPU time | 13.09 seconds |
Started | Jul 14 04:56:54 PM PDT 24 |
Finished | Jul 14 04:57:08 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-076dd9a2-2aae-44f5-b386-f85c5e8a0d5b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531777512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.3531777512 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.3737007669 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 5388419911 ps |
CPU time | 710.19 seconds |
Started | Jul 14 04:56:44 PM PDT 24 |
Finished | Jul 14 05:08:35 PM PDT 24 |
Peak memory | 359256 kb |
Host | smart-2c4d6841-f36a-4dcf-97b0-d15721622955 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737007669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3737007669 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.758332852 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 286440114 ps |
CPU time | 3.71 seconds |
Started | Jul 14 04:56:49 PM PDT 24 |
Finished | Jul 14 04:56:53 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-a0500769-10f8-4653-883d-258e7c7f9f44 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758332852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.758332852 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2791599143 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 17283850748 ps |
CPU time | 408.33 seconds |
Started | Jul 14 04:56:49 PM PDT 24 |
Finished | Jul 14 05:03:38 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-85e75a6b-0d3b-4285-b937-041294c3f5bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791599143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.2791599143 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.2956342650 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 29305821 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:56:56 PM PDT 24 |
Finished | Jul 14 04:56:57 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-f1dcc293-7844-46d8-ac7f-b404a2664188 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956342650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2956342650 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.437563231 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 6239497036 ps |
CPU time | 399.44 seconds |
Started | Jul 14 04:56:49 PM PDT 24 |
Finished | Jul 14 05:03:29 PM PDT 24 |
Peak memory | 370240 kb |
Host | smart-a49e19dd-8a9b-49b6-b5b0-cb25ec253e3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437563231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.437563231 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.1428507596 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 385956598 ps |
CPU time | 57.7 seconds |
Started | Jul 14 04:56:44 PM PDT 24 |
Finished | Jul 14 04:57:42 PM PDT 24 |
Peak memory | 311488 kb |
Host | smart-2abcf04f-4afd-439c-b945-c5d3914c2606 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428507596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1428507596 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.2885369043 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 32614566324 ps |
CPU time | 2736.4 seconds |
Started | Jul 14 04:56:55 PM PDT 24 |
Finished | Jul 14 05:42:32 PM PDT 24 |
Peak memory | 375804 kb |
Host | smart-fbebeb9a-ab71-427d-81f6-ddf7f24040ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885369043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.2885369043 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3663766184 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 6945213928 ps |
CPU time | 170.1 seconds |
Started | Jul 14 04:56:49 PM PDT 24 |
Finished | Jul 14 04:59:40 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-7938de6a-b60b-4cdf-a578-4425652ccbbf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663766184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3663766184 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2207576900 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 95983122 ps |
CPU time | 45.12 seconds |
Started | Jul 14 04:56:48 PM PDT 24 |
Finished | Jul 14 04:57:34 PM PDT 24 |
Peak memory | 288692 kb |
Host | smart-66fdda3b-50f9-412b-9c32-87b68aef647a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207576900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2207576900 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1288384261 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 30485286443 ps |
CPU time | 971.27 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 05:13:20 PM PDT 24 |
Peak memory | 374632 kb |
Host | smart-285c9b19-6872-4fd9-b610-1d0a4f2dd78e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288384261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.1288384261 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.3847426588 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 18061842 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:57:11 PM PDT 24 |
Finished | Jul 14 04:57:12 PM PDT 24 |
Peak memory | 202592 kb |
Host | smart-5e8e86e1-1289-445b-9071-988051b0dd46 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847426588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3847426588 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.327957729 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1423802046 ps |
CPU time | 40.02 seconds |
Started | Jul 14 04:57:02 PM PDT 24 |
Finished | Jul 14 04:57:42 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-1d2cdc07-ee6f-40d4-9a61-52a82d25a1ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327957729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection. 327957729 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.2758361123 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 70532830573 ps |
CPU time | 608.71 seconds |
Started | Jul 14 04:57:08 PM PDT 24 |
Finished | Jul 14 05:07:17 PM PDT 24 |
Peak memory | 370484 kb |
Host | smart-1096ab36-0ea5-4fb7-a4cc-ac2dfb531f24 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758361123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.2758361123 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.854924268 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 2386778833 ps |
CPU time | 7.24 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 04:57:15 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-6eae4c47-900d-4a9b-97ca-c79a2ff48f7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854924268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.854924268 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.3586623869 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 477717195 ps |
CPU time | 153.53 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 04:59:42 PM PDT 24 |
Peak memory | 370336 kb |
Host | smart-0e9c0d48-6d89-43b0-bfbf-447d2d739651 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586623869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3586623869 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1215767956 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 324069949 ps |
CPU time | 3.33 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 04:57:11 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-252dfe06-7286-488d-97ff-c36f54c7e335 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215767956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1215767956 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2329142987 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1232599688 ps |
CPU time | 10.46 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 04:57:18 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-d298aee8-8b1a-48ca-b99f-378ffd294ffa |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329142987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2329142987 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3785148333 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 5756174449 ps |
CPU time | 1523.11 seconds |
Started | Jul 14 04:57:00 PM PDT 24 |
Finished | Jul 14 05:22:24 PM PDT 24 |
Peak memory | 374636 kb |
Host | smart-6e55b936-a45f-4971-96dc-6c7e3fc3dccc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785148333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3785148333 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.2014535244 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 303613841 ps |
CPU time | 25.99 seconds |
Started | Jul 14 04:57:00 PM PDT 24 |
Finished | Jul 14 04:57:27 PM PDT 24 |
Peak memory | 262256 kb |
Host | smart-9d2acf7f-6f18-4977-b73b-56cfb94055f6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014535244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.2014535244 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.903613164 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 69434290512 ps |
CPU time | 431.8 seconds |
Started | Jul 14 04:57:01 PM PDT 24 |
Finished | Jul 14 05:04:13 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-5cec9ced-8129-429d-8c7b-64fe076768c5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903613164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.903613164 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.3144761168 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 47176629 ps |
CPU time | 0.79 seconds |
Started | Jul 14 04:57:06 PM PDT 24 |
Finished | Jul 14 04:57:07 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-fb2e758b-db85-4875-bbb3-62f2a28a9249 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144761168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3144761168 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.505215448 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 24743139824 ps |
CPU time | 787.13 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 05:10:14 PM PDT 24 |
Peak memory | 371520 kb |
Host | smart-ab9d4a8f-3e8f-4b10-9dc7-495e8a85bfa6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505215448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.505215448 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.20723449 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 455003915 ps |
CPU time | 94.95 seconds |
Started | Jul 14 04:56:56 PM PDT 24 |
Finished | Jul 14 04:58:31 PM PDT 24 |
Peak memory | 341428 kb |
Host | smart-cf3abb0e-f6b0-4389-811a-8199b9806818 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20723449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.20723449 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.939398349 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 59039225781 ps |
CPU time | 1647.92 seconds |
Started | Jul 14 04:57:07 PM PDT 24 |
Finished | Jul 14 05:24:36 PM PDT 24 |
Peak memory | 382608 kb |
Host | smart-a69bab52-9a79-400c-97e0-a5b686e060ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939398349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.939398349 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2241637278 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 3043903467 ps |
CPU time | 222.37 seconds |
Started | Jul 14 04:57:00 PM PDT 24 |
Finished | Jul 14 05:00:43 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-bacac4cc-88e2-4657-b259-4a04c6e144c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241637278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.2241637278 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2471480746 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 57567197 ps |
CPU time | 5.28 seconds |
Started | Jul 14 04:57:06 PM PDT 24 |
Finished | Jul 14 04:57:11 PM PDT 24 |
Peak memory | 225932 kb |
Host | smart-cdd7094b-b0c2-4397-a4a5-8134638fea24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471480746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2471480746 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2055364352 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 14222109454 ps |
CPU time | 864.16 seconds |
Started | Jul 14 04:57:28 PM PDT 24 |
Finished | Jul 14 05:11:53 PM PDT 24 |
Peak memory | 373588 kb |
Host | smart-e4396067-5262-4eec-bfd5-3c7e9ec59a30 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055364352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2055364352 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.2983933119 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 49050785 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:57:24 PM PDT 24 |
Finished | Jul 14 04:57:26 PM PDT 24 |
Peak memory | 202544 kb |
Host | smart-bbd9ceb4-5483-444e-b789-59f8c7c7803b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983933119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2983933119 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.1467841131 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 1352572563 ps |
CPU time | 23.93 seconds |
Started | Jul 14 04:57:12 PM PDT 24 |
Finished | Jul 14 04:57:37 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-943e924e-88f1-4576-b966-b66be13b25e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467841131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1467841131 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.3317891332 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 11271000617 ps |
CPU time | 237.98 seconds |
Started | Jul 14 04:57:25 PM PDT 24 |
Finished | Jul 14 05:01:23 PM PDT 24 |
Peak memory | 342612 kb |
Host | smart-84589fb9-02e9-4033-8ea6-8c5cc8c128a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317891332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.3317891332 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.4091308664 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 461930686 ps |
CPU time | 4.27 seconds |
Started | Jul 14 04:57:18 PM PDT 24 |
Finished | Jul 14 04:57:23 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-35a94532-3dd5-408b-8340-bc9602eb62ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091308664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.4091308664 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.3477851579 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 134398238 ps |
CPU time | 151.16 seconds |
Started | Jul 14 04:57:18 PM PDT 24 |
Finished | Jul 14 04:59:50 PM PDT 24 |
Peak memory | 370136 kb |
Host | smart-7266f804-2304-4d0e-8e68-a908ea46c3d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477851579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.3477851579 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.603979255 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 174982143 ps |
CPU time | 3.29 seconds |
Started | Jul 14 04:57:24 PM PDT 24 |
Finished | Jul 14 04:57:27 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-c91992a0-953c-481d-a1ae-ba7a9989cc7a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603979255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_mem_partial_access.603979255 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.4027113702 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 2640682999 ps |
CPU time | 11.91 seconds |
Started | Jul 14 04:57:26 PM PDT 24 |
Finished | Jul 14 04:57:38 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-7775a04a-a901-4145-a3be-539d27763250 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027113702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.4027113702 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.1514577346 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 58854103871 ps |
CPU time | 1122.29 seconds |
Started | Jul 14 04:57:11 PM PDT 24 |
Finished | Jul 14 05:15:53 PM PDT 24 |
Peak memory | 370528 kb |
Host | smart-9d17513d-761d-48d6-a145-25dd88706ade |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514577346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.1514577346 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3916563878 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 28534340 ps |
CPU time | 1.18 seconds |
Started | Jul 14 04:57:18 PM PDT 24 |
Finished | Jul 14 04:57:20 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-e4778e41-4453-4f86-9b8d-d3bd8ca53b96 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916563878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3916563878 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3465195839 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 8058415078 ps |
CPU time | 180.2 seconds |
Started | Jul 14 04:57:21 PM PDT 24 |
Finished | Jul 14 05:00:21 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-966e07ce-87b3-4357-840f-2e73f0da2c72 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465195839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3465195839 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.1811053578 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 85279048 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:57:25 PM PDT 24 |
Finished | Jul 14 04:57:27 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-59564022-8238-4c9e-bfec-2435861604b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811053578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1811053578 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.257989224 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 7811054684 ps |
CPU time | 604.54 seconds |
Started | Jul 14 04:57:25 PM PDT 24 |
Finished | Jul 14 05:07:30 PM PDT 24 |
Peak memory | 371520 kb |
Host | smart-96861039-4af5-4e45-a7c7-82bcadf74dbf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257989224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.257989224 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.1029519398 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 222045525 ps |
CPU time | 11.62 seconds |
Started | Jul 14 04:57:11 PM PDT 24 |
Finished | Jul 14 04:57:24 PM PDT 24 |
Peak memory | 248736 kb |
Host | smart-cd7f1351-91fd-4b59-9966-8d664cbccf85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029519398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1029519398 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.2642419643 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 17742633362 ps |
CPU time | 3120.73 seconds |
Started | Jul 14 04:57:25 PM PDT 24 |
Finished | Jul 14 05:49:27 PM PDT 24 |
Peak memory | 376964 kb |
Host | smart-f5f326cb-43c9-42fa-b64c-53da1d09196d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642419643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.2642419643 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.555046118 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 1927691535 ps |
CPU time | 263.22 seconds |
Started | Jul 14 04:57:27 PM PDT 24 |
Finished | Jul 14 05:01:51 PM PDT 24 |
Peak memory | 359372 kb |
Host | smart-d8e6c912-57fa-4794-8545-f26b473e1cdd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=555046118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.555046118 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1154248033 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 3305838935 ps |
CPU time | 149.34 seconds |
Started | Jul 14 04:57:17 PM PDT 24 |
Finished | Jul 14 04:59:47 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-7aff73c3-fffa-495b-b0e2-1eea86b88b6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154248033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.1154248033 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.225267914 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 68555888 ps |
CPU time | 10.41 seconds |
Started | Jul 14 04:57:20 PM PDT 24 |
Finished | Jul 14 04:57:31 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-6f260f72-c8d5-496f-b3e6-45f57ffd049a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225267914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.225267914 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2150518729 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 17038582572 ps |
CPU time | 1438.56 seconds |
Started | Jul 14 04:57:33 PM PDT 24 |
Finished | Jul 14 05:21:32 PM PDT 24 |
Peak memory | 374600 kb |
Host | smart-c25c78a0-eeef-436a-ac53-ebd808c357da |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150518729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.2150518729 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.802881565 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 34679822 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:57:37 PM PDT 24 |
Finished | Jul 14 04:57:39 PM PDT 24 |
Peak memory | 202592 kb |
Host | smart-973b994c-e0a3-4942-9c6c-df5fdf98dd55 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802881565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.802881565 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.632936795 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 19858926523 ps |
CPU time | 81.94 seconds |
Started | Jul 14 04:57:25 PM PDT 24 |
Finished | Jul 14 04:58:48 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-687037d8-0d13-4bf9-b47a-70f7f5429699 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632936795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 632936795 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.161533114 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 1574924964 ps |
CPU time | 6.44 seconds |
Started | Jul 14 04:57:30 PM PDT 24 |
Finished | Jul 14 04:57:37 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-64e1c1ea-db6c-4053-88d0-e36ff0f6514c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161533114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.161533114 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.2564555607 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 216619026 ps |
CPU time | 68.43 seconds |
Started | Jul 14 04:57:31 PM PDT 24 |
Finished | Jul 14 04:58:40 PM PDT 24 |
Peak memory | 324412 kb |
Host | smart-899e1245-d520-4406-a005-5a9b4e5afe09 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564555607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2564555607 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2826983853 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 251139088 ps |
CPU time | 4.47 seconds |
Started | Jul 14 04:57:38 PM PDT 24 |
Finished | Jul 14 04:57:43 PM PDT 24 |
Peak memory | 210880 kb |
Host | smart-08a374e2-5834-43bb-9fe4-f178c89c0990 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826983853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.2826983853 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.116392170 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 659362862 ps |
CPU time | 10.89 seconds |
Started | Jul 14 04:57:37 PM PDT 24 |
Finished | Jul 14 04:57:49 PM PDT 24 |
Peak memory | 210904 kb |
Host | smart-94198799-826d-444f-b0c1-cd4b4fe06e11 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116392170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _mem_walk.116392170 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3012790112 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 45173588727 ps |
CPU time | 2167.89 seconds |
Started | Jul 14 04:57:26 PM PDT 24 |
Finished | Jul 14 05:33:35 PM PDT 24 |
Peak memory | 374644 kb |
Host | smart-f34eb67b-6508-4c2c-8fb7-982ee082a391 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012790112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3012790112 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.173051648 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 524021641 ps |
CPU time | 57.55 seconds |
Started | Jul 14 04:57:30 PM PDT 24 |
Finished | Jul 14 04:58:28 PM PDT 24 |
Peak memory | 306672 kb |
Host | smart-7fb458ff-f296-4432-a8d3-5d5daf08b204 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173051648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s ram_ctrl_partial_access.173051648 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1012333126 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 30867307359 ps |
CPU time | 281.77 seconds |
Started | Jul 14 04:57:30 PM PDT 24 |
Finished | Jul 14 05:02:12 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-6a0df099-5faf-45a4-968c-562c82c0bcbf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012333126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.1012333126 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.1305286687 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 27884515 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:57:37 PM PDT 24 |
Finished | Jul 14 04:57:39 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-0bcc78fd-c9b0-496e-b17a-51b8c279e14f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305286687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1305286687 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3606211738 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 14002131983 ps |
CPU time | 1663.08 seconds |
Started | Jul 14 04:57:38 PM PDT 24 |
Finished | Jul 14 05:25:22 PM PDT 24 |
Peak memory | 375620 kb |
Host | smart-094664a3-16ef-41b9-a9bd-b5cdb9cb4444 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606211738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3606211738 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.1542033995 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 836227902 ps |
CPU time | 12.82 seconds |
Started | Jul 14 04:57:27 PM PDT 24 |
Finished | Jul 14 04:57:41 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-a0eb7e4c-10fd-47b9-8b77-97c0dbb35b2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542033995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1542033995 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3862505969 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 1376859078 ps |
CPU time | 70.29 seconds |
Started | Jul 14 04:57:39 PM PDT 24 |
Finished | Jul 14 04:58:50 PM PDT 24 |
Peak memory | 266324 kb |
Host | smart-11a62527-4e79-4c75-a134-f113bd256a41 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3862505969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3862505969 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.607790810 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 2359756451 ps |
CPU time | 223 seconds |
Started | Jul 14 04:57:26 PM PDT 24 |
Finished | Jul 14 05:01:09 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-e420b308-ba8c-4554-9d0d-90b3d42d872b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607790810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_stress_pipeline.607790810 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2198766204 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 556307486 ps |
CPU time | 127.62 seconds |
Started | Jul 14 04:57:30 PM PDT 24 |
Finished | Jul 14 04:59:38 PM PDT 24 |
Peak memory | 357568 kb |
Host | smart-bac0598a-191f-4a79-a5da-e05890aa6323 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198766204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2198766204 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2764012372 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 5651572888 ps |
CPU time | 861.62 seconds |
Started | Jul 14 04:57:43 PM PDT 24 |
Finished | Jul 14 05:12:05 PM PDT 24 |
Peak memory | 369408 kb |
Host | smart-b722961f-62c9-4c70-80bd-146783f9af95 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764012372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.2764012372 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.3596649145 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 42026456 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 04:57:50 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-842462a6-7dc2-4904-bd79-36666d0fe7ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596649145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3596649145 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.464105328 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 6211073792 ps |
CPU time | 74.95 seconds |
Started | Jul 14 04:57:38 PM PDT 24 |
Finished | Jul 14 04:58:54 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-8d92869a-338d-4ab1-a014-34c82a3a917f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464105328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 464105328 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.131365806 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 8328313802 ps |
CPU time | 1176.54 seconds |
Started | Jul 14 04:57:44 PM PDT 24 |
Finished | Jul 14 05:17:21 PM PDT 24 |
Peak memory | 374040 kb |
Host | smart-201e0966-00f8-4027-9510-6b476801d8e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131365806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executabl e.131365806 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.1930375286 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 338709081 ps |
CPU time | 1.55 seconds |
Started | Jul 14 04:57:43 PM PDT 24 |
Finished | Jul 14 04:57:45 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-391882ac-4639-4ede-9d5b-e00ccecf375f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930375286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.1930375286 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.1531581900 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 157609594 ps |
CPU time | 2.04 seconds |
Started | Jul 14 04:57:43 PM PDT 24 |
Finished | Jul 14 04:57:46 PM PDT 24 |
Peak memory | 210864 kb |
Host | smart-26381283-de4d-4d75-9c36-d68d5c074433 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531581900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1531581900 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2997264001 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 89444451 ps |
CPU time | 2.71 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 04:57:53 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-1acc4c74-ad32-47cc-b6db-b71b0341419b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997264001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.2997264001 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.2676432851 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 175799669 ps |
CPU time | 10.85 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 04:58:00 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-087d50a4-d812-4aa8-81d4-0216fcee3fee |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676432851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.2676432851 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.1511107241 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 3100383913 ps |
CPU time | 807.3 seconds |
Started | Jul 14 04:57:37 PM PDT 24 |
Finished | Jul 14 05:11:05 PM PDT 24 |
Peak memory | 371392 kb |
Host | smart-de7add0f-3b9e-4a6c-9ed0-2971c8c71a44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511107241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.1511107241 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.1220171057 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 7532643526 ps |
CPU time | 21.31 seconds |
Started | Jul 14 04:57:39 PM PDT 24 |
Finished | Jul 14 04:58:01 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-76dccc9f-95c7-480b-86c1-3b526188c650 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220171057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.1220171057 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4275439628 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 15523808791 ps |
CPU time | 287.33 seconds |
Started | Jul 14 04:57:38 PM PDT 24 |
Finished | Jul 14 05:02:26 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-9b6bacec-297d-4bb6-89fb-235e7de1357c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275439628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.4275439628 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.1397550992 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 173632998 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:57:42 PM PDT 24 |
Finished | Jul 14 04:57:43 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-9e4d1da1-d5fa-470a-a962-47a8fbea7bd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397550992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1397550992 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.3270426801 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 10289478038 ps |
CPU time | 1482.1 seconds |
Started | Jul 14 04:57:42 PM PDT 24 |
Finished | Jul 14 05:22:24 PM PDT 24 |
Peak memory | 374412 kb |
Host | smart-dc7a0486-3030-4ce8-bf89-12d7bd93702f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270426801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3270426801 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.215136338 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 113558644 ps |
CPU time | 2.3 seconds |
Started | Jul 14 04:57:38 PM PDT 24 |
Finished | Jul 14 04:57:41 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-aa0f9c1c-61a6-4b5d-89a4-6852bdaffb37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215136338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.215136338 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.4208437947 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 121246429035 ps |
CPU time | 2243.99 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 05:35:14 PM PDT 24 |
Peak memory | 382824 kb |
Host | smart-6bab9b65-f2d6-4e69-bf38-66c8c36609e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208437947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.4208437947 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3580235020 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 5901168020 ps |
CPU time | 281.11 seconds |
Started | Jul 14 04:57:39 PM PDT 24 |
Finished | Jul 14 05:02:21 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-925b6a23-f60c-4dbb-8be3-28691f5c3718 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580235020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.3580235020 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2582630788 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 272879014 ps |
CPU time | 8.69 seconds |
Started | Jul 14 04:57:43 PM PDT 24 |
Finished | Jul 14 04:57:52 PM PDT 24 |
Peak memory | 243672 kb |
Host | smart-e77da58b-5bd7-4033-bd3a-d5df84ab1f3f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582630788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2582630788 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.122564642 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 5887138224 ps |
CPU time | 1432.56 seconds |
Started | Jul 14 04:57:55 PM PDT 24 |
Finished | Jul 14 05:21:49 PM PDT 24 |
Peak memory | 375316 kb |
Host | smart-aead91ce-ebaf-48ec-bdf3-33647dd1aecc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122564642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sram_ctrl_access_during_key_req.122564642 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.2304985975 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 36579781 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:58:01 PM PDT 24 |
Finished | Jul 14 04:58:02 PM PDT 24 |
Peak memory | 202500 kb |
Host | smart-d6a3a686-380d-4572-92ec-71b0284e5a25 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304985975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2304985975 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.743689971 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 1103345414 ps |
CPU time | 63.09 seconds |
Started | Jul 14 04:57:54 PM PDT 24 |
Finished | Jul 14 04:58:58 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-1cebdcff-c414-454c-ae27-d2abdebe5067 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743689971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection. 743689971 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.4022055605 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 7146575956 ps |
CPU time | 428.26 seconds |
Started | Jul 14 04:57:55 PM PDT 24 |
Finished | Jul 14 05:05:04 PM PDT 24 |
Peak memory | 365180 kb |
Host | smart-d1e9243d-5b17-43d8-82e7-4171f6ce8aff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022055605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.4022055605 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.2379656988 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 2766222920 ps |
CPU time | 9.77 seconds |
Started | Jul 14 04:57:58 PM PDT 24 |
Finished | Jul 14 04:58:08 PM PDT 24 |
Peak memory | 214932 kb |
Host | smart-cc3e6f92-50e9-4366-8a62-27bf46e00858 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379656988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.2379656988 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.4220937769 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 706442186 ps |
CPU time | 40.13 seconds |
Started | Jul 14 04:57:55 PM PDT 24 |
Finished | Jul 14 04:58:36 PM PDT 24 |
Peak memory | 292904 kb |
Host | smart-7df780fb-2868-49b0-b80d-47c91c491bf4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220937769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.4220937769 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.16655502 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 452592254 ps |
CPU time | 3.83 seconds |
Started | Jul 14 04:58:01 PM PDT 24 |
Finished | Jul 14 04:58:06 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-32510112-66b3-4157-8aee-2e1155e4e58f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16655502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_mem_partial_access.16655502 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.2059461917 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 1502724249 ps |
CPU time | 6.67 seconds |
Started | Jul 14 04:58:01 PM PDT 24 |
Finished | Jul 14 04:58:09 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-de6c2598-e906-4093-b6f5-8792f192874c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059461917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.2059461917 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.4253686040 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 14145193784 ps |
CPU time | 1303.53 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 05:19:33 PM PDT 24 |
Peak memory | 358832 kb |
Host | smart-8c013e1d-c4dc-43fe-86f9-e1e9f7f9a67e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253686040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.4253686040 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.381417252 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 467810656 ps |
CPU time | 5.91 seconds |
Started | Jul 14 04:57:55 PM PDT 24 |
Finished | Jul 14 04:58:02 PM PDT 24 |
Peak memory | 219364 kb |
Host | smart-9178e9c0-e12b-493d-82c0-a14e099d331c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381417252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.381417252 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3290927073 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 39761661568 ps |
CPU time | 267.98 seconds |
Started | Jul 14 04:57:55 PM PDT 24 |
Finished | Jul 14 05:02:24 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-e81f571e-9a5f-4614-8c20-35a29de2206c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290927073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.3290927073 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.2915740417 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 45960212 ps |
CPU time | 0.74 seconds |
Started | Jul 14 04:57:55 PM PDT 24 |
Finished | Jul 14 04:57:57 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-88ca4eb2-e6c1-4d2b-a0b6-3fbb6ba72936 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915740417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2915740417 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.2039230538 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 14728515551 ps |
CPU time | 1482.01 seconds |
Started | Jul 14 04:57:54 PM PDT 24 |
Finished | Jul 14 05:22:37 PM PDT 24 |
Peak memory | 375392 kb |
Host | smart-0967b2e1-7aa1-4317-9da3-e1806b316c26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039230538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2039230538 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.2042229858 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 983451126 ps |
CPU time | 17.58 seconds |
Started | Jul 14 04:57:49 PM PDT 24 |
Finished | Jul 14 04:58:07 PM PDT 24 |
Peak memory | 251856 kb |
Host | smart-8dc06b77-334b-4fa3-a77b-60aa4ab8a7b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042229858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2042229858 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.1282248238 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 85820128017 ps |
CPU time | 3578.44 seconds |
Started | Jul 14 04:58:00 PM PDT 24 |
Finished | Jul 14 05:57:39 PM PDT 24 |
Peak memory | 375584 kb |
Host | smart-7cad2042-94c4-48a7-90a5-ac3e28de2e1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282248238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.1282248238 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.942364313 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 2259460294 ps |
CPU time | 34.4 seconds |
Started | Jul 14 04:58:02 PM PDT 24 |
Finished | Jul 14 04:58:37 PM PDT 24 |
Peak memory | 212164 kb |
Host | smart-91e0befa-e173-4811-ac68-d18cba6bcde0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=942364313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.942364313 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3678806574 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 2064089808 ps |
CPU time | 194.79 seconds |
Started | Jul 14 04:57:58 PM PDT 24 |
Finished | Jul 14 05:01:13 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-3251ed9d-525d-4a2c-8b92-3e0e17940d0f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678806574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.3678806574 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1275208705 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 57675832 ps |
CPU time | 3.97 seconds |
Started | Jul 14 04:57:57 PM PDT 24 |
Finished | Jul 14 04:58:01 PM PDT 24 |
Peak memory | 220948 kb |
Host | smart-0393530f-bafd-4507-b277-9a808bc6f35f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275208705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1275208705 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3434608417 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 43765833278 ps |
CPU time | 911.48 seconds |
Started | Jul 14 04:58:09 PM PDT 24 |
Finished | Jul 14 05:13:21 PM PDT 24 |
Peak memory | 360280 kb |
Host | smart-09f80dc3-6ca4-4493-be56-80db1a7a6bb3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434608417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.3434608417 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.2541123723 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 190005412 ps |
CPU time | 0.73 seconds |
Started | Jul 14 04:58:15 PM PDT 24 |
Finished | Jul 14 04:58:16 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-0e720fd5-f0fc-429a-b0ae-1a154576b648 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541123723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2541123723 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2285297795 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 2282470893 ps |
CPU time | 27.26 seconds |
Started | Jul 14 04:58:03 PM PDT 24 |
Finished | Jul 14 04:58:31 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-c7bbdc2a-4504-459e-91d2-165095badaa7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285297795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2285297795 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.27658492 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 1051416719 ps |
CPU time | 724.09 seconds |
Started | Jul 14 04:58:07 PM PDT 24 |
Finished | Jul 14 05:10:12 PM PDT 24 |
Peak memory | 373068 kb |
Host | smart-16b397da-89c6-41d2-a372-63ca29c60a38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable .27658492 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.2793815938 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 480638512 ps |
CPU time | 3.15 seconds |
Started | Jul 14 04:58:09 PM PDT 24 |
Finished | Jul 14 04:58:13 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-f0812aa6-e875-4031-86a0-c4030cd01b1c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793815938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.2793815938 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.2015405996 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 512017987 ps |
CPU time | 128.54 seconds |
Started | Jul 14 04:58:09 PM PDT 24 |
Finished | Jul 14 05:00:18 PM PDT 24 |
Peak memory | 370312 kb |
Host | smart-e37b609d-f6ef-4a25-81ae-d17766d935ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015405996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.2015405996 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1021906458 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 325274827 ps |
CPU time | 5.52 seconds |
Started | Jul 14 04:58:14 PM PDT 24 |
Finished | Jul 14 04:58:19 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-dc79eb76-0611-46a5-9a82-1f3591d0c129 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021906458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1021906458 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.549224452 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 371861774 ps |
CPU time | 5.34 seconds |
Started | Jul 14 04:58:08 PM PDT 24 |
Finished | Jul 14 04:58:14 PM PDT 24 |
Peak memory | 210916 kb |
Host | smart-18bb3492-d094-4485-bc5e-739d7d4c0f78 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549224452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.549224452 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.2118285008 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 34328301223 ps |
CPU time | 643.09 seconds |
Started | Jul 14 04:58:01 PM PDT 24 |
Finished | Jul 14 05:08:45 PM PDT 24 |
Peak memory | 374640 kb |
Host | smart-881300e2-097c-49cd-ae1f-a1bf0ccb75b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118285008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.2118285008 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.1304029720 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 8491426449 ps |
CPU time | 13.39 seconds |
Started | Jul 14 04:58:03 PM PDT 24 |
Finished | Jul 14 04:58:17 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-4595b457-6619-4dde-a919-65360c0faf6d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304029720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.1304029720 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1094200557 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 2919992280 ps |
CPU time | 205.77 seconds |
Started | Jul 14 04:58:02 PM PDT 24 |
Finished | Jul 14 05:01:29 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-aeb2a72e-441c-46b0-8f4b-9922a14dc3cb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094200557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1094200557 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.1683983386 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 26335979 ps |
CPU time | 0.76 seconds |
Started | Jul 14 04:58:09 PM PDT 24 |
Finished | Jul 14 04:58:10 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-92514ca9-ea45-40bc-8e2c-fea3a267fd10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683983386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1683983386 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.1957953658 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 21831811890 ps |
CPU time | 1280.76 seconds |
Started | Jul 14 04:58:07 PM PDT 24 |
Finished | Jul 14 05:19:29 PM PDT 24 |
Peak memory | 371532 kb |
Host | smart-c73c3693-91d9-47f9-9998-47bc61b58274 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957953658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1957953658 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.2467043577 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 1586264681 ps |
CPU time | 18.51 seconds |
Started | Jul 14 04:58:02 PM PDT 24 |
Finished | Jul 14 04:58:21 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-76ad9727-0d4e-4a0a-bf07-d171404a86af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467043577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2467043577 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.3243938417 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 25357167384 ps |
CPU time | 1412.77 seconds |
Started | Jul 14 04:58:13 PM PDT 24 |
Finished | Jul 14 05:21:47 PM PDT 24 |
Peak memory | 358748 kb |
Host | smart-108f42cb-f393-4eba-86b9-d10ca161432e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243938417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.3243938417 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.7216791 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 1884747786 ps |
CPU time | 809.8 seconds |
Started | Jul 14 04:58:13 PM PDT 24 |
Finished | Jul 14 05:11:44 PM PDT 24 |
Peak memory | 373328 kb |
Host | smart-d53db403-4b67-4d49-8d9c-c3fdcaaf9868 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=7216791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.7216791 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3027938120 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 7341772044 ps |
CPU time | 372.88 seconds |
Started | Jul 14 04:58:02 PM PDT 24 |
Finished | Jul 14 05:04:15 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-ee7c3743-935f-480e-bc0b-cbfc1fc00b65 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027938120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3027938120 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3223133604 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 448926749 ps |
CPU time | 82.42 seconds |
Started | Jul 14 04:58:08 PM PDT 24 |
Finished | Jul 14 04:59:31 PM PDT 24 |
Peak memory | 319084 kb |
Host | smart-da208cab-7f7b-4dc5-82be-d23cf7aef4c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223133604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3223133604 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3254450954 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 3240891952 ps |
CPU time | 1359.73 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 05:16:42 PM PDT 24 |
Peak memory | 372980 kb |
Host | smart-6a055d8d-7bed-4faa-9e0e-707f36cce4f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254450954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3254450954 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.1642306215 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 41301384 ps |
CPU time | 0.76 seconds |
Started | Jul 14 04:54:10 PM PDT 24 |
Finished | Jul 14 04:54:11 PM PDT 24 |
Peak memory | 202544 kb |
Host | smart-b4bee419-e06b-4435-a813-daec7b6f3578 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642306215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1642306215 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.259773749 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 780234589 ps |
CPU time | 17.44 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 04:54:18 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-091a4836-b31c-4c6c-90a7-a8c89bb1467b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259773749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.259773749 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.3066185657 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 13008521197 ps |
CPU time | 952.51 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 05:09:53 PM PDT 24 |
Peak memory | 366304 kb |
Host | smart-6f5ada18-da6b-4c99-93a7-831c1fb3939a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066185657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.3066185657 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.3107479903 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 6836060183 ps |
CPU time | 10.16 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 04:54:12 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-6f451621-cf4c-4264-aee9-88c7b3fa4f06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107479903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.3107479903 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.2700607528 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 193604793 ps |
CPU time | 68.21 seconds |
Started | Jul 14 04:54:02 PM PDT 24 |
Finished | Jul 14 04:55:11 PM PDT 24 |
Peak memory | 308520 kb |
Host | smart-acd4046b-ade5-4a67-886e-6146c4424d8c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700607528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.2700607528 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3974998774 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 953294177 ps |
CPU time | 4.44 seconds |
Started | Jul 14 04:54:11 PM PDT 24 |
Finished | Jul 14 04:54:16 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-9a789a33-9efb-4c35-b954-e2e2f3e4d86c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974998774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3974998774 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.44164424 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 343488159 ps |
CPU time | 9.78 seconds |
Started | Jul 14 04:54:09 PM PDT 24 |
Finished | Jul 14 04:54:20 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-1effb49f-ef99-43c8-8474-37599e9e5ae0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44164424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m em_walk.44164424 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.3785309684 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 13376110160 ps |
CPU time | 432.84 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 05:01:14 PM PDT 24 |
Peak memory | 361984 kb |
Host | smart-83fb657a-ae50-49d9-920b-d6313e1ef234 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785309684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.3785309684 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3928471282 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 342604411 ps |
CPU time | 67.54 seconds |
Started | Jul 14 04:54:07 PM PDT 24 |
Finished | Jul 14 04:55:15 PM PDT 24 |
Peak memory | 327144 kb |
Host | smart-13cdd653-2ef1-4a3e-a88c-35d0c4a76cfe |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928471282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3928471282 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1197197586 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 26070484089 ps |
CPU time | 354.72 seconds |
Started | Jul 14 04:54:01 PM PDT 24 |
Finished | Jul 14 04:59:56 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-86428932-8f1b-4d80-b114-3184a888a814 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197197586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.1197197586 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.832862826 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 44480633 ps |
CPU time | 0.85 seconds |
Started | Jul 14 04:54:08 PM PDT 24 |
Finished | Jul 14 04:54:09 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-f7e14b89-1047-4642-9a7c-56e47d37e719 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832862826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.832862826 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.864142176 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 25067006060 ps |
CPU time | 1214.37 seconds |
Started | Jul 14 04:54:02 PM PDT 24 |
Finished | Jul 14 05:14:17 PM PDT 24 |
Peak memory | 367436 kb |
Host | smart-6ab482fc-3f16-4417-88ce-64a74375ffad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864142176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.864142176 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.3109581679 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 1071302322 ps |
CPU time | 2.28 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:54:19 PM PDT 24 |
Peak memory | 221964 kb |
Host | smart-9f03c706-4f01-4c2a-86aa-5aa2e331c90c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109581679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3109581679 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.76169156 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 1913781580 ps |
CPU time | 16.72 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 04:54:18 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-6f85a15e-552e-493f-816b-b606bbd95335 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76169156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.76169156 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.2315177529 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 74507718458 ps |
CPU time | 7459.08 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 06:58:35 PM PDT 24 |
Peak memory | 377008 kb |
Host | smart-80d59175-fdaf-48c6-959e-d217e2dff798 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315177529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.2315177529 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.74533400 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 2817069654 ps |
CPU time | 32.9 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:54:49 PM PDT 24 |
Peak memory | 212268 kb |
Host | smart-aa5a79cd-2279-40ce-a5d3-977f044d5090 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=74533400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.74533400 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2101338466 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 5851247197 ps |
CPU time | 151.69 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 04:56:33 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-9ab458c1-0b1e-45b8-a0ae-219a9446f3e2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101338466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.2101338466 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2661920351 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 101480987 ps |
CPU time | 47.37 seconds |
Started | Jul 14 04:54:00 PM PDT 24 |
Finished | Jul 14 04:54:49 PM PDT 24 |
Peak memory | 291660 kb |
Host | smart-147d4ed3-0bf4-40e8-857d-880231e3e513 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661920351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2661920351 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3704174074 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 2304409973 ps |
CPU time | 602.16 seconds |
Started | Jul 14 04:58:18 PM PDT 24 |
Finished | Jul 14 05:08:21 PM PDT 24 |
Peak memory | 365468 kb |
Host | smart-5d9ca43a-bf69-4baa-954c-2e3302f944fe |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704174074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.3704174074 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.1639082574 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 42724053 ps |
CPU time | 0.62 seconds |
Started | Jul 14 04:58:30 PM PDT 24 |
Finished | Jul 14 04:58:32 PM PDT 24 |
Peak memory | 202516 kb |
Host | smart-c9216c42-466d-485b-9603-ffef7fd42a4e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639082574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1639082574 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.2739145418 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 1429250635 ps |
CPU time | 28.61 seconds |
Started | Jul 14 04:58:15 PM PDT 24 |
Finished | Jul 14 04:58:44 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-9e87398e-df92-4a69-89a1-c9bbaa302d97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739145418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .2739145418 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.3089908976 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 5850881118 ps |
CPU time | 867.94 seconds |
Started | Jul 14 04:58:20 PM PDT 24 |
Finished | Jul 14 05:12:49 PM PDT 24 |
Peak memory | 369476 kb |
Host | smart-e131b76d-8614-4e1d-ba3b-2e61ed4e9c54 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089908976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.3089908976 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.3800710392 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 493513482 ps |
CPU time | 5.66 seconds |
Started | Jul 14 04:58:20 PM PDT 24 |
Finished | Jul 14 04:58:26 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-4d270729-27dd-4bbc-a34e-7468044046fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800710392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.3800710392 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.3528787083 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 231141983 ps |
CPU time | 3.85 seconds |
Started | Jul 14 04:58:19 PM PDT 24 |
Finished | Jul 14 04:58:23 PM PDT 24 |
Peak memory | 219192 kb |
Host | smart-82b19946-c377-44d8-be23-4ebdc76d47be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528787083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.3528787083 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2501817704 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 188379475 ps |
CPU time | 6.21 seconds |
Started | Jul 14 04:58:26 PM PDT 24 |
Finished | Jul 14 04:58:32 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-8bb89137-6820-4e77-a544-dda6323276c3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501817704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.2501817704 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.1769120043 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 138625141 ps |
CPU time | 9.02 seconds |
Started | Jul 14 04:58:20 PM PDT 24 |
Finished | Jul 14 04:58:29 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-87fcfb77-59e8-4d67-bb71-3c458c6abccf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769120043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1769120043 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1713085236 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 13108003557 ps |
CPU time | 1106.45 seconds |
Started | Jul 14 04:58:15 PM PDT 24 |
Finished | Jul 14 05:16:41 PM PDT 24 |
Peak memory | 371604 kb |
Host | smart-299cc9ad-a855-4bec-879b-50ca32df5004 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713085236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1713085236 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.2934233232 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 192138837 ps |
CPU time | 115.11 seconds |
Started | Jul 14 04:58:18 PM PDT 24 |
Finished | Jul 14 05:00:14 PM PDT 24 |
Peak memory | 342000 kb |
Host | smart-b71d0bc2-83c6-4ab3-8e7f-31c5a687595e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934233232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.2934233232 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1880277998 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 12038655745 ps |
CPU time | 299.79 seconds |
Started | Jul 14 04:58:22 PM PDT 24 |
Finished | Jul 14 05:03:22 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-07065ca3-055c-4634-befa-36c1aca46c69 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880277998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.1880277998 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.1141428724 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 88713670 ps |
CPU time | 0.79 seconds |
Started | Jul 14 04:58:22 PM PDT 24 |
Finished | Jul 14 04:58:24 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-89638c46-5f46-468c-a800-a47302b7f665 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141428724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1141428724 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.4089517606 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 9320119996 ps |
CPU time | 460.75 seconds |
Started | Jul 14 04:58:20 PM PDT 24 |
Finished | Jul 14 05:06:01 PM PDT 24 |
Peak memory | 333680 kb |
Host | smart-a0106992-af12-42f5-9c8b-ed80d7663c0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089517606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4089517606 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.4034569835 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 4069922757 ps |
CPU time | 7.37 seconds |
Started | Jul 14 04:58:12 PM PDT 24 |
Finished | Jul 14 04:58:20 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-1a810d49-8a7b-4846-ae86-b04a3516c001 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034569835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.4034569835 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.2255165649 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 44637575321 ps |
CPU time | 4639.93 seconds |
Started | Jul 14 04:58:26 PM PDT 24 |
Finished | Jul 14 06:15:47 PM PDT 24 |
Peak memory | 375672 kb |
Host | smart-7d74bfe2-4451-4d04-bcf2-dc270f47cb84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255165649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.2255165649 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1000753422 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 4526078322 ps |
CPU time | 428.98 seconds |
Started | Jul 14 04:58:13 PM PDT 24 |
Finished | Jul 14 05:05:22 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-894bd0e3-bd0e-48ae-8bb2-6d70805234e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000753422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1000753422 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.517696868 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 131191696 ps |
CPU time | 83.11 seconds |
Started | Jul 14 04:58:22 PM PDT 24 |
Finished | Jul 14 04:59:46 PM PDT 24 |
Peak memory | 328052 kb |
Host | smart-690827e6-9c00-482f-8243-495f1fb672b9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517696868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.517696868 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.4153677971 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 6040550086 ps |
CPU time | 1015.93 seconds |
Started | Jul 14 04:58:32 PM PDT 24 |
Finished | Jul 14 05:15:28 PM PDT 24 |
Peak memory | 374620 kb |
Host | smart-089ddc0e-2832-4e24-8e60-748f5a18fe35 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153677971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.4153677971 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.2477345632 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 13588792 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:58:38 PM PDT 24 |
Finished | Jul 14 04:58:39 PM PDT 24 |
Peak memory | 202268 kb |
Host | smart-76ac77f4-7168-4a4e-bac6-c0b1b0cca302 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477345632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2477345632 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.483380140 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1181773457 ps |
CPU time | 17.5 seconds |
Started | Jul 14 04:58:26 PM PDT 24 |
Finished | Jul 14 04:58:44 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-d94bdab3-bdda-4115-8c24-2a5eff62b144 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483380140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection. 483380140 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.2986306076 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 107081060658 ps |
CPU time | 1455.24 seconds |
Started | Jul 14 04:58:31 PM PDT 24 |
Finished | Jul 14 05:22:47 PM PDT 24 |
Peak memory | 369468 kb |
Host | smart-af4091bc-5da5-46ee-95d3-5f355c54c4e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986306076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.2986306076 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.173601735 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 354667559 ps |
CPU time | 4.59 seconds |
Started | Jul 14 04:58:35 PM PDT 24 |
Finished | Jul 14 04:58:39 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-5faa32af-3722-42e1-8d10-51680d7a09ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173601735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc alation.173601735 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.2421752877 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 127435131 ps |
CPU time | 82.58 seconds |
Started | Jul 14 04:58:35 PM PDT 24 |
Finished | Jul 14 04:59:58 PM PDT 24 |
Peak memory | 360236 kb |
Host | smart-a2606d9e-1c79-43c0-af7c-2d854c49e9f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421752877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.2421752877 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3955061161 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 387774385 ps |
CPU time | 5.9 seconds |
Started | Jul 14 04:58:39 PM PDT 24 |
Finished | Jul 14 04:58:45 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-e93217c0-9504-4dd6-9f28-8b471c7a9c1b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955061161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.3955061161 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.3772475141 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 1519300267 ps |
CPU time | 11.76 seconds |
Started | Jul 14 04:58:38 PM PDT 24 |
Finished | Jul 14 04:58:50 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-8b76b3d0-47e0-40f6-85d4-a27611aa89b5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772475141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.3772475141 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.1746300482 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 6250047333 ps |
CPU time | 472.05 seconds |
Started | Jul 14 04:58:26 PM PDT 24 |
Finished | Jul 14 05:06:19 PM PDT 24 |
Peak memory | 339320 kb |
Host | smart-3c82c98e-17d4-4e16-9b39-66f504b8830c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746300482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.1746300482 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.1607408589 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2876552279 ps |
CPU time | 17.61 seconds |
Started | Jul 14 04:58:33 PM PDT 24 |
Finished | Jul 14 04:58:51 PM PDT 24 |
Peak memory | 250880 kb |
Host | smart-fec5a038-899f-403e-98d2-d7c761564314 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607408589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.1607408589 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2398537287 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 51339967260 ps |
CPU time | 318.45 seconds |
Started | Jul 14 04:58:32 PM PDT 24 |
Finished | Jul 14 05:03:51 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-3da26cf3-4a1f-4c26-9506-436146d8012c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398537287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2398537287 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.876674353 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 48609087 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:58:39 PM PDT 24 |
Finished | Jul 14 04:58:40 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-e507de91-c3c8-49de-bbae-22bc443ca4d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876674353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.876674353 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.2003270883 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 3734792611 ps |
CPU time | 1032.83 seconds |
Started | Jul 14 04:58:38 PM PDT 24 |
Finished | Jul 14 05:15:51 PM PDT 24 |
Peak memory | 371688 kb |
Host | smart-76663773-3e1b-4561-92dd-f89ca8d243fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003270883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2003270883 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.2592984617 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 1210074058 ps |
CPU time | 13.75 seconds |
Started | Jul 14 04:58:30 PM PDT 24 |
Finished | Jul 14 04:58:45 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-8b796f73-8192-41f7-9cef-e327ce4a0d90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592984617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2592984617 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.2192336962 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 357316767931 ps |
CPU time | 6735.09 seconds |
Started | Jul 14 04:58:39 PM PDT 24 |
Finished | Jul 14 06:50:56 PM PDT 24 |
Peak memory | 383852 kb |
Host | smart-a01715a4-73be-4375-9821-597b157f2a94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192336962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.2192336962 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3924495798 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 4882393386 ps |
CPU time | 243.18 seconds |
Started | Jul 14 04:58:33 PM PDT 24 |
Finished | Jul 14 05:02:36 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-282bc55c-e2dc-414b-9a55-dadeefda96eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924495798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3924495798 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1533609472 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 190213467 ps |
CPU time | 64.62 seconds |
Started | Jul 14 04:58:32 PM PDT 24 |
Finished | Jul 14 04:59:37 PM PDT 24 |
Peak memory | 300852 kb |
Host | smart-e67be965-9949-4a96-ab94-ca8b5ae87e3a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533609472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1533609472 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.692200697 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 13141628025 ps |
CPU time | 1134.41 seconds |
Started | Jul 14 04:58:52 PM PDT 24 |
Finished | Jul 14 05:17:47 PM PDT 24 |
Peak memory | 374816 kb |
Host | smart-d2e4fb15-afef-413b-9eca-f8fa6dd4fec7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692200697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sram_ctrl_access_during_key_req.692200697 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.1423865814 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 18173620 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:59:00 PM PDT 24 |
Finished | Jul 14 04:59:01 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-ac0ffc10-af5c-4ea1-a72f-9aabac465945 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423865814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1423865814 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.4045599092 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 28172453134 ps |
CPU time | 65.88 seconds |
Started | Jul 14 04:58:45 PM PDT 24 |
Finished | Jul 14 04:59:51 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-8dec2332-fc08-4152-bfb3-b0f3fea9a57b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045599092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .4045599092 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.4074435857 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 57600588462 ps |
CPU time | 2248.37 seconds |
Started | Jul 14 04:58:53 PM PDT 24 |
Finished | Jul 14 05:36:22 PM PDT 24 |
Peak memory | 375172 kb |
Host | smart-bf868030-c9bb-4918-a67c-05e83b950b8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074435857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.4074435857 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.3803352644 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 1750399060 ps |
CPU time | 7.38 seconds |
Started | Jul 14 04:58:53 PM PDT 24 |
Finished | Jul 14 04:59:01 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-d51da332-a616-45e1-a690-a1168a73baae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803352644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3803352644 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.1857500703 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 844759096 ps |
CPU time | 39.29 seconds |
Started | Jul 14 04:58:45 PM PDT 24 |
Finished | Jul 14 04:59:25 PM PDT 24 |
Peak memory | 286580 kb |
Host | smart-2c14f047-aab7-4203-975e-44bcaece761e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857500703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.1857500703 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1420302939 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 178303512 ps |
CPU time | 6.18 seconds |
Started | Jul 14 04:58:59 PM PDT 24 |
Finished | Jul 14 04:59:05 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-c3f172ab-5d8e-402b-8373-c13d53a98fea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420302939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.1420302939 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3909125805 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 266495341 ps |
CPU time | 8.81 seconds |
Started | Jul 14 04:58:59 PM PDT 24 |
Finished | Jul 14 04:59:08 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-69bfb101-f137-4a5c-8f57-f3f476d72876 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909125805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3909125805 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.217937044 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 6940919357 ps |
CPU time | 686.81 seconds |
Started | Jul 14 04:58:45 PM PDT 24 |
Finished | Jul 14 05:10:13 PM PDT 24 |
Peak memory | 370524 kb |
Host | smart-2f69215e-7052-402d-b448-9d07ade264c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217937044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip le_keys.217937044 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.236846885 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 318277671 ps |
CPU time | 6.28 seconds |
Started | Jul 14 04:58:46 PM PDT 24 |
Finished | Jul 14 04:58:52 PM PDT 24 |
Peak memory | 223904 kb |
Host | smart-944105d4-a565-411a-accf-afd8791fa530 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236846885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s ram_ctrl_partial_access.236846885 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.476267483 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 29378178 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:58:53 PM PDT 24 |
Finished | Jul 14 04:58:54 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-bbc2eb5c-8e8b-4b3c-85b3-28fb7ac42b61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476267483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.476267483 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.1406900374 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 40129893135 ps |
CPU time | 1501.13 seconds |
Started | Jul 14 04:58:52 PM PDT 24 |
Finished | Jul 14 05:23:54 PM PDT 24 |
Peak memory | 374672 kb |
Host | smart-c2ab5e2e-0497-438c-bad7-7eb09c0ffe7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406900374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1406900374 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1836556111 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1385725984 ps |
CPU time | 5.13 seconds |
Started | Jul 14 04:58:39 PM PDT 24 |
Finished | Jul 14 04:58:45 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-550de3bc-bbed-493b-8127-ab8331730b8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836556111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1836556111 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.2000354021 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 3137240790 ps |
CPU time | 744.01 seconds |
Started | Jul 14 04:59:00 PM PDT 24 |
Finished | Jul 14 05:11:24 PM PDT 24 |
Peak memory | 366108 kb |
Host | smart-ae9bc950-920b-47aa-9d8f-db5116cce7d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000354021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.2000354021 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.332614597 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 2512675741 ps |
CPU time | 231.82 seconds |
Started | Jul 14 04:58:48 PM PDT 24 |
Finished | Jul 14 05:02:40 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-e3daa0ce-5823-4900-afed-772be0b8f0b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332614597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_stress_pipeline.332614597 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2971632592 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 452953964 ps |
CPU time | 65.3 seconds |
Started | Jul 14 04:58:52 PM PDT 24 |
Finished | Jul 14 04:59:57 PM PDT 24 |
Peak memory | 305628 kb |
Host | smart-6b94d41c-5695-4dd9-b5d9-e197a85914d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971632592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2971632592 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.699434949 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 14017845350 ps |
CPU time | 1531.15 seconds |
Started | Jul 14 04:59:13 PM PDT 24 |
Finished | Jul 14 05:24:44 PM PDT 24 |
Peak memory | 374864 kb |
Host | smart-64e408aa-8b3b-4c20-a695-8a2b8b77e4d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699434949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 33.sram_ctrl_access_during_key_req.699434949 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.3267096179 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 14274297 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:59:22 PM PDT 24 |
Finished | Jul 14 04:59:23 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-97dacd94-2951-4d1d-bf61-a8bfd4082899 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267096179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3267096179 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.1796034907 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 5403755377 ps |
CPU time | 75.54 seconds |
Started | Jul 14 04:59:08 PM PDT 24 |
Finished | Jul 14 05:00:24 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-5ecf8254-661f-4749-9739-c78eaa7e6a1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796034907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1796034907 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.3738697315 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 8597437172 ps |
CPU time | 802.65 seconds |
Started | Jul 14 04:59:13 PM PDT 24 |
Finished | Jul 14 05:12:37 PM PDT 24 |
Peak memory | 370112 kb |
Host | smart-65728060-0255-4d2c-bf3e-dcff1b101f60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738697315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3738697315 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.611797637 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 665244798 ps |
CPU time | 6.93 seconds |
Started | Jul 14 04:59:13 PM PDT 24 |
Finished | Jul 14 04:59:21 PM PDT 24 |
Peak memory | 214076 kb |
Host | smart-f66daf71-43ff-41cf-8517-c016d41806b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611797637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc alation.611797637 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.245258887 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 115332722 ps |
CPU time | 77.91 seconds |
Started | Jul 14 04:59:14 PM PDT 24 |
Finished | Jul 14 05:00:33 PM PDT 24 |
Peak memory | 321040 kb |
Host | smart-130309a9-5269-4ee2-960a-ce39273c4622 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245258887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.sram_ctrl_max_throughput.245258887 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3864368353 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 2878442010 ps |
CPU time | 6.79 seconds |
Started | Jul 14 04:59:14 PM PDT 24 |
Finished | Jul 14 04:59:21 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-e9aa4fd1-198e-4b30-bd76-01141cd5def6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864368353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.3864368353 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.3399409825 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 382306358 ps |
CPU time | 5.65 seconds |
Started | Jul 14 04:59:12 PM PDT 24 |
Finished | Jul 14 04:59:18 PM PDT 24 |
Peak memory | 210884 kb |
Host | smart-fa4a5716-8fce-4728-a415-47eac188b807 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399409825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.3399409825 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.646658310 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 9020025769 ps |
CPU time | 127.77 seconds |
Started | Jul 14 04:59:09 PM PDT 24 |
Finished | Jul 14 05:01:17 PM PDT 24 |
Peak memory | 324024 kb |
Host | smart-c543f123-ba17-4db1-8e7c-653353dcdc69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646658310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.646658310 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.180247473 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 643006468 ps |
CPU time | 94.53 seconds |
Started | Jul 14 04:59:06 PM PDT 24 |
Finished | Jul 14 05:00:41 PM PDT 24 |
Peak memory | 335724 kb |
Host | smart-0e35ba2f-cc84-4837-9a1c-c792e72abf35 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180247473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.180247473 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1171203344 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 13602405796 ps |
CPU time | 254.8 seconds |
Started | Jul 14 04:59:14 PM PDT 24 |
Finished | Jul 14 05:03:29 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-47733a65-ac26-426d-bbef-4b0d063685a1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171203344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.1171203344 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.3221592694 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 78320045 ps |
CPU time | 0.76 seconds |
Started | Jul 14 04:59:13 PM PDT 24 |
Finished | Jul 14 04:59:15 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-442d3cd7-e7aa-4956-82b8-f6319d9d5d1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221592694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3221592694 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.2607216895 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 29237993953 ps |
CPU time | 1413.66 seconds |
Started | Jul 14 06:17:28 PM PDT 24 |
Finished | Jul 14 06:41:03 PM PDT 24 |
Peak memory | 374576 kb |
Host | smart-8fff559d-d3a5-422e-bdea-2a151d8b8ab1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607216895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2607216895 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.1470022637 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 584178682 ps |
CPU time | 7.18 seconds |
Started | Jul 14 04:59:07 PM PDT 24 |
Finished | Jul 14 04:59:15 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-a2bd82a2-2679-48b6-b2b4-d311eead3645 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470022637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1470022637 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.1016851322 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 48561145516 ps |
CPU time | 2840.02 seconds |
Started | Jul 14 04:59:21 PM PDT 24 |
Finished | Jul 14 05:46:41 PM PDT 24 |
Peak memory | 380788 kb |
Host | smart-414f8471-b2ab-4e1a-b04e-6de1005780cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016851322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.1016851322 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2363935963 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 4416410283 ps |
CPU time | 31.06 seconds |
Started | Jul 14 04:59:19 PM PDT 24 |
Finished | Jul 14 04:59:50 PM PDT 24 |
Peak memory | 211496 kb |
Host | smart-b5ae69f3-5283-4936-bff7-53ef9a632f53 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2363935963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2363935963 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1636444137 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 1605526935 ps |
CPU time | 164.63 seconds |
Started | Jul 14 04:59:06 PM PDT 24 |
Finished | Jul 14 05:01:51 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-027c3ef1-2073-45ea-8b09-2fe7a9d17286 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636444137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.1636444137 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2598946329 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 446719346 ps |
CPU time | 57.58 seconds |
Started | Jul 14 04:59:13 PM PDT 24 |
Finished | Jul 14 05:00:11 PM PDT 24 |
Peak memory | 308236 kb |
Host | smart-e71a3bcf-55ac-4903-9ec9-520681686f35 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598946329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2598946329 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1473533809 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 8089830472 ps |
CPU time | 367.92 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 05:05:34 PM PDT 24 |
Peak memory | 319432 kb |
Host | smart-c97ac7bd-46a2-4c05-9faa-43e20f462ec1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473533809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.1473533809 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.1217337521 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 25233806 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:59:35 PM PDT 24 |
Finished | Jul 14 04:59:36 PM PDT 24 |
Peak memory | 202164 kb |
Host | smart-0eed9052-c407-4b8a-b497-8a3097923723 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217337521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1217337521 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.718553565 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 1391596450 ps |
CPU time | 59.23 seconds |
Started | Jul 14 04:59:21 PM PDT 24 |
Finished | Jul 14 05:00:20 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-b12dea6d-79eb-4b97-8dac-8a10a92430e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718553565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 718553565 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.1466251040 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 9493965829 ps |
CPU time | 1465.25 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 05:23:52 PM PDT 24 |
Peak memory | 374648 kb |
Host | smart-d1d56e31-6971-44bf-9a71-cb40913a7d1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466251040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1466251040 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.2312149747 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1062359053 ps |
CPU time | 7.12 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 04:59:34 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-02051169-d685-4de1-88ce-7dbe27b27129 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312149747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.2312149747 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.460604914 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 484572573 ps |
CPU time | 139.22 seconds |
Started | Jul 14 04:59:21 PM PDT 24 |
Finished | Jul 14 05:01:41 PM PDT 24 |
Peak memory | 358640 kb |
Host | smart-e084315d-3619-4867-99c3-725b6bacc4ce |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460604914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.sram_ctrl_max_throughput.460604914 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1428453972 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 301097279 ps |
CPU time | 5.92 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 04:59:33 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-5e5094ad-bf88-4aa6-9be2-5b9e05ab4002 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428453972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.1428453972 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.4175974084 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 343464402 ps |
CPU time | 11.02 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 04:59:38 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-7108428e-0668-4f14-8581-74491afe8efb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175974084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.4175974084 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1449225018 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 10350897816 ps |
CPU time | 914.71 seconds |
Started | Jul 14 04:59:20 PM PDT 24 |
Finished | Jul 14 05:14:35 PM PDT 24 |
Peak memory | 366340 kb |
Host | smart-4d29e84e-880d-47b1-bcf3-6add9967dd42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449225018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1449225018 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.2301894942 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 410170900 ps |
CPU time | 28.13 seconds |
Started | Jul 14 04:59:20 PM PDT 24 |
Finished | Jul 14 04:59:49 PM PDT 24 |
Peak memory | 275084 kb |
Host | smart-b6a3a867-c2da-4b89-aee0-a973c069c6bc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301894942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.2301894942 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3909470156 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 17837736884 ps |
CPU time | 440.79 seconds |
Started | Jul 14 04:59:22 PM PDT 24 |
Finished | Jul 14 05:06:44 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-747fe64a-5a5c-4a3a-99f2-f1ebb2e3fb28 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909470156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.3909470156 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.4162024244 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 32203994 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 04:59:28 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-4d95845a-7e01-4f40-a1c3-fa0b1aced0d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162024244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.4162024244 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.1894455259 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 6028757540 ps |
CPU time | 1922.62 seconds |
Started | Jul 14 04:59:27 PM PDT 24 |
Finished | Jul 14 05:31:30 PM PDT 24 |
Peak memory | 374452 kb |
Host | smart-871c6774-fe5e-45ce-9200-93364b34dab6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894455259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1894455259 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.591903809 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 70618095 ps |
CPU time | 3.93 seconds |
Started | Jul 14 04:59:20 PM PDT 24 |
Finished | Jul 14 04:59:24 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-20f325ed-fe03-4fc2-8c78-ec60c57e10d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591903809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.591903809 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.2507105262 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 8460550549 ps |
CPU time | 118.19 seconds |
Started | Jul 14 04:59:26 PM PDT 24 |
Finished | Jul 14 05:01:24 PM PDT 24 |
Peak memory | 259996 kb |
Host | smart-13119fce-5280-426e-a071-1d91a86b5a56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507105262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.2507105262 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2560264825 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1761260588 ps |
CPU time | 20.07 seconds |
Started | Jul 14 04:59:25 PM PDT 24 |
Finished | Jul 14 04:59:46 PM PDT 24 |
Peak memory | 251548 kb |
Host | smart-c46fabd6-5477-48d2-a931-fa61b8b7f926 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2560264825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2560264825 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.254067068 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2299172793 ps |
CPU time | 191.71 seconds |
Started | Jul 14 04:59:22 PM PDT 24 |
Finished | Jul 14 05:02:34 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-d56227a0-1e66-41ba-b5ac-61e0a0ff0842 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254067068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_stress_pipeline.254067068 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1199656131 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 138373986 ps |
CPU time | 92.08 seconds |
Started | Jul 14 04:59:21 PM PDT 24 |
Finished | Jul 14 05:00:53 PM PDT 24 |
Peak memory | 337624 kb |
Host | smart-e8365dce-5e9b-4edc-956c-458f0b8bb9af |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199656131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1199656131 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.4198214025 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 9948911285 ps |
CPU time | 1239.04 seconds |
Started | Jul 14 04:59:40 PM PDT 24 |
Finished | Jul 14 05:20:19 PM PDT 24 |
Peak memory | 371568 kb |
Host | smart-555c0754-7bcc-4cb4-98b0-cbe2463a8a25 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198214025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.4198214025 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.3501288188 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 22797487 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:59:54 PM PDT 24 |
Finished | Jul 14 04:59:56 PM PDT 24 |
Peak memory | 202132 kb |
Host | smart-d271e68c-1649-4de6-92c7-043f33312656 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501288188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.3501288188 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.3164466405 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 405036496 ps |
CPU time | 26.26 seconds |
Started | Jul 14 04:59:34 PM PDT 24 |
Finished | Jul 14 05:00:01 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-38522fd2-74d0-4a6d-894b-59de7a12982b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164466405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .3164466405 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.1501021259 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 3936147079 ps |
CPU time | 329.77 seconds |
Started | Jul 14 04:59:41 PM PDT 24 |
Finished | Jul 14 05:05:11 PM PDT 24 |
Peak memory | 366352 kb |
Host | smart-3dd11193-97d0-45fe-8b95-f707fd510304 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501021259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1501021259 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.2115938334 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 469488958 ps |
CPU time | 4.94 seconds |
Started | Jul 14 04:59:41 PM PDT 24 |
Finished | Jul 14 04:59:47 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-21cb3c25-a360-421b-a488-6efa04267dbb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115938334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.2115938334 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1629513367 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 102867783 ps |
CPU time | 47.08 seconds |
Started | Jul 14 04:59:42 PM PDT 24 |
Finished | Jul 14 05:00:30 PM PDT 24 |
Peak memory | 290896 kb |
Host | smart-ba3910c5-0f33-42cd-acb3-504def8e3bd1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629513367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1629513367 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2368904625 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 204046999 ps |
CPU time | 3.61 seconds |
Started | Jul 14 04:59:54 PM PDT 24 |
Finished | Jul 14 04:59:59 PM PDT 24 |
Peak memory | 210936 kb |
Host | smart-1533a8d0-646c-4983-9181-a4570f6227df |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368904625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2368904625 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.853211106 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 2373506176 ps |
CPU time | 7.04 seconds |
Started | Jul 14 04:59:55 PM PDT 24 |
Finished | Jul 14 05:00:02 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-74b7c28e-fa6f-4136-9b6a-80db7243229d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853211106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.853211106 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.834902428 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 2512596817 ps |
CPU time | 712.46 seconds |
Started | Jul 14 04:59:35 PM PDT 24 |
Finished | Jul 14 05:11:29 PM PDT 24 |
Peak memory | 374032 kb |
Host | smart-d3e87d89-0b5b-4c46-8b7a-26edaa9c4182 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834902428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.834902428 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.134805452 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2237180522 ps |
CPU time | 11.18 seconds |
Started | Jul 14 04:59:36 PM PDT 24 |
Finished | Jul 14 04:59:48 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-e465a874-738f-41d6-862b-a43ad98556b5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134805452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s ram_ctrl_partial_access.134805452 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4105504290 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 3833917703 ps |
CPU time | 291.3 seconds |
Started | Jul 14 04:59:34 PM PDT 24 |
Finished | Jul 14 05:04:26 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-13f11f00-b892-4c14-8c3a-3fda6261ed48 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105504290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.4105504290 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.4173813802 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 28055936 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:59:49 PM PDT 24 |
Finished | Jul 14 04:59:50 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-7336ff78-c376-4156-8235-70d27c1c1989 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173813802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.4173813802 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.151529366 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1528006286 ps |
CPU time | 211.44 seconds |
Started | Jul 14 04:59:40 PM PDT 24 |
Finished | Jul 14 05:03:12 PM PDT 24 |
Peak memory | 334668 kb |
Host | smart-bf5eb9dd-ba9a-4730-b64e-b6c50405709b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151529366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.151529366 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3350040914 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 3780980119 ps |
CPU time | 170.46 seconds |
Started | Jul 14 04:59:34 PM PDT 24 |
Finished | Jul 14 05:02:25 PM PDT 24 |
Peak memory | 367504 kb |
Host | smart-3eccc7d3-488a-4db8-b5f0-52d0b422a3b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350040914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3350040914 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.2382992445 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 4741369057 ps |
CPU time | 2048.9 seconds |
Started | Jul 14 04:59:54 PM PDT 24 |
Finished | Jul 14 05:34:04 PM PDT 24 |
Peak memory | 375268 kb |
Host | smart-abbc2b43-6b4a-450b-bf31-27bce364d508 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382992445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.2382992445 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3556679750 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 4224663713 ps |
CPU time | 254.85 seconds |
Started | Jul 14 04:59:56 PM PDT 24 |
Finished | Jul 14 05:04:11 PM PDT 24 |
Peak memory | 373756 kb |
Host | smart-17f60b3e-2c66-4960-95c9-014e2e22a609 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3556679750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3556679750 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2217238150 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 49177889927 ps |
CPU time | 270 seconds |
Started | Jul 14 04:59:35 PM PDT 24 |
Finished | Jul 14 05:04:06 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-4cc857b6-eec1-4f61-acce-cb1ef8b838a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217238150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.2217238150 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4148292032 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 77164645 ps |
CPU time | 11.85 seconds |
Started | Jul 14 04:59:40 PM PDT 24 |
Finished | Jul 14 04:59:52 PM PDT 24 |
Peak memory | 244688 kb |
Host | smart-db7a311a-ddb8-421b-9715-017550656742 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148292032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4148292032 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3880740967 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 20742129574 ps |
CPU time | 1155.53 seconds |
Started | Jul 14 05:00:13 PM PDT 24 |
Finished | Jul 14 05:19:29 PM PDT 24 |
Peak memory | 373232 kb |
Host | smart-abaf95e0-7889-48e0-9cc1-ac1b646c52c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880740967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.3880740967 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.2787539592 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 44616998 ps |
CPU time | 0.65 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:00:19 PM PDT 24 |
Peak memory | 202168 kb |
Host | smart-f1ccd4b3-6a68-4bec-81b7-6be162219f2f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787539592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.2787539592 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.2856639636 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 4506295809 ps |
CPU time | 72.52 seconds |
Started | Jul 14 05:00:03 PM PDT 24 |
Finished | Jul 14 05:01:16 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-96b6be00-a5a4-43f4-a51c-b5b9ad24ec58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856639636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .2856639636 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.3913125859 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 5368987064 ps |
CPU time | 565.33 seconds |
Started | Jul 14 05:00:12 PM PDT 24 |
Finished | Jul 14 05:09:37 PM PDT 24 |
Peak memory | 371336 kb |
Host | smart-c807db00-260c-4360-936c-d69152ce2433 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913125859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3913125859 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.1859250185 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 8447950376 ps |
CPU time | 7.17 seconds |
Started | Jul 14 05:00:09 PM PDT 24 |
Finished | Jul 14 05:00:17 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-d11dca99-ec5c-4296-8b66-4d560ed27899 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859250185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.1859250185 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.2971477196 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 105067086 ps |
CPU time | 5.18 seconds |
Started | Jul 14 05:00:02 PM PDT 24 |
Finished | Jul 14 05:00:07 PM PDT 24 |
Peak memory | 235028 kb |
Host | smart-83733d12-53e6-48a7-8bdd-5fa42f8eea63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971477196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.2971477196 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1594243704 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 462606285 ps |
CPU time | 3.42 seconds |
Started | Jul 14 05:00:18 PM PDT 24 |
Finished | Jul 14 05:00:22 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-7f526fcc-cca6-455b-bea4-b2072537de62 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594243704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.1594243704 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.3239311557 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 1617822450 ps |
CPU time | 11.5 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:00:29 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-13207213-5707-4ba7-8a5b-15011fa9aab1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239311557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3239311557 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.2487954470 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 19652480249 ps |
CPU time | 1497.68 seconds |
Started | Jul 14 05:00:02 PM PDT 24 |
Finished | Jul 14 05:25:01 PM PDT 24 |
Peak memory | 374680 kb |
Host | smart-cc7a1e8c-6776-421c-9fb6-762426a642dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487954470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.2487954470 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.3553434823 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 393944280 ps |
CPU time | 11.66 seconds |
Started | Jul 14 05:00:03 PM PDT 24 |
Finished | Jul 14 05:00:15 PM PDT 24 |
Peak memory | 239056 kb |
Host | smart-1725b08e-966e-4011-a2b8-9c116dbc84bb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553434823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.3553434823 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.4179623179 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 35976258537 ps |
CPU time | 333.04 seconds |
Started | Jul 14 05:00:04 PM PDT 24 |
Finished | Jul 14 05:05:38 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-f8c2fd45-796c-4f91-8a09-5597249467a8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179623179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.4179623179 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.1030554816 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 28231059 ps |
CPU time | 0.79 seconds |
Started | Jul 14 05:00:12 PM PDT 24 |
Finished | Jul 14 05:00:13 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-b119099d-420e-44a3-abc5-3810280bd299 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030554816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1030554816 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.2161293646 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 11115700263 ps |
CPU time | 789.73 seconds |
Started | Jul 14 05:00:10 PM PDT 24 |
Finished | Jul 14 05:13:20 PM PDT 24 |
Peak memory | 370044 kb |
Host | smart-22613b22-47a2-48f9-9af9-337da6e55207 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161293646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2161293646 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.1229997241 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 148439381 ps |
CPU time | 2.18 seconds |
Started | Jul 14 05:00:02 PM PDT 24 |
Finished | Jul 14 05:00:05 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-761d9b17-23e0-4072-9dd0-a4b8562f008b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229997241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1229997241 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.893628423 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 13935594008 ps |
CPU time | 407.48 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:07:06 PM PDT 24 |
Peak memory | 366592 kb |
Host | smart-6e8108d3-51af-4466-a6c9-2ddae6dc5e16 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=893628423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.893628423 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3174495412 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 2331833447 ps |
CPU time | 222.05 seconds |
Started | Jul 14 05:00:03 PM PDT 24 |
Finished | Jul 14 05:03:45 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-b7c2ed0b-5a43-4e7f-9041-046b479159a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174495412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.3174495412 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1208212862 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 1134479652 ps |
CPU time | 82.15 seconds |
Started | Jul 14 05:00:03 PM PDT 24 |
Finished | Jul 14 05:01:26 PM PDT 24 |
Peak memory | 321240 kb |
Host | smart-0d910dda-90bd-41e5-badf-5fbd737235e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208212862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1208212862 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2208777202 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 405343733 ps |
CPU time | 78.66 seconds |
Started | Jul 14 05:00:27 PM PDT 24 |
Finished | Jul 14 05:01:46 PM PDT 24 |
Peak memory | 314192 kb |
Host | smart-54fca650-4722-4f27-bae2-4bc6397ff97a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208777202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.2208777202 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.4160875915 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 48070047 ps |
CPU time | 0.63 seconds |
Started | Jul 14 05:00:31 PM PDT 24 |
Finished | Jul 14 05:00:32 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-f1dacda2-be00-4018-b5ad-db05be288432 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160875915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.4160875915 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.3916413740 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 2646945841 ps |
CPU time | 44.99 seconds |
Started | Jul 14 05:00:19 PM PDT 24 |
Finished | Jul 14 05:01:04 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-e3fa46b6-baf8-4156-af7b-73ef1cf9fc52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916413740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .3916413740 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.362263172 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 6541085237 ps |
CPU time | 410.37 seconds |
Started | Jul 14 05:00:22 PM PDT 24 |
Finished | Jul 14 05:07:13 PM PDT 24 |
Peak memory | 370620 kb |
Host | smart-6a19ee8b-cc2c-412d-a058-7e461ab18add |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362263172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl e.362263172 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.660070709 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 661372650 ps |
CPU time | 9.35 seconds |
Started | Jul 14 05:00:23 PM PDT 24 |
Finished | Jul 14 05:00:32 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-9ed2722f-83fc-4317-be4d-45daefcd0e9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660070709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc alation.660070709 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.4202752919 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 472196293 ps |
CPU time | 103.15 seconds |
Started | Jul 14 05:00:18 PM PDT 24 |
Finished | Jul 14 05:02:01 PM PDT 24 |
Peak memory | 347004 kb |
Host | smart-1bbecb36-4f6b-400e-92ec-10cc346ccf2c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202752919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.4202752919 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.849837090 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 191030659 ps |
CPU time | 5.83 seconds |
Started | Jul 14 05:00:31 PM PDT 24 |
Finished | Jul 14 05:00:37 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-03170933-5a37-4f6c-b867-1a7f46b1eec7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849837090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.849837090 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.3190484774 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 613747853 ps |
CPU time | 9.83 seconds |
Started | Jul 14 05:00:23 PM PDT 24 |
Finished | Jul 14 05:00:33 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-d288eea5-2c7b-4b0b-9b75-3df36551eca8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190484774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.3190484774 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.1965578442 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 9957766121 ps |
CPU time | 648.82 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:11:06 PM PDT 24 |
Peak memory | 364536 kb |
Host | smart-023772eb-f9ea-49c1-8a61-50a7cfbb8f15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965578442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.1965578442 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.495056051 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 233035261 ps |
CPU time | 15.32 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:00:33 PM PDT 24 |
Peak memory | 250456 kb |
Host | smart-5479de86-5e39-4e2a-814b-b9edd26bf2d5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495056051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s ram_ctrl_partial_access.495056051 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.309680034 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 16170177287 ps |
CPU time | 390.62 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:06:48 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-75a34b42-5243-4864-a006-3295191c066c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309680034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.sram_ctrl_partial_access_b2b.309680034 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2213074335 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 27695253 ps |
CPU time | 0.77 seconds |
Started | Jul 14 05:00:24 PM PDT 24 |
Finished | Jul 14 05:00:25 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-53731111-37d3-459d-9e6a-3481f56103d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213074335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2213074335 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.1567246864 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 23562360817 ps |
CPU time | 765.93 seconds |
Started | Jul 14 05:00:25 PM PDT 24 |
Finished | Jul 14 05:13:11 PM PDT 24 |
Peak memory | 374572 kb |
Host | smart-463c0f44-e68b-4720-8037-1c71673bae99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567246864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1567246864 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.2514048337 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 662000409 ps |
CPU time | 156.12 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:02:54 PM PDT 24 |
Peak memory | 365004 kb |
Host | smart-b8c89468-3e91-4c14-a659-b48e31a81dcc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514048337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2514048337 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.611288449 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 2666920460 ps |
CPU time | 1042.92 seconds |
Started | Jul 14 05:00:33 PM PDT 24 |
Finished | Jul 14 05:17:56 PM PDT 24 |
Peak memory | 379908 kb |
Host | smart-3cbc36a3-a709-42dd-9738-50372af23a44 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=611288449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.611288449 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1862410970 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1416246095 ps |
CPU time | 138.67 seconds |
Started | Jul 14 05:00:17 PM PDT 24 |
Finished | Jul 14 05:02:36 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-2a1c4f1e-0dba-45e6-8766-60aff4f9aadb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862410970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1862410970 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4177654938 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 1189148680 ps |
CPU time | 109.65 seconds |
Started | Jul 14 05:00:23 PM PDT 24 |
Finished | Jul 14 05:02:13 PM PDT 24 |
Peak memory | 348004 kb |
Host | smart-53160a81-a572-407f-baf8-0f7938bb9415 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177654938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.4177654938 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.904953584 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 9656619065 ps |
CPU time | 895.5 seconds |
Started | Jul 14 05:00:40 PM PDT 24 |
Finished | Jul 14 05:15:37 PM PDT 24 |
Peak memory | 373376 kb |
Host | smart-b31fc703-0804-4c66-bf8e-99b4606c727e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904953584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 38.sram_ctrl_access_during_key_req.904953584 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.3310592363 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 14945573 ps |
CPU time | 0.66 seconds |
Started | Jul 14 05:00:46 PM PDT 24 |
Finished | Jul 14 05:00:47 PM PDT 24 |
Peak memory | 202468 kb |
Host | smart-311204cf-ff3c-4c30-9bcd-6dc936ace03b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310592363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3310592363 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.3980755116 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 45475936406 ps |
CPU time | 83.32 seconds |
Started | Jul 14 05:00:31 PM PDT 24 |
Finished | Jul 14 05:01:55 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-81db4e9d-8473-4830-b3dc-b63294d0d613 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980755116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .3980755116 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.1710447683 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 13640469898 ps |
CPU time | 679.25 seconds |
Started | Jul 14 05:00:43 PM PDT 24 |
Finished | Jul 14 05:12:03 PM PDT 24 |
Peak memory | 375272 kb |
Host | smart-1bb05947-2cb1-4dba-abc2-a6c73b408fde |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710447683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1710447683 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.2944626220 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 6938938826 ps |
CPU time | 8.26 seconds |
Started | Jul 14 05:00:42 PM PDT 24 |
Finished | Jul 14 05:00:51 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-1f987490-6363-4e48-907b-ed02f29a9d89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944626220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2944626220 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.3781647068 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 92745786 ps |
CPU time | 22.75 seconds |
Started | Jul 14 05:00:38 PM PDT 24 |
Finished | Jul 14 05:01:01 PM PDT 24 |
Peak memory | 271256 kb |
Host | smart-9edc2058-e384-491d-9799-0e5296cce0aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781647068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.3781647068 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.675484671 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 606905330 ps |
CPU time | 5.03 seconds |
Started | Jul 14 05:00:43 PM PDT 24 |
Finished | Jul 14 05:00:48 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-a15b10f4-7e19-4e90-ad6f-960240edc169 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675484671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_mem_partial_access.675484671 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.1311715653 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 880931846 ps |
CPU time | 11.36 seconds |
Started | Jul 14 05:00:37 PM PDT 24 |
Finished | Jul 14 05:00:49 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-cdeffacb-101d-4161-b40c-ad2283b9b7fb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311715653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1311715653 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.1723770551 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 254360834 ps |
CPU time | 22.2 seconds |
Started | Jul 14 05:00:32 PM PDT 24 |
Finished | Jul 14 05:00:54 PM PDT 24 |
Peak memory | 230572 kb |
Host | smart-4f0d3f9e-b56d-4b40-b84e-ee1d67f3ede9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723770551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.1723770551 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.208701502 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 186765264 ps |
CPU time | 98.02 seconds |
Started | Jul 14 05:00:32 PM PDT 24 |
Finished | Jul 14 05:02:10 PM PDT 24 |
Peak memory | 346704 kb |
Host | smart-9319077c-9777-4d2f-8e19-89d6f317d2e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208701502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s ram_ctrl_partial_access.208701502 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1877990988 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 16016214629 ps |
CPU time | 432.16 seconds |
Started | Jul 14 05:00:31 PM PDT 24 |
Finished | Jul 14 05:07:44 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-14a8ec59-8344-4ce3-bafc-7f8067a4c1c3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877990988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.1877990988 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.1194187654 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 88752675 ps |
CPU time | 0.8 seconds |
Started | Jul 14 05:00:38 PM PDT 24 |
Finished | Jul 14 05:00:39 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-bf2cd506-fd0b-4825-a7b2-55a4d847a975 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194187654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1194187654 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.1761584766 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 55668585484 ps |
CPU time | 964.82 seconds |
Started | Jul 14 05:00:39 PM PDT 24 |
Finished | Jul 14 05:16:44 PM PDT 24 |
Peak memory | 366440 kb |
Host | smart-06715954-8b7d-4ed4-ae87-883fc7e0f5cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761584766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1761584766 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.370930898 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 816458238 ps |
CPU time | 12.37 seconds |
Started | Jul 14 05:00:33 PM PDT 24 |
Finished | Jul 14 05:00:45 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-e955b6e8-656e-4ff5-bb49-23385da8d68e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370930898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.370930898 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.1548266774 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 12425253129 ps |
CPU time | 4367.17 seconds |
Started | Jul 14 05:00:47 PM PDT 24 |
Finished | Jul 14 06:13:35 PM PDT 24 |
Peak memory | 375388 kb |
Host | smart-c13e3461-813c-40b7-afcb-4746c3f5e744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548266774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.1548266774 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1006146102 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 634933194 ps |
CPU time | 7.35 seconds |
Started | Jul 14 05:00:46 PM PDT 24 |
Finished | Jul 14 05:00:54 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-86cad716-a076-4d48-a087-6bcae31f201f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1006146102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1006146102 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.493373048 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 4133427164 ps |
CPU time | 328.24 seconds |
Started | Jul 14 05:00:32 PM PDT 24 |
Finished | Jul 14 05:06:01 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-3872818c-6cdb-42c4-ad65-007316f8a519 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493373048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_stress_pipeline.493373048 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2578082627 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 414730597 ps |
CPU time | 33.66 seconds |
Started | Jul 14 05:00:43 PM PDT 24 |
Finished | Jul 14 05:01:17 PM PDT 24 |
Peak memory | 300492 kb |
Host | smart-0f2de9f8-08dd-49f2-a7a5-96e25d37f4d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578082627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2578082627 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3744318647 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 818282659 ps |
CPU time | 193.79 seconds |
Started | Jul 14 05:00:54 PM PDT 24 |
Finished | Jul 14 05:04:09 PM PDT 24 |
Peak memory | 371140 kb |
Host | smart-62110575-2c9f-4a50-aa45-f0706edfc5f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744318647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.3744318647 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.960258780 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 22048761 ps |
CPU time | 0.7 seconds |
Started | Jul 14 05:01:03 PM PDT 24 |
Finished | Jul 14 05:01:04 PM PDT 24 |
Peak memory | 202524 kb |
Host | smart-f1fc95e6-77fa-421c-b5ed-dc2485584228 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960258780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.960258780 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.861842222 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 3562946253 ps |
CPU time | 68.37 seconds |
Started | Jul 14 05:00:53 PM PDT 24 |
Finished | Jul 14 05:02:02 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-a1f4a142-75ad-4e6d-98d5-3daab43f4852 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861842222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection. 861842222 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.2857864498 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 7965035304 ps |
CPU time | 321.53 seconds |
Started | Jul 14 05:00:54 PM PDT 24 |
Finished | Jul 14 05:06:16 PM PDT 24 |
Peak memory | 341064 kb |
Host | smart-1ce74fe6-3d25-44ff-8efc-1b4ad6e7dfd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857864498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2857864498 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.2056163349 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 178088457 ps |
CPU time | 2.44 seconds |
Started | Jul 14 05:00:54 PM PDT 24 |
Finished | Jul 14 05:00:57 PM PDT 24 |
Peak memory | 210944 kb |
Host | smart-d65e6bbd-cf2a-45c2-b077-d7a782a46391 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056163349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.2056163349 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.2472405203 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 1056840760 ps |
CPU time | 142.02 seconds |
Started | Jul 14 05:00:54 PM PDT 24 |
Finished | Jul 14 05:03:17 PM PDT 24 |
Peak memory | 368284 kb |
Host | smart-7f3fa8ea-eb00-48b6-88ba-08823e26d58c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472405203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2472405203 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.1392442413 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 659518339 ps |
CPU time | 12.21 seconds |
Started | Jul 14 05:01:04 PM PDT 24 |
Finished | Jul 14 05:01:17 PM PDT 24 |
Peak memory | 210936 kb |
Host | smart-ef84da29-2bae-44c3-b7e5-ed457729541c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392442413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.1392442413 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.2314928570 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 18836260210 ps |
CPU time | 1618.57 seconds |
Started | Jul 14 05:00:54 PM PDT 24 |
Finished | Jul 14 05:27:53 PM PDT 24 |
Peak memory | 372552 kb |
Host | smart-96d82d1d-edc3-48ee-b016-26ca8f62183a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314928570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.2314928570 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.3706031480 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 333659025 ps |
CPU time | 18.11 seconds |
Started | Jul 14 05:00:53 PM PDT 24 |
Finished | Jul 14 05:01:12 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-e6ff170d-8229-419f-83a6-e178eeacab41 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706031480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.3706031480 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.104681547 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 103845032304 ps |
CPU time | 308.72 seconds |
Started | Jul 14 05:00:54 PM PDT 24 |
Finished | Jul 14 05:06:04 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-519c5d64-794b-48be-b553-e20c00d3f62b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104681547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.104681547 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.1418723832 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 27707116 ps |
CPU time | 0.86 seconds |
Started | Jul 14 05:01:02 PM PDT 24 |
Finished | Jul 14 05:01:04 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-b2d028ea-4549-4fa7-bb7b-f64bca02a6c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418723832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1418723832 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.3923316622 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 23766567383 ps |
CPU time | 1481.31 seconds |
Started | Jul 14 05:00:52 PM PDT 24 |
Finished | Jul 14 05:25:34 PM PDT 24 |
Peak memory | 368472 kb |
Host | smart-1b1bccdd-4219-4eed-984a-44570101cf5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923316622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3923316622 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.2264095884 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1888125236 ps |
CPU time | 8.72 seconds |
Started | Jul 14 05:00:45 PM PDT 24 |
Finished | Jul 14 05:00:54 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-8eb79b06-e6ca-4426-a08c-c3423a3e520c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264095884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2264095884 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.2643327307 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 126784821070 ps |
CPU time | 2110.06 seconds |
Started | Jul 14 05:01:05 PM PDT 24 |
Finished | Jul 14 05:36:16 PM PDT 24 |
Peak memory | 376732 kb |
Host | smart-e35837fd-7afa-43a8-a23e-f3215fa5885d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643327307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2643327307 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4190886667 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 2109526252 ps |
CPU time | 950.83 seconds |
Started | Jul 14 05:01:03 PM PDT 24 |
Finished | Jul 14 05:16:54 PM PDT 24 |
Peak memory | 372568 kb |
Host | smart-f06ef8ce-fd20-40fe-9b15-8991e4d6d490 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4190886667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.4190886667 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1212116506 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2502551810 ps |
CPU time | 113.76 seconds |
Started | Jul 14 05:00:55 PM PDT 24 |
Finished | Jul 14 05:02:49 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-0421b377-deae-451c-b86a-16de7fcb20c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212116506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1212116506 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.119568518 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 811154139 ps |
CPU time | 167.21 seconds |
Started | Jul 14 05:00:53 PM PDT 24 |
Finished | Jul 14 05:03:41 PM PDT 24 |
Peak memory | 370068 kb |
Host | smart-00c6fbfa-7637-42d9-9372-606823007654 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119568518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.119568518 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.872854975 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 3832047722 ps |
CPU time | 1027.96 seconds |
Started | Jul 14 04:54:11 PM PDT 24 |
Finished | Jul 14 05:11:20 PM PDT 24 |
Peak memory | 368532 kb |
Host | smart-7cb81aa9-80d5-40a8-a101-59aa050960d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872854975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_access_during_key_req.872854975 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.688318175 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 12956998 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:15 PM PDT 24 |
Peak memory | 202528 kb |
Host | smart-5e6abad0-b2f6-452b-b98a-f230a4f7feba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688318175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.688318175 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.3089508816 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 883946570 ps |
CPU time | 56.41 seconds |
Started | Jul 14 04:54:10 PM PDT 24 |
Finished | Jul 14 04:55:07 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-c1d26bb2-a613-4928-a311-3ef86dad62ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089508816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 3089508816 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.362656256 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 22261123937 ps |
CPU time | 1049.87 seconds |
Started | Jul 14 04:54:17 PM PDT 24 |
Finished | Jul 14 05:11:48 PM PDT 24 |
Peak memory | 375340 kb |
Host | smart-590c2e8a-25d9-4366-9397-69d74370f8b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362656256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable .362656256 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.3511739248 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 1358300574 ps |
CPU time | 6.89 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:23 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-02bbe9f9-c6fa-46e4-85ad-37b560977ab9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511739248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.3511739248 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.1041936194 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 53612765 ps |
CPU time | 3.8 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:20 PM PDT 24 |
Peak memory | 222244 kb |
Host | smart-535d6516-6dfe-4b6f-86ce-e11216962598 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041936194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1041936194 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2380748001 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 346676190 ps |
CPU time | 3.3 seconds |
Started | Jul 14 04:54:17 PM PDT 24 |
Finished | Jul 14 04:54:21 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-59f7d364-f82a-4abe-a4f9-3188ff92d461 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380748001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2380748001 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.2663578900 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 347378064 ps |
CPU time | 6.49 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:22 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-67524fcc-7ffb-4679-9bab-7591c2d81711 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663578900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2663578900 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.477642862 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 14735740302 ps |
CPU time | 977.8 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 05:10:34 PM PDT 24 |
Peak memory | 374600 kb |
Host | smart-e7f22236-90d8-4ce2-b6d4-8e653355b7ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477642862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.477642862 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.2708331668 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 138377658 ps |
CPU time | 39.49 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 04:55:05 PM PDT 24 |
Peak memory | 295748 kb |
Host | smart-854dd8da-28f5-4c28-80a0-3ce4203414dd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708331668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2708331668 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1233020871 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 7691455304 ps |
CPU time | 285.52 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:59:02 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-2f61ef42-0b7b-43d3-80d2-ac14c1da04bd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233020871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.1233020871 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.1217981357 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 50279987 ps |
CPU time | 0.77 seconds |
Started | Jul 14 04:54:11 PM PDT 24 |
Finished | Jul 14 04:54:12 PM PDT 24 |
Peak memory | 202740 kb |
Host | smart-e173d643-c560-45fc-8bb8-459ff33a981d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217981357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1217981357 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.3936849633 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 10022899799 ps |
CPU time | 1659.35 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 05:21:56 PM PDT 24 |
Peak memory | 370504 kb |
Host | smart-693d0d60-9fc2-4456-ad13-024086abf876 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936849633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3936849633 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.669246928 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 105263278 ps |
CPU time | 67.26 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 04:55:33 PM PDT 24 |
Peak memory | 327536 kb |
Host | smart-a70892b1-a955-4dde-a5b6-3c3f3df705e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669246928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.669246928 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.3099612444 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 27182170102 ps |
CPU time | 3739.7 seconds |
Started | Jul 14 04:54:17 PM PDT 24 |
Finished | Jul 14 05:56:38 PM PDT 24 |
Peak memory | 376716 kb |
Host | smart-0f83dfc0-02f5-4670-b7bd-5431dc91e188 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099612444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.3099612444 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3753540227 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 33211368106 ps |
CPU time | 67.1 seconds |
Started | Jul 14 04:54:11 PM PDT 24 |
Finished | Jul 14 04:55:18 PM PDT 24 |
Peak memory | 212220 kb |
Host | smart-039ca483-dd36-41c4-a793-d55a11ea33b7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3753540227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3753540227 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3928877117 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 3411123682 ps |
CPU time | 329.85 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:59:45 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-2f5bb1b2-aeff-4cd3-86ec-8e6b44e554b4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928877117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3928877117 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3090198409 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 285724164 ps |
CPU time | 5.58 seconds |
Started | Jul 14 04:54:13 PM PDT 24 |
Finished | Jul 14 04:54:20 PM PDT 24 |
Peak memory | 227700 kb |
Host | smart-a7b0595d-44fc-403a-86cf-a78336b44d5d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090198409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3090198409 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.557001651 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 8049200218 ps |
CPU time | 746.65 seconds |
Started | Jul 14 05:01:11 PM PDT 24 |
Finished | Jul 14 05:13:38 PM PDT 24 |
Peak memory | 370776 kb |
Host | smart-45987023-da3f-494d-894b-d0d227b23236 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557001651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.sram_ctrl_access_during_key_req.557001651 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.4267335890 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 16032500 ps |
CPU time | 0.67 seconds |
Started | Jul 14 05:01:23 PM PDT 24 |
Finished | Jul 14 05:01:24 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-9ba2ec5e-f01a-4999-9fa8-a8345b14ee14 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267335890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.4267335890 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.3898886998 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 874055544 ps |
CPU time | 20.08 seconds |
Started | Jul 14 05:01:03 PM PDT 24 |
Finished | Jul 14 05:01:23 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-c63b33e3-86ab-440a-900f-357ada924899 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898886998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .3898886998 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.1889085197 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 33671857627 ps |
CPU time | 998.24 seconds |
Started | Jul 14 05:01:10 PM PDT 24 |
Finished | Jul 14 05:17:48 PM PDT 24 |
Peak memory | 366072 kb |
Host | smart-21242c5a-3574-4d82-9ada-04f753781b14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889085197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.1889085197 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.2679121924 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 863451188 ps |
CPU time | 8.32 seconds |
Started | Jul 14 05:01:12 PM PDT 24 |
Finished | Jul 14 05:01:20 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-d330ea0f-3423-4151-9c4f-8d3906a2ed0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679121924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.2679121924 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.3756427971 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 82978832 ps |
CPU time | 14.21 seconds |
Started | Jul 14 05:01:09 PM PDT 24 |
Finished | Jul 14 05:01:24 PM PDT 24 |
Peak memory | 251768 kb |
Host | smart-588240b8-c4f0-4c24-8b07-3e6172ca322d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756427971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.3756427971 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.662425278 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 732611945 ps |
CPU time | 6.33 seconds |
Started | Jul 14 05:01:24 PM PDT 24 |
Finished | Jul 14 05:01:31 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-e6cea340-0165-4af8-bb66-0e01a3c9427e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662425278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.662425278 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.2531526860 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 570071401 ps |
CPU time | 5.98 seconds |
Started | Jul 14 05:01:16 PM PDT 24 |
Finished | Jul 14 05:01:23 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-8962d352-fa93-43e8-90cb-92516b9689a5 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531526860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.2531526860 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.994330047 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 10672775959 ps |
CPU time | 1370.07 seconds |
Started | Jul 14 05:01:04 PM PDT 24 |
Finished | Jul 14 05:23:54 PM PDT 24 |
Peak memory | 373648 kb |
Host | smart-be9396bd-17b3-4d6d-ae0a-bc4615e44f65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994330047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip le_keys.994330047 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.575326310 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 8651695722 ps |
CPU time | 73.83 seconds |
Started | Jul 14 05:01:09 PM PDT 24 |
Finished | Jul 14 05:02:23 PM PDT 24 |
Peak memory | 307528 kb |
Host | smart-3b51e3d0-4e10-4051-8736-b4cb7767ad65 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575326310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.575326310 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2102005459 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 14743686877 ps |
CPU time | 172.69 seconds |
Started | Jul 14 05:01:10 PM PDT 24 |
Finished | Jul 14 05:04:03 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-a1c139f0-2b30-4256-8d17-5d86a49d7e1e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102005459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.2102005459 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.944263951 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 104057120 ps |
CPU time | 0.76 seconds |
Started | Jul 14 05:01:15 PM PDT 24 |
Finished | Jul 14 05:01:16 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-6911e40e-2ecb-4b9e-be74-d3a486354c9d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944263951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.944263951 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.2046314077 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2431453198 ps |
CPU time | 1494.13 seconds |
Started | Jul 14 05:01:17 PM PDT 24 |
Finished | Jul 14 05:26:11 PM PDT 24 |
Peak memory | 365912 kb |
Host | smart-3fb67827-8fc5-4eaf-8f1d-e6f340d60469 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046314077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2046314077 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.3145827465 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 707365429 ps |
CPU time | 110.21 seconds |
Started | Jul 14 05:01:02 PM PDT 24 |
Finished | Jul 14 05:02:53 PM PDT 24 |
Peak memory | 361948 kb |
Host | smart-d4a6b690-4a04-4941-869f-c63b2b188c94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145827465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3145827465 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.4073371797 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 8853761225 ps |
CPU time | 488.33 seconds |
Started | Jul 14 05:01:23 PM PDT 24 |
Finished | Jul 14 05:09:31 PM PDT 24 |
Peak memory | 381016 kb |
Host | smart-4a0293de-13b8-414f-ba77-ec9e4bf8d8a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073371797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.4073371797 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2886322793 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 10812749237 ps |
CPU time | 1172.69 seconds |
Started | Jul 14 05:01:23 PM PDT 24 |
Finished | Jul 14 05:20:57 PM PDT 24 |
Peak memory | 379920 kb |
Host | smart-92f0b148-a74a-4a96-842a-c9f3e39de04c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2886322793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2886322793 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1213772833 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 29344144142 ps |
CPU time | 335.23 seconds |
Started | Jul 14 05:01:12 PM PDT 24 |
Finished | Jul 14 05:06:48 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-b1915b61-2c6e-4a08-bdc8-57688f47064b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213772833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1213772833 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1668391276 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 147692512 ps |
CPU time | 1.46 seconds |
Started | Jul 14 05:01:08 PM PDT 24 |
Finished | Jul 14 05:01:10 PM PDT 24 |
Peak memory | 210928 kb |
Host | smart-8abf80b8-2969-49af-af07-8e9385e70507 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668391276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1668391276 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3269139927 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 11270797683 ps |
CPU time | 1052.3 seconds |
Started | Jul 14 05:01:28 PM PDT 24 |
Finished | Jul 14 05:19:01 PM PDT 24 |
Peak memory | 372568 kb |
Host | smart-f8417d93-65a0-4168-ae88-a4aa4216db41 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269139927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3269139927 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.1822622873 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 1497867879 ps |
CPU time | 33.37 seconds |
Started | Jul 14 05:01:29 PM PDT 24 |
Finished | Jul 14 05:02:03 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-8f77bdca-aeeb-43eb-8fec-6cb318a5cbc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822622873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1822622873 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.855276480 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 681869325 ps |
CPU time | 400.29 seconds |
Started | Jul 14 05:01:29 PM PDT 24 |
Finished | Jul 14 05:08:10 PM PDT 24 |
Peak memory | 371440 kb |
Host | smart-3a70dc52-b6f9-4400-a733-7d021b192c3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855276480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl e.855276480 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.2694540346 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 2007146323 ps |
CPU time | 3.68 seconds |
Started | Jul 14 05:01:29 PM PDT 24 |
Finished | Jul 14 05:01:33 PM PDT 24 |
Peak memory | 210896 kb |
Host | smart-dde8450f-d081-454d-9725-85147094b0b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694540346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.2694540346 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.3941734465 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 983713359 ps |
CPU time | 6.45 seconds |
Started | Jul 14 05:01:31 PM PDT 24 |
Finished | Jul 14 05:01:38 PM PDT 24 |
Peak memory | 235224 kb |
Host | smart-9a26196b-c498-49d5-b7e0-273f7d1a4401 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941734465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3941734465 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1440408300 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 236092073 ps |
CPU time | 3.1 seconds |
Started | Jul 14 05:01:42 PM PDT 24 |
Finished | Jul 14 05:01:45 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-428af8f6-f433-4c93-9536-bf48a58f849b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440408300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.1440408300 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.3531257337 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 2114392908 ps |
CPU time | 10.93 seconds |
Started | Jul 14 05:01:43 PM PDT 24 |
Finished | Jul 14 05:01:54 PM PDT 24 |
Peak memory | 210876 kb |
Host | smart-f6b2f2e9-4261-41b9-b2ee-8b17e9501dc7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531257337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.3531257337 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.3207902524 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 1827237531 ps |
CPU time | 341.45 seconds |
Started | Jul 14 05:01:28 PM PDT 24 |
Finished | Jul 14 05:07:09 PM PDT 24 |
Peak memory | 333648 kb |
Host | smart-191340aa-742f-46dc-b7de-f343eacba55e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207902524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.3207902524 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.2279533876 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 97732709 ps |
CPU time | 5.05 seconds |
Started | Jul 14 05:01:31 PM PDT 24 |
Finished | Jul 14 05:01:36 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-94ac4f06-c269-46d4-a68d-0144072c4c2f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279533876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2279533876 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3438315723 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 2974974054 ps |
CPU time | 200.42 seconds |
Started | Jul 14 05:01:29 PM PDT 24 |
Finished | Jul 14 05:04:50 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-b79596c2-b3e8-4bd5-bb00-e91da85493d1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438315723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.3438315723 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.3837050066 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 57108148 ps |
CPU time | 0.78 seconds |
Started | Jul 14 05:01:34 PM PDT 24 |
Finished | Jul 14 05:01:35 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-5a92944c-79ee-4316-888b-ceaea17fd6be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837050066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3837050066 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.3070495797 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 16804238719 ps |
CPU time | 1095.33 seconds |
Started | Jul 14 05:01:34 PM PDT 24 |
Finished | Jul 14 05:19:50 PM PDT 24 |
Peak memory | 373536 kb |
Host | smart-4e73dd56-8a1f-4bdb-bcca-c81adb3f7d95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070495797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3070495797 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.2440297296 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 45861834 ps |
CPU time | 5.86 seconds |
Started | Jul 14 05:01:31 PM PDT 24 |
Finished | Jul 14 05:01:37 PM PDT 24 |
Peak memory | 227380 kb |
Host | smart-4562301a-b8c4-41b1-9664-706d1d951d6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440297296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2440297296 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.3135969158 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 222828613851 ps |
CPU time | 4955.32 seconds |
Started | Jul 14 05:01:43 PM PDT 24 |
Finished | Jul 14 06:24:19 PM PDT 24 |
Peak memory | 375684 kb |
Host | smart-ef420071-9aaf-4c2a-8b4b-67348f9108c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135969158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.3135969158 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1497386410 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 4532812993 ps |
CPU time | 271.25 seconds |
Started | Jul 14 05:01:42 PM PDT 24 |
Finished | Jul 14 05:06:14 PM PDT 24 |
Peak memory | 347176 kb |
Host | smart-3a28ddd5-5d10-4ed4-b2fb-f355dcbfe5c1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1497386410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1497386410 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1106382166 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 2242933255 ps |
CPU time | 219.71 seconds |
Started | Jul 14 05:01:31 PM PDT 24 |
Finished | Jul 14 05:05:11 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-fe6a1546-c176-4550-8b78-94142ce70c56 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106382166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1106382166 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1438235467 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 247452186 ps |
CPU time | 9.06 seconds |
Started | Jul 14 05:01:33 PM PDT 24 |
Finished | Jul 14 05:01:42 PM PDT 24 |
Peak memory | 241520 kb |
Host | smart-6b63ff2e-4c06-477a-a980-f8f48d4b887c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438235467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1438235467 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.4272549542 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 943102681 ps |
CPU time | 781.39 seconds |
Started | Jul 14 05:01:55 PM PDT 24 |
Finished | Jul 14 05:14:57 PM PDT 24 |
Peak memory | 373460 kb |
Host | smart-4321bc8f-925b-43e1-8d20-c57e94b86f98 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272549542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.4272549542 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.4114113796 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 27615578 ps |
CPU time | 0.71 seconds |
Started | Jul 14 05:01:56 PM PDT 24 |
Finished | Jul 14 05:01:57 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-5b18643f-2ab5-40dd-8e41-d3caace36cc6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114113796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.4114113796 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3845290662 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 1742257033 ps |
CPU time | 14.53 seconds |
Started | Jul 14 05:01:47 PM PDT 24 |
Finished | Jul 14 05:02:02 PM PDT 24 |
Peak memory | 202700 kb |
Host | smart-72343c26-dab7-4cc8-84e5-0954e5c9dbdf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845290662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3845290662 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.483118373 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 5103784661 ps |
CPU time | 648.27 seconds |
Started | Jul 14 05:01:55 PM PDT 24 |
Finished | Jul 14 05:12:44 PM PDT 24 |
Peak memory | 367472 kb |
Host | smart-322ed1b6-9ed3-40f0-8244-6f1ed6538d4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483118373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl e.483118373 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.1658922933 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 640824005 ps |
CPU time | 6.63 seconds |
Started | Jul 14 05:01:56 PM PDT 24 |
Finished | Jul 14 05:02:03 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-0a6c685f-f96d-447a-92ad-7be520b7e2a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658922933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.1658922933 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.3416109315 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 180957060 ps |
CPU time | 3.18 seconds |
Started | Jul 14 05:01:48 PM PDT 24 |
Finished | Jul 14 05:01:52 PM PDT 24 |
Peak memory | 219088 kb |
Host | smart-7b956f63-02e2-4235-a655-8b55d23497b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416109315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.3416109315 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2622808501 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 383387203 ps |
CPU time | 3.12 seconds |
Started | Jul 14 05:01:55 PM PDT 24 |
Finished | Jul 14 05:01:59 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-b1107919-c0ec-4c09-8d0b-6cd2fe644684 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622808501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.2622808501 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.2329634530 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 363574820 ps |
CPU time | 5.65 seconds |
Started | Jul 14 05:01:55 PM PDT 24 |
Finished | Jul 14 05:02:02 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-4591b4e3-afa9-4c69-8f88-1094bbfb9a13 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329634530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.2329634530 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.2777247415 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 24826576054 ps |
CPU time | 1252.74 seconds |
Started | Jul 14 05:01:43 PM PDT 24 |
Finished | Jul 14 05:22:36 PM PDT 24 |
Peak memory | 375616 kb |
Host | smart-d88eec33-91bb-4f83-b22f-a8d6b5946015 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777247415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2777247415 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.4161986996 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 3406369448 ps |
CPU time | 16.61 seconds |
Started | Jul 14 05:01:47 PM PDT 24 |
Finished | Jul 14 05:02:04 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-28127a81-e84d-4e70-9135-c9bee029048a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161986996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.4161986996 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4096026289 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 18943968374 ps |
CPU time | 325.05 seconds |
Started | Jul 14 05:01:49 PM PDT 24 |
Finished | Jul 14 05:07:14 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-440ba5d6-bea6-4290-8a67-4249cec47c99 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096026289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.4096026289 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.4080947318 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 28066895 ps |
CPU time | 0.76 seconds |
Started | Jul 14 05:01:57 PM PDT 24 |
Finished | Jul 14 05:01:58 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-6845b783-1658-4493-9560-aae261f4b08d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080947318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.4080947318 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.1221509727 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 4614334480 ps |
CPU time | 788.6 seconds |
Started | Jul 14 05:01:56 PM PDT 24 |
Finished | Jul 14 05:15:05 PM PDT 24 |
Peak memory | 373588 kb |
Host | smart-d50c5b0a-4352-4380-b428-4cceb8dae940 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221509727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1221509727 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.1965658475 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 1050447702 ps |
CPU time | 125 seconds |
Started | Jul 14 05:01:42 PM PDT 24 |
Finished | Jul 14 05:03:47 PM PDT 24 |
Peak memory | 365892 kb |
Host | smart-4169f989-1c2d-4ce0-8b33-b33261d12b91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965658475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1965658475 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.113771901 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 40428925983 ps |
CPU time | 4116.09 seconds |
Started | Jul 14 05:01:56 PM PDT 24 |
Finished | Jul 14 06:10:33 PM PDT 24 |
Peak memory | 375644 kb |
Host | smart-e0b3042f-f99c-466a-9b1b-56cce91d52f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113771901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_stress_all.113771901 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3927972814 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 616783060 ps |
CPU time | 17.46 seconds |
Started | Jul 14 05:01:55 PM PDT 24 |
Finished | Jul 14 05:02:13 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-d9ef80a8-58cf-4ae9-bb2a-e7321c7f8454 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3927972814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3927972814 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.367215647 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 4165784427 ps |
CPU time | 417.83 seconds |
Started | Jul 14 05:01:47 PM PDT 24 |
Finished | Jul 14 05:08:46 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-7751f396-90bf-481f-a965-550944f7342b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367215647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.367215647 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3984307711 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 287076332 ps |
CPU time | 4.95 seconds |
Started | Jul 14 05:01:49 PM PDT 24 |
Finished | Jul 14 05:01:54 PM PDT 24 |
Peak memory | 226088 kb |
Host | smart-346e1378-e7c1-40dd-a031-3c01d6ac2c94 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984307711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3984307711 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.815588075 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 14060061097 ps |
CPU time | 1254.49 seconds |
Started | Jul 14 05:02:09 PM PDT 24 |
Finished | Jul 14 05:23:04 PM PDT 24 |
Peak memory | 374924 kb |
Host | smart-6e151798-46e2-40aa-a3a7-b39b197e161a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815588075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sram_ctrl_access_during_key_req.815588075 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.3339220246 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 51179148 ps |
CPU time | 0.69 seconds |
Started | Jul 14 05:02:14 PM PDT 24 |
Finished | Jul 14 05:02:15 PM PDT 24 |
Peak memory | 202516 kb |
Host | smart-256e6127-d532-4be2-9d70-f3c53b159ea5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339220246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3339220246 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.738238540 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 1917617105 ps |
CPU time | 36.13 seconds |
Started | Jul 14 05:02:02 PM PDT 24 |
Finished | Jul 14 05:02:38 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-0f2bfb96-bd85-4735-a229-641bc169e0b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738238540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection. 738238540 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.884196125 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 19511954381 ps |
CPU time | 1531.64 seconds |
Started | Jul 14 05:02:08 PM PDT 24 |
Finished | Jul 14 05:27:40 PM PDT 24 |
Peak memory | 374672 kb |
Host | smart-4326886a-9902-4f21-a6b9-d982e372e1f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884196125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl e.884196125 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.3896944506 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 924839286 ps |
CPU time | 4.55 seconds |
Started | Jul 14 05:02:09 PM PDT 24 |
Finished | Jul 14 05:02:14 PM PDT 24 |
Peak memory | 214148 kb |
Host | smart-c06e5a9b-5eb7-45b3-b173-db73bf5cec8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896944506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.3896944506 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.208997250 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 79269459 ps |
CPU time | 21.78 seconds |
Started | Jul 14 05:02:02 PM PDT 24 |
Finished | Jul 14 05:02:25 PM PDT 24 |
Peak memory | 269220 kb |
Host | smart-ed681bc1-619a-4faf-b9f7-b754777a8316 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208997250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.sram_ctrl_max_throughput.208997250 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1918952317 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 177671569 ps |
CPU time | 2.54 seconds |
Started | Jul 14 05:02:16 PM PDT 24 |
Finished | Jul 14 05:02:19 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-3f9b439a-b4e3-490d-acba-9f16447c341c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918952317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1918952317 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.3909258627 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 2968319319 ps |
CPU time | 12.1 seconds |
Started | Jul 14 05:02:16 PM PDT 24 |
Finished | Jul 14 05:02:28 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-0ef2a0e7-5210-48a1-a06c-44e7ecde191c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909258627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3909258627 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.919082295 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 17313826509 ps |
CPU time | 894.03 seconds |
Started | Jul 14 05:02:02 PM PDT 24 |
Finished | Jul 14 05:16:57 PM PDT 24 |
Peak memory | 371592 kb |
Host | smart-f1acfc15-1dc7-42bf-ba74-d5a3a9329281 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919082295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip le_keys.919082295 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.227478378 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 78442478 ps |
CPU time | 1.95 seconds |
Started | Jul 14 05:02:01 PM PDT 24 |
Finished | Jul 14 05:02:04 PM PDT 24 |
Peak memory | 202672 kb |
Host | smart-c7c836af-45eb-4f37-a0d2-b33adcf5acf9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227478378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s ram_ctrl_partial_access.227478378 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3322321813 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 17833697069 ps |
CPU time | 458.94 seconds |
Started | Jul 14 05:02:04 PM PDT 24 |
Finished | Jul 14 05:09:44 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-ad46c53b-0b6f-48cc-946e-10f4210cf9e8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322321813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3322321813 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.3738866415 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 259882281 ps |
CPU time | 0.8 seconds |
Started | Jul 14 05:02:08 PM PDT 24 |
Finished | Jul 14 05:02:09 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-a491306a-c8d6-4828-a457-0b010a6e5018 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738866415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3738866415 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.4046099490 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 20246863086 ps |
CPU time | 975 seconds |
Started | Jul 14 05:02:09 PM PDT 24 |
Finished | Jul 14 05:18:25 PM PDT 24 |
Peak memory | 374464 kb |
Host | smart-29147f09-677c-4e0f-9f9f-727df67de4df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046099490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.4046099490 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.4147783785 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 766655268 ps |
CPU time | 17.38 seconds |
Started | Jul 14 05:02:08 PM PDT 24 |
Finished | Jul 14 05:02:26 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-0c2e6549-95bc-4fab-a7ed-d47d32973790 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147783785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4147783785 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3040559899 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 2592092384 ps |
CPU time | 452.06 seconds |
Started | Jul 14 05:02:16 PM PDT 24 |
Finished | Jul 14 05:09:49 PM PDT 24 |
Peak memory | 378680 kb |
Host | smart-7eb6cfbd-9a8f-4087-8e6e-feb31c9f1e88 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3040559899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3040559899 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1255999320 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 4121761852 ps |
CPU time | 195.83 seconds |
Started | Jul 14 05:02:02 PM PDT 24 |
Finished | Jul 14 05:05:18 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-1dd8942c-6cb8-47d6-9c6a-6cdf8d05bb03 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255999320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1255999320 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1702048432 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 148676875 ps |
CPU time | 98.08 seconds |
Started | Jul 14 05:02:05 PM PDT 24 |
Finished | Jul 14 05:03:43 PM PDT 24 |
Peak memory | 336424 kb |
Host | smart-bfa9903f-fe37-498b-b2c5-4dc82095d1ee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702048432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1702048432 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3943447114 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 2661747031 ps |
CPU time | 729.15 seconds |
Started | Jul 14 05:02:38 PM PDT 24 |
Finished | Jul 14 05:14:47 PM PDT 24 |
Peak memory | 370588 kb |
Host | smart-56ae16f2-d254-4ec9-b5f2-bfbfaa168bd0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943447114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3943447114 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.989993895 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 17448585 ps |
CPU time | 0.71 seconds |
Started | Jul 14 05:02:34 PM PDT 24 |
Finished | Jul 14 05:02:35 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-70b08ef9-3d42-4d29-8458-518973846b2f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989993895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.989993895 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.1681145881 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 6144765020 ps |
CPU time | 24.76 seconds |
Started | Jul 14 05:02:20 PM PDT 24 |
Finished | Jul 14 05:02:45 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-9b855d7b-5843-48de-98fd-dfb53945bb1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681145881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .1681145881 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.1606247524 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 6699959156 ps |
CPU time | 622.06 seconds |
Started | Jul 14 05:02:36 PM PDT 24 |
Finished | Jul 14 05:12:58 PM PDT 24 |
Peak memory | 374568 kb |
Host | smart-7de873d6-2bbf-4903-b906-a2bd5311c54b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606247524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.1606247524 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.475446841 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 514099799 ps |
CPU time | 3.29 seconds |
Started | Jul 14 05:02:29 PM PDT 24 |
Finished | Jul 14 05:02:33 PM PDT 24 |
Peak memory | 214120 kb |
Host | smart-88acf0ae-69a8-48de-b2d0-39c69160119b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475446841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_esc alation.475446841 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.3195064253 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 2131849079 ps |
CPU time | 161.4 seconds |
Started | Jul 14 05:02:27 PM PDT 24 |
Finished | Jul 14 05:05:09 PM PDT 24 |
Peak memory | 369288 kb |
Host | smart-57ffa8dd-02fb-4d38-a5c7-a9284dc72878 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195064253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.3195064253 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.693426428 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 344425937 ps |
CPU time | 3.09 seconds |
Started | Jul 14 05:02:37 PM PDT 24 |
Finished | Jul 14 05:02:40 PM PDT 24 |
Peak memory | 210896 kb |
Host | smart-c35fe84f-7226-4ac7-9fee-c72b69da43b6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693426428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_mem_partial_access.693426428 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.1406344073 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 714019435 ps |
CPU time | 9.83 seconds |
Started | Jul 14 05:02:33 PM PDT 24 |
Finished | Jul 14 05:02:43 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-41e8e904-f237-4cfb-8b6d-01a0732f3569 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406344073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1406344073 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.3795292858 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 28172635235 ps |
CPU time | 523.02 seconds |
Started | Jul 14 05:02:22 PM PDT 24 |
Finished | Jul 14 05:11:06 PM PDT 24 |
Peak memory | 348328 kb |
Host | smart-12789565-796d-4f84-9837-954bcff6c29e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795292858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.3795292858 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.896442027 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 375056122 ps |
CPU time | 11.23 seconds |
Started | Jul 14 05:02:20 PM PDT 24 |
Finished | Jul 14 05:02:32 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-8612074d-37a0-490e-b1d7-69f754139567 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896442027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.896442027 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1820226751 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 29746936247 ps |
CPU time | 201.58 seconds |
Started | Jul 14 05:02:22 PM PDT 24 |
Finished | Jul 14 05:05:44 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-5e647394-8747-411f-bb91-ec62f551f619 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820226751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1820226751 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2910466579 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 85183348 ps |
CPU time | 0.76 seconds |
Started | Jul 14 05:02:38 PM PDT 24 |
Finished | Jul 14 05:02:39 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-0796ba76-593d-46a5-98d8-20ba61b83713 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910466579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2910466579 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.1884921373 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 1506317648 ps |
CPU time | 92.5 seconds |
Started | Jul 14 05:02:33 PM PDT 24 |
Finished | Jul 14 05:04:06 PM PDT 24 |
Peak memory | 320120 kb |
Host | smart-5ae9a0bb-baca-4482-9c9e-f3602d7f34e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884921373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1884921373 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.2114487051 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 2364775997 ps |
CPU time | 131.49 seconds |
Started | Jul 14 05:02:16 PM PDT 24 |
Finished | Jul 14 05:04:27 PM PDT 24 |
Peak memory | 355140 kb |
Host | smart-00b1579a-bf11-4cd7-b34c-6e8abb01be7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114487051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2114487051 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.2600537248 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 21158967801 ps |
CPU time | 86.06 seconds |
Started | Jul 14 05:02:37 PM PDT 24 |
Finished | Jul 14 05:04:04 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-25ee8781-953b-4e14-96d7-e2cdd3f4c515 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600537248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.2600537248 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4250610715 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 1140566804 ps |
CPU time | 157.32 seconds |
Started | Jul 14 05:02:33 PM PDT 24 |
Finished | Jul 14 05:05:11 PM PDT 24 |
Peak memory | 345952 kb |
Host | smart-c02edb08-a44c-4ab8-93a2-749b44c2c9a2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4250610715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.4250610715 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3058797745 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2061778206 ps |
CPU time | 218.51 seconds |
Started | Jul 14 05:02:20 PM PDT 24 |
Finished | Jul 14 05:05:59 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-e28973a2-7979-4516-a065-53db8df11f5b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058797745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3058797745 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1534930241 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 374394704 ps |
CPU time | 22.73 seconds |
Started | Jul 14 05:02:28 PM PDT 24 |
Finished | Jul 14 05:02:51 PM PDT 24 |
Peak memory | 281432 kb |
Host | smart-8399d803-bef8-4d51-8207-fbe6c029c4e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534930241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1534930241 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.35944981 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 3986618031 ps |
CPU time | 1290.12 seconds |
Started | Jul 14 05:02:39 PM PDT 24 |
Finished | Jul 14 05:24:10 PM PDT 24 |
Peak memory | 374048 kb |
Host | smart-5659324b-c18e-4b98-be0a-818d1c5a8a90 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35944981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.sram_ctrl_access_during_key_req.35944981 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.3470182297 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 24367708 ps |
CPU time | 0.68 seconds |
Started | Jul 14 05:02:57 PM PDT 24 |
Finished | Jul 14 05:02:58 PM PDT 24 |
Peak memory | 202528 kb |
Host | smart-54b13966-cb32-424a-8802-5f6cf7a0a396 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470182297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3470182297 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.2920044184 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 3153509259 ps |
CPU time | 49.45 seconds |
Started | Jul 14 05:02:40 PM PDT 24 |
Finished | Jul 14 05:03:30 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-18dadc53-1c5c-4dd4-b514-8bce4ff3dcea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920044184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2920044184 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.3056448902 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 67249457606 ps |
CPU time | 861.37 seconds |
Started | Jul 14 05:02:47 PM PDT 24 |
Finished | Jul 14 05:17:09 PM PDT 24 |
Peak memory | 365108 kb |
Host | smart-0b43dca1-0123-4711-b854-17a2bee8718c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056448902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3056448902 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.3219083 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 866424479 ps |
CPU time | 6.56 seconds |
Started | Jul 14 05:02:39 PM PDT 24 |
Finished | Jul 14 05:02:46 PM PDT 24 |
Peak memory | 210884 kb |
Host | smart-9b073c74-43d1-4ec8-b507-014571a655eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esca lation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escal ation.3219083 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.1419431901 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 508330442 ps |
CPU time | 19.84 seconds |
Started | Jul 14 05:02:39 PM PDT 24 |
Finished | Jul 14 05:02:59 PM PDT 24 |
Peak memory | 272228 kb |
Host | smart-1230ccf0-a3f6-48a6-bfe1-bf469db61f46 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419431901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.1419431901 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1544069162 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 99740371 ps |
CPU time | 5.51 seconds |
Started | Jul 14 05:02:55 PM PDT 24 |
Finished | Jul 14 05:03:01 PM PDT 24 |
Peak memory | 210952 kb |
Host | smart-9b6c9936-ac16-4d1a-a9dc-e2eff3b67fda |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544069162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.1544069162 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.3820598657 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 186448542 ps |
CPU time | 9.85 seconds |
Started | Jul 14 05:02:55 PM PDT 24 |
Finished | Jul 14 05:03:05 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-dcfcabad-c205-468c-9a99-2531182f90e7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820598657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3820598657 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.1675433724 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 16871097557 ps |
CPU time | 1182.49 seconds |
Started | Jul 14 05:02:40 PM PDT 24 |
Finished | Jul 14 05:22:23 PM PDT 24 |
Peak memory | 375584 kb |
Host | smart-1148eab1-0ca3-434d-bff3-066852714caa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675433724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.1675433724 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.1025153783 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 57891023 ps |
CPU time | 1.09 seconds |
Started | Jul 14 05:02:41 PM PDT 24 |
Finished | Jul 14 05:02:42 PM PDT 24 |
Peak memory | 202472 kb |
Host | smart-295ae927-f4a5-4913-946c-375714eb99a1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025153783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1025153783 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1596007480 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 10474171627 ps |
CPU time | 285.65 seconds |
Started | Jul 14 05:02:42 PM PDT 24 |
Finished | Jul 14 05:07:28 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-6c400d3b-24b8-4fb5-a8fa-ac960d4c6cf0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596007480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1596007480 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.48244509 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 76307660 ps |
CPU time | 0.77 seconds |
Started | Jul 14 05:02:47 PM PDT 24 |
Finished | Jul 14 05:02:48 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-18c10362-69b3-4e5f-8762-ba965a6aa36c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48244509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.48244509 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.2689618133 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 6431403778 ps |
CPU time | 1287.94 seconds |
Started | Jul 14 05:02:46 PM PDT 24 |
Finished | Jul 14 05:24:15 PM PDT 24 |
Peak memory | 362284 kb |
Host | smart-c1023113-d757-412a-b3fd-7a4cb2c1009c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689618133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2689618133 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.4271835602 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 48294694 ps |
CPU time | 1.07 seconds |
Started | Jul 14 05:02:40 PM PDT 24 |
Finished | Jul 14 05:02:41 PM PDT 24 |
Peak memory | 202496 kb |
Host | smart-ad94647a-2281-45d8-a84b-fa91cef4588e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271835602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.4271835602 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.3447648389 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 6984294550 ps |
CPU time | 1958.77 seconds |
Started | Jul 14 05:02:56 PM PDT 24 |
Finished | Jul 14 05:35:35 PM PDT 24 |
Peak memory | 375664 kb |
Host | smart-c3c6b370-cb6d-4f9e-b090-ef4c58543591 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447648389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.3447648389 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2761296482 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 8126720225 ps |
CPU time | 213.81 seconds |
Started | Jul 14 05:02:40 PM PDT 24 |
Finished | Jul 14 05:06:14 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-31b474cf-06db-49e4-9e56-c796d55c4a13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761296482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2761296482 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2676647823 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 114478482 ps |
CPU time | 51.45 seconds |
Started | Jul 14 05:02:40 PM PDT 24 |
Finished | Jul 14 05:03:32 PM PDT 24 |
Peak memory | 302872 kb |
Host | smart-982ab113-ee28-4415-90c4-5173160b92e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676647823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2676647823 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2523299070 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 7953266709 ps |
CPU time | 679.79 seconds |
Started | Jul 14 05:03:03 PM PDT 24 |
Finished | Jul 14 05:14:23 PM PDT 24 |
Peak memory | 356036 kb |
Host | smart-43189fb9-b748-4996-adbc-ecbd0ed86088 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523299070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.2523299070 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1505714152 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 14927035 ps |
CPU time | 0.67 seconds |
Started | Jul 14 05:03:19 PM PDT 24 |
Finished | Jul 14 05:03:20 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-589e1e38-7f74-40cc-bc10-0070cdc94b44 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505714152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1505714152 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.3407511816 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 3154561487 ps |
CPU time | 47.44 seconds |
Started | Jul 14 05:03:02 PM PDT 24 |
Finished | Jul 14 05:03:50 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-bae0487c-821b-4e10-adce-4fb15d9a8ed8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407511816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .3407511816 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.1396779655 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 62712837821 ps |
CPU time | 1022.72 seconds |
Started | Jul 14 05:03:02 PM PDT 24 |
Finished | Jul 14 05:20:06 PM PDT 24 |
Peak memory | 374304 kb |
Host | smart-e3cac28e-365f-4f5e-9752-aaf005bd15cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396779655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1396779655 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1617210339 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 928242979 ps |
CPU time | 5.76 seconds |
Started | Jul 14 05:03:02 PM PDT 24 |
Finished | Jul 14 05:03:08 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-4d3e1ffa-938c-4925-b50d-006a6bd1973b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617210339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1617210339 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.792044721 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 49221381 ps |
CPU time | 4.37 seconds |
Started | Jul 14 05:03:02 PM PDT 24 |
Finished | Jul 14 05:03:07 PM PDT 24 |
Peak memory | 222904 kb |
Host | smart-6f4645bc-c698-4d1e-947d-c33b7028795d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792044721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.sram_ctrl_max_throughput.792044721 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4072001943 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 349978134 ps |
CPU time | 3.41 seconds |
Started | Jul 14 05:03:09 PM PDT 24 |
Finished | Jul 14 05:03:13 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-25051975-c23c-44a5-9b6d-139333385b07 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072001943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.4072001943 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.373198004 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1369355999 ps |
CPU time | 10.99 seconds |
Started | Jul 14 05:03:10 PM PDT 24 |
Finished | Jul 14 05:03:22 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-6d25d21e-5cf3-4650-b40b-141f2621156d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373198004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _mem_walk.373198004 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.1026981315 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 17976412451 ps |
CPU time | 1173.25 seconds |
Started | Jul 14 05:03:02 PM PDT 24 |
Finished | Jul 14 05:22:36 PM PDT 24 |
Peak memory | 376704 kb |
Host | smart-fee31d49-4e14-47e2-87ed-fbb00f11c0a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026981315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1026981315 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.1138961882 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 235661487 ps |
CPU time | 8.46 seconds |
Started | Jul 14 05:03:04 PM PDT 24 |
Finished | Jul 14 05:03:12 PM PDT 24 |
Peak memory | 231252 kb |
Host | smart-efb9fa79-3aaf-498f-a7cd-195b0d98622c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138961882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.1138961882 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.172469889 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 51918978274 ps |
CPU time | 345.49 seconds |
Started | Jul 14 05:03:04 PM PDT 24 |
Finished | Jul 14 05:08:50 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-6473ad49-7c92-4c60-9d98-5d822582936f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172469889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.sram_ctrl_partial_access_b2b.172469889 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2985292867 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 115233556 ps |
CPU time | 0.77 seconds |
Started | Jul 14 05:03:12 PM PDT 24 |
Finished | Jul 14 05:03:13 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-5990b386-dc92-4c46-8e33-ea72de0be7dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985292867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2985292867 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.3408803036 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 7084878622 ps |
CPU time | 757.26 seconds |
Started | Jul 14 05:03:01 PM PDT 24 |
Finished | Jul 14 05:15:39 PM PDT 24 |
Peak memory | 372936 kb |
Host | smart-9da0eba0-ec43-408c-a42b-140b23cc50ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408803036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3408803036 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.1887551128 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 743833360 ps |
CPU time | 11.5 seconds |
Started | Jul 14 05:02:55 PM PDT 24 |
Finished | Jul 14 05:03:07 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-826f70e0-6e20-44aa-b01d-39be4b9057f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887551128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1887551128 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.3447874582 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 8612222029 ps |
CPU time | 2644.31 seconds |
Started | Jul 14 05:03:19 PM PDT 24 |
Finished | Jul 14 05:47:24 PM PDT 24 |
Peak memory | 383900 kb |
Host | smart-01d5aef4-447f-42b0-9927-221d63d1e385 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447874582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.3447874582 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1193923227 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 2529908194 ps |
CPU time | 156.08 seconds |
Started | Jul 14 05:03:11 PM PDT 24 |
Finished | Jul 14 05:05:48 PM PDT 24 |
Peak memory | 322528 kb |
Host | smart-89c3f211-c524-4bad-a55a-0f8f6bc02ac8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1193923227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1193923227 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2890954297 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 1850287068 ps |
CPU time | 178.26 seconds |
Started | Jul 14 05:03:04 PM PDT 24 |
Finished | Jul 14 05:06:02 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-62983418-198f-4e4c-a64d-485267cec17d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890954297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2890954297 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2069090572 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 163215237 ps |
CPU time | 3.02 seconds |
Started | Jul 14 05:03:02 PM PDT 24 |
Finished | Jul 14 05:03:05 PM PDT 24 |
Peak memory | 219028 kb |
Host | smart-622b2f87-f722-409a-81fd-7e4aaf259867 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069090572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2069090572 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3254840919 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 3510564975 ps |
CPU time | 1342.74 seconds |
Started | Jul 14 05:03:25 PM PDT 24 |
Finished | Jul 14 05:25:48 PM PDT 24 |
Peak memory | 373560 kb |
Host | smart-c104fdd4-bcff-45ab-a53a-376b0e4cdebb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254840919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.3254840919 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.3742888174 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 13308921 ps |
CPU time | 0.67 seconds |
Started | Jul 14 05:03:32 PM PDT 24 |
Finished | Jul 14 05:03:33 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-f3aa73cb-6b60-4cd0-8458-5cd1c3dc6e70 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742888174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3742888174 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.2353054578 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 6808888447 ps |
CPU time | 73.76 seconds |
Started | Jul 14 05:03:18 PM PDT 24 |
Finished | Jul 14 05:04:32 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-a9ebe4ad-e2a3-49b9-97c6-40292660c4cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353054578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2353054578 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.3731181924 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 2892921813 ps |
CPU time | 414.95 seconds |
Started | Jul 14 05:03:25 PM PDT 24 |
Finished | Jul 14 05:10:20 PM PDT 24 |
Peak memory | 367116 kb |
Host | smart-5804ec33-595b-4c6c-b0d3-26cf054e253e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731181924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.3731181924 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.338885193 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 1021591911 ps |
CPU time | 3.37 seconds |
Started | Jul 14 05:03:18 PM PDT 24 |
Finished | Jul 14 05:03:22 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-3e874d8d-0a97-4bbf-804c-89ea77134744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338885193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esc alation.338885193 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2023936636 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 182110427 ps |
CPU time | 58.88 seconds |
Started | Jul 14 05:03:18 PM PDT 24 |
Finished | Jul 14 05:04:18 PM PDT 24 |
Peak memory | 297176 kb |
Host | smart-c64edfbc-92a3-4819-abd5-26bcd9773743 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023936636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2023936636 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3948371411 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 97951465 ps |
CPU time | 3.15 seconds |
Started | Jul 14 05:03:25 PM PDT 24 |
Finished | Jul 14 05:03:28 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-135ba214-53f9-4d37-9067-515abea0820e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948371411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.3948371411 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.2141309137 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 462270591 ps |
CPU time | 10.39 seconds |
Started | Jul 14 05:03:25 PM PDT 24 |
Finished | Jul 14 05:03:36 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-68738663-56c0-45f3-954c-2901695dd96c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141309137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2141309137 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.3434026910 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 16214607057 ps |
CPU time | 754.14 seconds |
Started | Jul 14 05:03:17 PM PDT 24 |
Finished | Jul 14 05:15:52 PM PDT 24 |
Peak memory | 368456 kb |
Host | smart-560f56de-60ea-4285-ad5d-4c6fc9f71b79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434026910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.3434026910 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2689370973 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 2047871263 ps |
CPU time | 14.19 seconds |
Started | Jul 14 05:03:19 PM PDT 24 |
Finished | Jul 14 05:03:33 PM PDT 24 |
Peak memory | 249728 kb |
Host | smart-c4a72e40-a9af-46de-88f7-08f11989fb48 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689370973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2689370973 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2377680371 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 59911032095 ps |
CPU time | 384.39 seconds |
Started | Jul 14 05:03:19 PM PDT 24 |
Finished | Jul 14 05:09:44 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-dbdc1203-7192-4940-b69c-52e69538daf2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377680371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.2377680371 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.1091623074 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 45506875 ps |
CPU time | 0.81 seconds |
Started | Jul 14 05:03:25 PM PDT 24 |
Finished | Jul 14 05:03:26 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-442a6ce6-896e-4773-94c4-b93a1c018ee9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091623074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1091623074 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.3264293221 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 4141376396 ps |
CPU time | 311.54 seconds |
Started | Jul 14 05:03:24 PM PDT 24 |
Finished | Jul 14 05:08:36 PM PDT 24 |
Peak memory | 370712 kb |
Host | smart-c2bb421c-c80b-4c08-b085-01b9dfa558ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264293221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3264293221 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.1649126003 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 370666637 ps |
CPU time | 39.78 seconds |
Started | Jul 14 05:03:19 PM PDT 24 |
Finished | Jul 14 05:03:59 PM PDT 24 |
Peak memory | 291204 kb |
Host | smart-7694a1cb-082a-443c-89d1-a7f566f30371 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649126003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1649126003 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.1165656640 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 30132315908 ps |
CPU time | 2991.87 seconds |
Started | Jul 14 05:03:31 PM PDT 24 |
Finished | Jul 14 05:53:24 PM PDT 24 |
Peak memory | 375708 kb |
Host | smart-c1e54e21-bbc5-4608-a817-a478f7c81fe2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165656640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.1165656640 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2490435289 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2339925612 ps |
CPU time | 37.96 seconds |
Started | Jul 14 05:03:31 PM PDT 24 |
Finished | Jul 14 05:04:09 PM PDT 24 |
Peak memory | 235636 kb |
Host | smart-490012b7-2fca-4ba2-9479-9206861d393b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2490435289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2490435289 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1695167152 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 12019955031 ps |
CPU time | 217.92 seconds |
Started | Jul 14 05:03:18 PM PDT 24 |
Finished | Jul 14 05:06:57 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-98191fe2-4364-451c-a5bd-30adcee62c40 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695167152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.1695167152 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4116503078 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 194074244 ps |
CPU time | 162.17 seconds |
Started | Jul 14 05:03:20 PM PDT 24 |
Finished | Jul 14 05:06:02 PM PDT 24 |
Peak memory | 370028 kb |
Host | smart-eb84dce2-a619-4fd8-b887-721982c995ac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116503078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.4116503078 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2652024296 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 3402732212 ps |
CPU time | 1057.59 seconds |
Started | Jul 14 05:03:45 PM PDT 24 |
Finished | Jul 14 05:21:23 PM PDT 24 |
Peak memory | 374600 kb |
Host | smart-0cb28adc-586d-4bc4-bb3d-cafcca102449 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652024296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.2652024296 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.756367248 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 12792334 ps |
CPU time | 0.63 seconds |
Started | Jul 14 05:03:52 PM PDT 24 |
Finished | Jul 14 05:03:53 PM PDT 24 |
Peak memory | 202576 kb |
Host | smart-e1bf67a1-54cb-4173-b36d-02331f9f3c07 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756367248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.756367248 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.2591983484 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 1991333836 ps |
CPU time | 21.61 seconds |
Started | Jul 14 05:03:37 PM PDT 24 |
Finished | Jul 14 05:03:59 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-1f517958-873b-4e11-bd10-454e006fa376 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591983484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2591983484 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.2124897172 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 6489136414 ps |
CPU time | 1146.49 seconds |
Started | Jul 14 05:03:46 PM PDT 24 |
Finished | Jul 14 05:22:53 PM PDT 24 |
Peak memory | 365632 kb |
Host | smart-8c63fe09-018f-46d8-b5db-806ba694994b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124897172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2124897172 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.3878570955 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 6546805573 ps |
CPU time | 8.4 seconds |
Started | Jul 14 05:03:45 PM PDT 24 |
Finished | Jul 14 05:03:53 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-f98e29c8-aab7-455c-8f24-3f911b2c2791 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878570955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.3878570955 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.3466695849 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 83715793 ps |
CPU time | 29.82 seconds |
Started | Jul 14 05:03:44 PM PDT 24 |
Finished | Jul 14 05:04:14 PM PDT 24 |
Peak memory | 276400 kb |
Host | smart-78fccd4e-7eb1-4386-ae71-023a859f0511 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466695849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.3466695849 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1674211601 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 342018590 ps |
CPU time | 2.89 seconds |
Started | Jul 14 05:03:53 PM PDT 24 |
Finished | Jul 14 05:03:57 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-0e3a9fa1-18fd-48c1-962e-3b11b8e5459d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674211601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.1674211601 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.780814145 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 1543171595 ps |
CPU time | 10.01 seconds |
Started | Jul 14 05:03:53 PM PDT 24 |
Finished | Jul 14 05:04:04 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-29439504-d8f3-4af7-b0d3-f88b4f314835 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780814145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _mem_walk.780814145 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.2746059261 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 1329676997 ps |
CPU time | 37.71 seconds |
Started | Jul 14 05:03:32 PM PDT 24 |
Finished | Jul 14 05:04:11 PM PDT 24 |
Peak memory | 264816 kb |
Host | smart-c3b555a7-b23b-4499-999a-9d4963d0072f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746059261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.2746059261 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1054007633 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 122719696 ps |
CPU time | 36.44 seconds |
Started | Jul 14 05:03:37 PM PDT 24 |
Finished | Jul 14 05:04:14 PM PDT 24 |
Peak memory | 281404 kb |
Host | smart-0da3ed69-bf68-4f4c-984f-301b8d3727bd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054007633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1054007633 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1185045479 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 2277046394 ps |
CPU time | 172.41 seconds |
Started | Jul 14 05:03:43 PM PDT 24 |
Finished | Jul 14 05:06:36 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-2b517677-7a1c-4901-b1a3-bebb701afdf5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185045479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1185045479 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.2842127679 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 278273766 ps |
CPU time | 0.79 seconds |
Started | Jul 14 05:03:54 PM PDT 24 |
Finished | Jul 14 05:03:55 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-f830f067-ef56-41b0-8fb9-d25b6d0bc1b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842127679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2842127679 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3952188072 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 4215561857 ps |
CPU time | 1500.38 seconds |
Started | Jul 14 05:03:52 PM PDT 24 |
Finished | Jul 14 05:28:53 PM PDT 24 |
Peak memory | 374692 kb |
Host | smart-b643ffd0-df56-4202-a183-90ecd8fb4b60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952188072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3952188072 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.1627295769 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 643396331 ps |
CPU time | 182.65 seconds |
Started | Jul 14 05:03:33 PM PDT 24 |
Finished | Jul 14 05:06:36 PM PDT 24 |
Peak memory | 367384 kb |
Host | smart-bb647ab7-e3f1-4e09-952e-3e93635c44d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627295769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1627295769 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.244232302 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 132026149737 ps |
CPU time | 3730.64 seconds |
Started | Jul 14 05:03:52 PM PDT 24 |
Finished | Jul 14 06:06:03 PM PDT 24 |
Peak memory | 381920 kb |
Host | smart-28c88beb-e22c-4478-9c2c-3e472e0bad14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244232302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_stress_all.244232302 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1908419797 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 2324252633 ps |
CPU time | 55.59 seconds |
Started | Jul 14 05:03:53 PM PDT 24 |
Finished | Jul 14 05:04:49 PM PDT 24 |
Peak memory | 272000 kb |
Host | smart-bfd59602-c8df-481a-83dc-5bc425155da2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1908419797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1908419797 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.324639244 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 1104633187 ps |
CPU time | 113.42 seconds |
Started | Jul 14 05:03:38 PM PDT 24 |
Finished | Jul 14 05:05:32 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-0273e07a-3106-4942-9236-2b6bc2169f30 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324639244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_stress_pipeline.324639244 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1310575777 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 325845815 ps |
CPU time | 25.9 seconds |
Started | Jul 14 05:03:45 PM PDT 24 |
Finished | Jul 14 05:04:12 PM PDT 24 |
Peak memory | 270132 kb |
Host | smart-2aa8ef52-da96-4e38-9fb9-3a0c4e3357ef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310575777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1310575777 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3574936133 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1174048459 ps |
CPU time | 650.44 seconds |
Started | Jul 14 05:04:08 PM PDT 24 |
Finished | Jul 14 05:15:00 PM PDT 24 |
Peak memory | 373956 kb |
Host | smart-7b78839e-b5ca-4612-a50b-aa70ea5ec80d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574936133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.3574936133 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.3908951556 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 42952421 ps |
CPU time | 0.67 seconds |
Started | Jul 14 05:04:23 PM PDT 24 |
Finished | Jul 14 05:04:24 PM PDT 24 |
Peak memory | 202512 kb |
Host | smart-062fc4df-9483-416b-b938-7aae4ee2bd80 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908951556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3908951556 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.1766528633 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 5506949580 ps |
CPU time | 47.82 seconds |
Started | Jul 14 05:03:57 PM PDT 24 |
Finished | Jul 14 05:04:45 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-c300e9f7-af09-4fef-84e3-21205fcd3474 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766528633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .1766528633 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.2623365206 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 7338114405 ps |
CPU time | 2093.94 seconds |
Started | Jul 14 05:04:07 PM PDT 24 |
Finished | Jul 14 05:39:02 PM PDT 24 |
Peak memory | 372640 kb |
Host | smart-fb6c05d6-8335-4b0d-8942-875330490529 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623365206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2623365206 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.2548653089 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 480532664 ps |
CPU time | 6.91 seconds |
Started | Jul 14 05:04:05 PM PDT 24 |
Finished | Jul 14 05:04:13 PM PDT 24 |
Peak memory | 202732 kb |
Host | smart-d4a87940-92d4-4132-9b66-e9ba78ec1b50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548653089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.2548653089 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.408682739 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 221390637 ps |
CPU time | 94.94 seconds |
Started | Jul 14 05:04:05 PM PDT 24 |
Finished | Jul 14 05:05:41 PM PDT 24 |
Peak memory | 326584 kb |
Host | smart-94a7be9e-71c4-4bc8-94de-3afc8997adaf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408682739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.408682739 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2160435752 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 92970736 ps |
CPU time | 3.17 seconds |
Started | Jul 14 05:04:15 PM PDT 24 |
Finished | Jul 14 05:04:19 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-3e82a395-9da3-4c43-95b0-ec093350e410 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160435752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.2160435752 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.2377324173 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 180129628 ps |
CPU time | 4.65 seconds |
Started | Jul 14 05:04:16 PM PDT 24 |
Finished | Jul 14 05:04:21 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-52c7209d-0c63-4588-92c7-ce6840014f6c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377324173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.2377324173 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.2264026210 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 5477435815 ps |
CPU time | 566.85 seconds |
Started | Jul 14 05:04:02 PM PDT 24 |
Finished | Jul 14 05:13:29 PM PDT 24 |
Peak memory | 369468 kb |
Host | smart-96854984-fdc6-4340-91d2-1288b58630b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264026210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.2264026210 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.171952166 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 1552397327 ps |
CPU time | 169.74 seconds |
Started | Jul 14 05:03:58 PM PDT 24 |
Finished | Jul 14 05:06:48 PM PDT 24 |
Peak memory | 364048 kb |
Host | smart-7b854380-dc99-43ad-9ea2-d79ff8b19870 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171952166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s ram_ctrl_partial_access.171952166 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1149624332 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 117936577195 ps |
CPU time | 436.57 seconds |
Started | Jul 14 05:03:58 PM PDT 24 |
Finished | Jul 14 05:11:15 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-63fb6cd3-d668-4ac3-aea6-935ccb4ed249 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149624332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1149624332 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.172668455 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 72706880 ps |
CPU time | 0.86 seconds |
Started | Jul 14 05:04:13 PM PDT 24 |
Finished | Jul 14 05:04:15 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-e47a85ba-5aaf-40ab-8115-792e2d82b3dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172668455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.172668455 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.3357792016 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 4288931207 ps |
CPU time | 750.26 seconds |
Started | Jul 14 05:04:15 PM PDT 24 |
Finished | Jul 14 05:16:45 PM PDT 24 |
Peak memory | 364596 kb |
Host | smart-14195bb6-d4b6-4671-aec5-bcd0ecfa02f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357792016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3357792016 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.1173553101 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 967751106 ps |
CPU time | 95.44 seconds |
Started | Jul 14 05:03:51 PM PDT 24 |
Finished | Jul 14 05:05:27 PM PDT 24 |
Peak memory | 324436 kb |
Host | smart-caf26201-a5e4-43e6-a29d-6563795d1fc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173553101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1173553101 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.2176139911 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 69597124840 ps |
CPU time | 4668.09 seconds |
Started | Jul 14 05:04:23 PM PDT 24 |
Finished | Jul 14 06:22:12 PM PDT 24 |
Peak memory | 375748 kb |
Host | smart-2afd7afe-03d1-4215-9cdb-7f2992951f77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176139911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.2176139911 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2441670121 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 2459494259 ps |
CPU time | 235.78 seconds |
Started | Jul 14 05:03:59 PM PDT 24 |
Finished | Jul 14 05:07:55 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-af41658f-a2f7-489f-ae3a-c6bf037e2618 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441670121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.2441670121 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1516921027 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 119806786 ps |
CPU time | 68.6 seconds |
Started | Jul 14 05:04:05 PM PDT 24 |
Finished | Jul 14 05:05:15 PM PDT 24 |
Peak memory | 309380 kb |
Host | smart-d02406ad-b673-42dd-85fa-eb2cd492d1dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516921027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1516921027 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4033189140 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 10138541465 ps |
CPU time | 568.86 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 05:03:44 PM PDT 24 |
Peak memory | 346720 kb |
Host | smart-0fab4ce6-0c14-483b-af5f-80eac791ff9a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033189140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.4033189140 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.4144347001 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 13575362 ps |
CPU time | 0.67 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:17 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-064df919-00c3-456b-ab58-e36c421413eb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144347001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.4144347001 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.876249145 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 2585445318 ps |
CPU time | 59.17 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:55:16 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-34e31f59-e448-4fff-8fe4-1e76ed6ab821 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876249145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.876249145 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.1509401612 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 4317466425 ps |
CPU time | 1218.55 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 05:14:35 PM PDT 24 |
Peak memory | 366296 kb |
Host | smart-e8a581f1-db94-440e-b085-1f786aaa7183 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509401612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.1509401612 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.1310081561 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 623074380 ps |
CPU time | 2.39 seconds |
Started | Jul 14 04:54:13 PM PDT 24 |
Finished | Jul 14 04:54:16 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-96bd7f94-0163-4fb8-b37e-332007ea2121 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310081561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.1310081561 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.3877556902 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 333557349 ps |
CPU time | 1.19 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:17 PM PDT 24 |
Peak memory | 202460 kb |
Host | smart-aed122b7-50dd-49d2-a6dc-3844a27f3730 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877556902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.3877556902 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3938619992 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 344175140 ps |
CPU time | 6.35 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:54:23 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-a4428b81-babd-424e-817b-1e69beb0de8a |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938619992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3938619992 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.3369725091 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 184235208 ps |
CPU time | 5.94 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:54:22 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-9169bc19-9f28-490b-9378-0751306a66ec |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369725091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.3369725091 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.776363722 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 16389615101 ps |
CPU time | 825.16 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 05:08:11 PM PDT 24 |
Peak memory | 372512 kb |
Host | smart-28038b65-5823-4d32-8ad1-163d4fc31999 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776363722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl e_keys.776363722 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.393726746 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 1054678615 ps |
CPU time | 12.06 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:54:29 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-38ddcec5-a86c-430a-a935-a9373f2071c9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393726746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr am_ctrl_partial_access.393726746 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2078987997 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 24086627056 ps |
CPU time | 692.88 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 05:05:48 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-eec33db7-220f-4909-a949-e5514ce7b059 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078987997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2078987997 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.369719481 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 351628379 ps |
CPU time | 0.75 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:15 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-3613b2c2-b40c-4560-9d5a-efb829601c12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369719481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.369719481 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2555891785 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 7850717930 ps |
CPU time | 448.42 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 05:01:54 PM PDT 24 |
Peak memory | 358168 kb |
Host | smart-3b25f8a0-dfc9-48a0-8a61-a142edc939e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555891785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2555891785 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.4169736177 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 397391434 ps |
CPU time | 62.13 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:55:19 PM PDT 24 |
Peak memory | 299880 kb |
Host | smart-c7022f74-4870-4e00-a598-93298c417cd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169736177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4169736177 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3806261511 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 6567873977 ps |
CPU time | 348.85 seconds |
Started | Jul 14 04:54:17 PM PDT 24 |
Finished | Jul 14 05:00:06 PM PDT 24 |
Peak memory | 366312 kb |
Host | smart-88f2fd53-8989-485c-8c30-a459f980a161 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806261511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3806261511 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2190605498 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 510605482 ps |
CPU time | 20.66 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:54:38 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-e8f100db-f5c4-4d33-9b0c-af43fa6a79ea |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2190605498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2190605498 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3002020997 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 4441341481 ps |
CPU time | 172.77 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:57:09 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-651a30c5-2593-42ce-9f77-c4121d346e63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002020997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.3002020997 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3128379450 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 142337816 ps |
CPU time | 84.35 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:55:41 PM PDT 24 |
Peak memory | 343800 kb |
Host | smart-aed37db2-afec-4a99-b505-18d7a69bf736 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128379450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3128379450 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.132392495 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 2801839257 ps |
CPU time | 672.92 seconds |
Started | Jul 14 04:54:13 PM PDT 24 |
Finished | Jul 14 05:05:27 PM PDT 24 |
Peak memory | 375580 kb |
Host | smart-afeda0a2-c520-42b1-a56f-57d322cb56da |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132392495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_access_during_key_req.132392495 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.4010726066 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 71667149 ps |
CPU time | 0.66 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:54:24 PM PDT 24 |
Peak memory | 202448 kb |
Host | smart-11f6a64a-8e4f-46e3-be7c-7fee1f0d514d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010726066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.4010726066 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.1743042687 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 7876401809 ps |
CPU time | 47.71 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:55:05 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-5af0c4dd-58b6-485a-ab39-0cb067c0602e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743042687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 1743042687 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.4288493421 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 3231540925 ps |
CPU time | 980.05 seconds |
Started | Jul 14 04:54:19 PM PDT 24 |
Finished | Jul 14 05:10:39 PM PDT 24 |
Peak memory | 371560 kb |
Host | smart-e48272b0-aaf5-4f4a-ab11-250e17c1a553 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288493421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.4288493421 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.4092902633 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 1331521741 ps |
CPU time | 7.04 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 04:54:33 PM PDT 24 |
Peak memory | 202664 kb |
Host | smart-f3cbde72-6933-43c1-bc17-1f50b2e9c8b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092902633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.4092902633 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.710526959 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 235734633 ps |
CPU time | 12.52 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:54:28 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-a23fc30b-5185-4616-9096-31d6a38742bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710526959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.sram_ctrl_max_throughput.710526959 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1324928363 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 92380017 ps |
CPU time | 3.28 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:54:27 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-f653c321-fc9a-4350-9793-7e6229e8afcb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324928363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.1324928363 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.1293986767 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2976795146 ps |
CPU time | 12.26 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 04:54:36 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-6caad17a-6ca0-452e-8379-b26acb1870b2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293986767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1293986767 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.2967381696 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 56486851905 ps |
CPU time | 1918.97 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 05:26:15 PM PDT 24 |
Peak memory | 375604 kb |
Host | smart-5fe3e50f-9fc5-459f-889b-8cee1592af5b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967381696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2967381696 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.190113746 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1990091479 ps |
CPU time | 17.41 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:54:35 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-9cde1a5e-9994-453f-8a0a-f4108d70ead1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190113746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr am_ctrl_partial_access.190113746 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2165011191 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 23742074646 ps |
CPU time | 273.07 seconds |
Started | Jul 14 04:54:14 PM PDT 24 |
Finished | Jul 14 04:58:48 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-b75a29ed-e064-4627-a71b-114282d69427 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165011191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.2165011191 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2979274556 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 27390211 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:54:20 PM PDT 24 |
Finished | Jul 14 04:54:22 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-10d918c2-1257-47b0-93c8-d4dec87d151a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979274556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2979274556 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.1889794662 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 14191256448 ps |
CPU time | 855.43 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 05:08:38 PM PDT 24 |
Peak memory | 374564 kb |
Host | smart-7a8d40f5-5bcf-4693-ab13-ab18304ca948 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889794662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1889794662 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.216301416 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 350825509 ps |
CPU time | 1.39 seconds |
Started | Jul 14 04:54:16 PM PDT 24 |
Finished | Jul 14 04:54:19 PM PDT 24 |
Peak memory | 202504 kb |
Host | smart-680ffd33-90b1-46e5-b168-be1bad03e324 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216301416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.216301416 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2293502204 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 780125123 ps |
CPU time | 24.85 seconds |
Started | Jul 14 04:54:20 PM PDT 24 |
Finished | Jul 14 04:54:45 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-a7a398cb-ab0a-4719-bd42-a0c078b043d7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2293502204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2293502204 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2384342549 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 4181626075 ps |
CPU time | 197.15 seconds |
Started | Jul 14 04:54:15 PM PDT 24 |
Finished | Jul 14 04:57:33 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-80f1ba5d-ad61-4bde-8c1c-4ec973cc7d99 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384342549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.2384342549 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1395871918 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 36627433 ps |
CPU time | 1.15 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 04:54:27 PM PDT 24 |
Peak memory | 210652 kb |
Host | smart-85eb9c8d-a765-4b00-9d25-46d136674f4d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395871918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1395871918 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1151744202 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 2147813995 ps |
CPU time | 888.06 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 05:09:12 PM PDT 24 |
Peak memory | 371572 kb |
Host | smart-6855de65-8b14-4a80-8979-9fda7af2a50d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151744202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1151744202 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2561836776 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 16750775 ps |
CPU time | 0.69 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:54:24 PM PDT 24 |
Peak memory | 202524 kb |
Host | smart-6f5f42db-d5d2-4140-9ed2-401e0a43dbb5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561836776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2561836776 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.828558513 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 1316261082 ps |
CPU time | 31.74 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:54:55 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-a6efb8ce-b93b-4480-9eac-8596f67d738f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828558513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.828558513 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.2274865641 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 30216969290 ps |
CPU time | 1033.15 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 05:11:37 PM PDT 24 |
Peak memory | 374716 kb |
Host | smart-c7e481eb-824b-49c2-a670-d543be851420 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274865641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.2274865641 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.3866353624 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 369428609 ps |
CPU time | 2.69 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:54:25 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-2c623fb9-0c54-4ac5-a7ea-6c7e3c479306 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866353624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.3866353624 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.3277640589 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 519466564 ps |
CPU time | 127.75 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:56:30 PM PDT 24 |
Peak memory | 371116 kb |
Host | smart-e1291e08-864e-4a16-822a-996196f95cfb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277640589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.3277640589 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2056615452 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 45719985 ps |
CPU time | 2.89 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:54:25 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-888930e1-65b1-49c2-88c7-a558a2db5082 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056615452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.2056615452 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2885159909 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 871537070 ps |
CPU time | 5.6 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:54:27 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-1e62f0dc-3b79-4598-8fdd-7e8f53748ee2 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885159909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2885159909 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.3295928893 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 10213025723 ps |
CPU time | 1058 seconds |
Started | Jul 14 04:54:20 PM PDT 24 |
Finished | Jul 14 05:11:59 PM PDT 24 |
Peak memory | 375692 kb |
Host | smart-91b31095-2734-434a-b71d-3a9de31a822c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295928893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3295928893 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.3420930410 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 585472488 ps |
CPU time | 3.07 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 04:54:28 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-dc6143b1-fa7e-4e25-a4cd-d8065e112b99 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420930410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3420930410 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2064445851 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 4111118684 ps |
CPU time | 301.31 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 04:59:26 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-9c654858-5f09-43f3-b3f9-6a08739dc1ac |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064445851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.2064445851 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.3724822890 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 77332103 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:54:23 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-a822eed0-f771-406e-be0a-d36197d9b481 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724822890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3724822890 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.1763076690 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 11852977851 ps |
CPU time | 1428.44 seconds |
Started | Jul 14 04:54:24 PM PDT 24 |
Finished | Jul 14 05:18:13 PM PDT 24 |
Peak memory | 374628 kb |
Host | smart-0a52fad8-fe2f-41da-8f7c-b98fffe87ed1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763076690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1763076690 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.1354077242 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 2123372904 ps |
CPU time | 125.32 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:56:28 PM PDT 24 |
Peak memory | 340380 kb |
Host | smart-52740bf8-fed3-4f8c-abee-0c35a29a972f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354077242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1354077242 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1753367179 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 46166033451 ps |
CPU time | 3681.74 seconds |
Started | Jul 14 04:54:24 PM PDT 24 |
Finished | Jul 14 05:55:47 PM PDT 24 |
Peak memory | 374596 kb |
Host | smart-0ce9b1b3-8586-4640-a911-87c137fea87e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753367179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1753367179 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.917907809 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 4798146150 ps |
CPU time | 145.09 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:56:47 PM PDT 24 |
Peak memory | 365272 kb |
Host | smart-9fb5a26b-8ab1-448a-a388-47070066a2fa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=917907809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.917907809 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1883062813 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 11021566546 ps |
CPU time | 247.79 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 04:58:32 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-ab46c11f-0fa8-463e-b31c-9a46cd3b6bd7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883062813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.1883062813 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3336234441 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 85846812 ps |
CPU time | 17.64 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:54:40 PM PDT 24 |
Peak memory | 252760 kb |
Host | smart-3754e232-3e59-4c7b-8ae2-e333f22c44c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336234441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.3336234441 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3085532390 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 2371061799 ps |
CPU time | 1554.88 seconds |
Started | Jul 14 04:54:29 PM PDT 24 |
Finished | Jul 14 05:20:25 PM PDT 24 |
Peak memory | 373284 kb |
Host | smart-0dc58cee-b98c-44a8-97b9-3dc860f7a5cb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085532390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.3085532390 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.1601950763 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 30174569 ps |
CPU time | 0.64 seconds |
Started | Jul 14 04:54:31 PM PDT 24 |
Finished | Jul 14 04:54:32 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-f4346434-4df8-4835-bd88-02b98254ac22 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601950763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1601950763 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.2108688718 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 6467148765 ps |
CPU time | 56.86 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:55:19 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-5eebb18f-71d2-4961-a8a8-c8b21a284fda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108688718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 2108688718 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.2500992821 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 13795316603 ps |
CPU time | 613.27 seconds |
Started | Jul 14 04:54:29 PM PDT 24 |
Finished | Jul 14 05:04:43 PM PDT 24 |
Peak memory | 375448 kb |
Host | smart-51d07ef1-d6cc-4c62-8774-c88f8e334e64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500992821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.2500992821 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.340546835 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 2369283556 ps |
CPU time | 9.25 seconds |
Started | Jul 14 04:54:31 PM PDT 24 |
Finished | Jul 14 04:54:41 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-e2862a12-5028-4ff2-8b0c-6104b7c1330b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340546835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca lation.340546835 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.449889010 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 122234145 ps |
CPU time | 66.35 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:55:29 PM PDT 24 |
Peak memory | 328352 kb |
Host | smart-e0a77e74-08f7-4af5-b7b5-767adea28bc9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449889010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_max_throughput.449889010 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.483100699 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 999569431 ps |
CPU time | 4.03 seconds |
Started | Jul 14 04:54:30 PM PDT 24 |
Finished | Jul 14 04:54:34 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-f40397b0-9067-4ad7-a2e3-64507a63d724 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483100699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. sram_ctrl_mem_partial_access.483100699 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.3589323519 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 449529118 ps |
CPU time | 10.61 seconds |
Started | Jul 14 04:54:31 PM PDT 24 |
Finished | Jul 14 04:54:42 PM PDT 24 |
Peak memory | 210928 kb |
Host | smart-e7d08aed-6974-450f-aa8a-5ba7459d9cfa |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589323519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.3589323519 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.120839208 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 36509143110 ps |
CPU time | 826.1 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 05:08:10 PM PDT 24 |
Peak memory | 373544 kb |
Host | smart-88cbe738-85a8-42a6-b8e1-5745a4459615 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120839208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl e_keys.120839208 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.1664171478 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 918420659 ps |
CPU time | 5.14 seconds |
Started | Jul 14 04:54:22 PM PDT 24 |
Finished | Jul 14 04:54:28 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-470bdd4d-96dc-475c-ba9a-ef00dbcdee8e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664171478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1664171478 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3893514623 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 23295522471 ps |
CPU time | 627.52 seconds |
Started | Jul 14 04:54:23 PM PDT 24 |
Finished | Jul 14 05:04:52 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-fb075f8c-f0b5-49bc-82ed-50d727f3c957 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893514623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.3893514623 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.4289229901 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 46286562 ps |
CPU time | 0.78 seconds |
Started | Jul 14 04:54:32 PM PDT 24 |
Finished | Jul 14 04:54:33 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-0f45466e-7142-435b-9535-04d308f682f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289229901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.4289229901 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.2484305100 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 15779479664 ps |
CPU time | 1247.94 seconds |
Started | Jul 14 04:54:34 PM PDT 24 |
Finished | Jul 14 05:15:22 PM PDT 24 |
Peak memory | 370576 kb |
Host | smart-99643027-392c-4f95-a27f-3888ca7e074f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484305100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2484305100 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.260958857 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 516653580 ps |
CPU time | 145.36 seconds |
Started | Jul 14 04:54:25 PM PDT 24 |
Finished | Jul 14 04:56:50 PM PDT 24 |
Peak memory | 359692 kb |
Host | smart-e6d7f962-c6d9-46fd-8566-a9e9077dc1bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260958857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.260958857 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.339180568 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 23621188312 ps |
CPU time | 3220.87 seconds |
Started | Jul 14 04:54:34 PM PDT 24 |
Finished | Jul 14 05:48:16 PM PDT 24 |
Peak memory | 377704 kb |
Host | smart-1f32b487-41f5-4b61-8c64-e65daf17e532 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339180568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_stress_all.339180568 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2352235298 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 1358988101 ps |
CPU time | 504.17 seconds |
Started | Jul 14 04:54:30 PM PDT 24 |
Finished | Jul 14 05:02:54 PM PDT 24 |
Peak memory | 378644 kb |
Host | smart-ec4e2e93-1b76-41b0-9d89-6f6710b6f544 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2352235298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2352235298 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3949390965 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 2387876502 ps |
CPU time | 209.32 seconds |
Started | Jul 14 04:54:21 PM PDT 24 |
Finished | Jul 14 04:57:52 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-1982dace-528b-4b08-9ac7-8bc7da0eed8e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949390965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.3949390965 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.825235846 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 2060093099 ps |
CPU time | 164.63 seconds |
Started | Jul 14 04:54:30 PM PDT 24 |
Finished | Jul 14 04:57:15 PM PDT 24 |
Peak memory | 369240 kb |
Host | smart-c351bc89-5866-4ba0-9333-6a0dae862b42 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825235846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_throughput_w_partial_write.825235846 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.76782408 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 4360333691 ps |
CPU time | 310.59 seconds |
Started | Jul 14 04:54:38 PM PDT 24 |
Finished | Jul 14 04:59:49 PM PDT 24 |
Peak memory | 364312 kb |
Host | smart-ab339ee5-ed46-40a5-9204-0fd750013061 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76782408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.sram_ctrl_access_during_key_req.76782408 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.4091193372 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 45965993 ps |
CPU time | 0.65 seconds |
Started | Jul 14 04:54:38 PM PDT 24 |
Finished | Jul 14 04:54:39 PM PDT 24 |
Peak memory | 202280 kb |
Host | smart-a15aa8e8-d38f-45cf-a1a4-de71a251b173 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091193372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.4091193372 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.892582844 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 2606875085 ps |
CPU time | 56.5 seconds |
Started | Jul 14 04:54:32 PM PDT 24 |
Finished | Jul 14 04:55:29 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-d54fb6c9-b367-4927-bfed-44b2ab166f95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892582844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.892582844 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.2476373103 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 1945524991 ps |
CPU time | 838.4 seconds |
Started | Jul 14 04:54:39 PM PDT 24 |
Finished | Jul 14 05:08:38 PM PDT 24 |
Peak memory | 373516 kb |
Host | smart-966d1ff5-47ef-4969-bc0d-91dda0ceaa48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476373103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2476373103 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.451636199 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 2675378098 ps |
CPU time | 8.6 seconds |
Started | Jul 14 04:54:38 PM PDT 24 |
Finished | Jul 14 04:54:47 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-4c1dc1ca-e030-4545-b39c-8c2a085250b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451636199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca lation.451636199 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.2270677034 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 73547691 ps |
CPU time | 6.41 seconds |
Started | Jul 14 04:54:38 PM PDT 24 |
Finished | Jul 14 04:54:45 PM PDT 24 |
Peak memory | 235236 kb |
Host | smart-19f4ce7d-e04a-4d71-b2b2-45a5af820f20 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270677034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.2270677034 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2573636822 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 93065269 ps |
CPU time | 5.05 seconds |
Started | Jul 14 04:54:37 PM PDT 24 |
Finished | Jul 14 04:54:43 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-fe06a148-07b0-4ef7-ac6f-8be54f16250b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573636822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2573636822 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.3547427836 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 1118927827 ps |
CPU time | 4.99 seconds |
Started | Jul 14 04:54:39 PM PDT 24 |
Finished | Jul 14 04:54:45 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-341e2491-b8c2-4036-8b1c-b3a11fcff6d1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547427836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3547427836 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.2768597451 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 8202892734 ps |
CPU time | 1693.82 seconds |
Started | Jul 14 04:54:33 PM PDT 24 |
Finished | Jul 14 05:22:47 PM PDT 24 |
Peak memory | 375224 kb |
Host | smart-b54c5588-b690-46b4-94c4-936bd20b9e5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768597451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.2768597451 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3637618551 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 158561174 ps |
CPU time | 62.05 seconds |
Started | Jul 14 04:54:37 PM PDT 24 |
Finished | Jul 14 04:55:40 PM PDT 24 |
Peak memory | 313752 kb |
Host | smart-a895651a-22f2-4b60-8d95-b25e2e855b26 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637618551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3637618551 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2155113109 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 20753921212 ps |
CPU time | 438.23 seconds |
Started | Jul 14 04:54:37 PM PDT 24 |
Finished | Jul 14 05:01:56 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-565683c1-3182-44fb-b2bd-cc2f310c6c99 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155113109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.2155113109 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.2128467464 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 10790215799 ps |
CPU time | 1169.54 seconds |
Started | Jul 14 04:54:39 PM PDT 24 |
Finished | Jul 14 05:14:09 PM PDT 24 |
Peak memory | 373612 kb |
Host | smart-f236eef2-36cf-4747-b6ee-9026306ed2c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128467464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2128467464 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.4074189840 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 666554270 ps |
CPU time | 150.92 seconds |
Started | Jul 14 04:54:34 PM PDT 24 |
Finished | Jul 14 04:57:05 PM PDT 24 |
Peak memory | 366236 kb |
Host | smart-0fca8cf5-0869-4492-b680-e987d2a3e81d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074189840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4074189840 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3988730577 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 9223884693 ps |
CPU time | 386.77 seconds |
Started | Jul 14 04:54:37 PM PDT 24 |
Finished | Jul 14 05:01:04 PM PDT 24 |
Peak memory | 378776 kb |
Host | smart-6e9aa94f-13a7-469b-861f-a17d982f4ce7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3988730577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3988730577 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3626262930 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 1945345770 ps |
CPU time | 92.94 seconds |
Started | Jul 14 04:54:38 PM PDT 24 |
Finished | Jul 14 04:56:11 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-a4dda807-ed99-4856-a282-9b5eb9d3e317 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626262930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3626262930 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1736897629 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 104090588 ps |
CPU time | 4.92 seconds |
Started | Jul 14 04:54:36 PM PDT 24 |
Finished | Jul 14 04:54:42 PM PDT 24 |
Peak memory | 224252 kb |
Host | smart-fac78967-ec86-4ecb-a6ab-f7c2dd0255e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736897629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1736897629 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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